mister-devel/InputTest_MiSTer
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Working thing!

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This commit is contained in:
jimmystones
2021-06-22 21:25:57 +01:00
parent 80f89a50f8
commit 67cf451f71
41 changed files with 1838 additions and 3552 deletions
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126
InputTest.sv
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@@ -32,12 +32,14 @@ module emu
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
`ifdef MISTER_FB
// Use framebuffer in DDRAM (USE_FB=1 in qsf)
@@ -164,9 +166,9 @@ assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
assign VGA_SL = 0;
assign VGA_F1 = 0;
assign VGA_SCALER = 0;
assign HDMI_FREEZE = 0;
assign AUDIO_S = 0;
assign AUDIO_L = 0;
@@ -184,8 +186,6 @@ wire [1:0] ar = status[9:8];
assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
assign LED_USER = copy_in_progress;
`include "build_id.v"
localparam CONF_STR = {
"InputTest;;",
@@ -197,56 +197,118 @@ localparam CONF_STR = {
"V,v",`BUILD_DATE
};
//
// HPS is the module that communicates between the linux and fpga
//
wire [31:0] status;
wire [1:0] buttons;
wire forced_scandoubler;
wire direct_video;
hps_io #(.STRLEN(($size(CONF_STR)>>3)) , .PS2DIV(1000), .WIDE(0)) hps_io
wire ioctl_download;
wire ioctl_upload;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
wire [7:0] ioctl_index;
wire ioctl_wait;
wire [15:0] joystick_0, joystick_1;
wire [21:0] gamma_bus;
hps_io #(.CONF_STR(CONF_STR)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.status(status),
.conf_str(CONF_STR)
.buttons(buttons),
.status(status),
.status_menumask({direct_video}),
.forced_scandoubler(forced_scandoubler),
.direct_video(direct_video),
.ioctl_download(ioctl_download),
.ioctl_upload(ioctl_upload),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_din(ioctl_din),
.ioctl_index(ioctl_index),
.ioctl_wait(ioctl_wait),
.joystick_0(joystick_0),
.joystick_1(joystick_1)
);
///////////////////
// PLL - clocks are the most important part of a system
///////////////////////////////////////////////////
wire clk_sys, locked;
//////////////////// CLOCKS ///////////////////
wire clk_sys;
reg ce_pix;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys), // 25.116279 Mhz - for the vga pixel clock
.locked(locked)
.outclk_0(clk_sys)
);
/////////////////// CLOCK DIVIDER ////////////////////
always @(posedge clk_sys) begin
reg div;
div <= div + 1'd1;
ce_pix <= !div;
end
/////////////////// VIDEO ////////////////////
wire hblank, vblank;
wire hs, vs;
wire [7:0] r;
wire [7:0] g;
wire [7:0] b;
wire [23:0] rgb = {r,g,b};
arcade_video #(224,24) arcade_video
(
.*,
.clk_video(clk_sys),
.RGB_in(rgb),
.HBlank(hblank),
.VBlank(vblank),
.HSync(hs),
.VSync(vs),
.fx(status[5:3])
);
///////////////////////////////////////////////////
assign CLK_VIDEO = clk_sys;
assign CE_PIXEL = 1;
///////////////////////////////////////////////////
wire [3:0] r, g, b;
wire vs,hs;
wire ce_pix;
wire hblank, vblank;
wire rom_download = ioctl_download && (ioctl_index < 8'd2);
wire reset = (RESET | status[0] | buttons[1] | rom_download);
assign LED_USER = rom_download;
soc soc(
.clk_sys(clk_sys), // wrong
.pixel_clock(clk_sys), // wrong
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
.clk_sys(clk_sys),
.ce_pix(ce_pix),
.reset(reset | ioctl_download),
.VGA_HS(hs),
.VGA_VS(vs),
.VGA_R(r),
.VGA_G(g),
.VGA_B(b),
.VGA_HB(hblank),
.VGA_VB(vblank),
.dn_addr(ioctl_addr[13:0]),
.dn_data(ioctl_dout),
.dn_wr(ioctl_wr),
.dn_index(ioctl_index),
.inputs1(joystick_0[7:0]),
.inputs2(joystick_1[7:0])
);
endmodule

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MiSTer.pf Normal file
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19
README.MD
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@@ -1,14 +1,19 @@
# InputTest_MiSTer
## Overview
# Memory Map
## Memory Map
Start|End|Length|Name
---|---|---|---
0x0000|0x3FFF|0x4000|Program ROM
0x4000|0x43FF|0x0400|Char ROM
0x4000|0x47FF|0x0800|Char ROM
0x6000|0x6000|0x0001|System inputs (video timings etc)
0x6001|0x6001|0x0001|Control inputs
0x8000|0xBFFF|0x4000|Work RAM
0xC000|0xC3FF|0xDFFF|Char RAM
0x7000|0x70BF|0x00C0|Joystick inputs
0x8000|0x87FF|0x0800|Char RAM
0x8800|0x8FFF|0x0800|Colour RAM
0xC000|0xFFFF|0x4000|Work RAM

3
build.sh
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@@ -1,5 +1,6 @@
cd src
make
make clean
make all
cd ..
cd verilator
./verilate.sh

1
files.qip
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@@ -1,5 +1,4 @@
set_global_assignment -name SYSTEMVERILOG_FILE InputTest.sv
set_global_assignment -name QIP_FILE rtl/T80/t80.qip
set_global_assignment -name QIP_FILE rtl/tv80/TV80.qip
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip

0
src/font.bin → font.bin
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0
src/font.fnt → font.fnt
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font.pf Normal file
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4
ram4k.qip
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@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram4k.v"]

173
ram4k.v
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@@ -1,173 +0,0 @@
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram4k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram4k (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram4k_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

22
release/InputTest.mra Normal file
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@@ -0,0 +1,22 @@
<misterromdescription>
<name>Input Test</name>
<setname></setname>
<parent></parent>
<mameversion>0225</mameversion>
<rbf>InputTest</rbf>
<about></about>
<rom index="0" md5="none">
<part crc="none">
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</part>
</rom>
<rom index="1" md5="none">
<part crc="none">
00 00 00 00 00 00 00 00 FF 00 FF 00 FF 00 FF 00 00 FF 00 FF 00 FF 00 00 00 00 FF 00 FF 00 00 00 FE E6 AA C6 AA E6 FE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05 05 05 0D 0D 19 79 71 A0 A0 A0 B0 B0 98 9E 8E 03 0F 3F FF 3F 0F 03 00 C0 F0 FC FF FC F0 C0 00 00 00 18 3C 7E 18 18 00 00 00 18 18 7E 3C 18 00 00 00 FC FC FC 00 00 00 00 00 3F 3F 3F 00 00 00 00 00 60 78 7E 78 60 00 00 38 44 44 FE FE FE 00 00 06 09 09 FC FC FC 00 00 FE C6 C6 C6 FE 00 00 00 FE FE FE FE FE 00 00 00 00 18 18 00 00 00 00 38 38 10 FE 44 EE EE 00 7E 81 3C 42 18 24 00 18 06 0C 18 3E 7C 18 30 60 38 FE 82 82 FE FE FE 00 00 00 00 00 00 00 00 00 30 30 30 30 00 30 30 00 CC 44 88 00 00 00 00 00 68 68 FC 68 FC 68 68 00 00 08 7C D0 78 2C F8 40 00 64 A8 D0 2C 54 98 00 00 30 58 30 5A CC 76 00 30 10 20 00 00 00 00 00 0C 18 30 30 30 18 0C 00 C0 60 30 30 30 60 C0 00 00 48 30 FC 30 48 00 00 00 30 30 FC 30 30 00 00 00 00 00 00 00 30 10 20 00 00 00 FC 00 00 00 00 00 00 00 00 00 30 30 00 04 0C 18 30 60 C0 80 00 78 CC DC DC DC CC 78 00 70 30 30 30 30 30 30 00 F8 0C 0C 78 C0 C0 FC 00 F8 0C 0C 78 0C 0C F8 00 38 78 D8 D8 FC 18 18 00 FC C0 C0 F8 0C 0C F8 00 7C C0 C0 F8 CC CC 78 00 FC 0C 18 30 30 30 30 00 78 CC CC 78 CC CC 78 00 78 CC CC 7C 0C 0C F8 00 00 00 30 30 00 30 30 00 00 00 30 30 00 30 10 20 18 30 60 C0 60 30 18 00 00 00 78 00 78 00 00 00 60 30 18 0C 18 30 60 00 78 CC CC 18 30 00 30 00 78 CC DC DC D8 C0 7C 00 78 CC CC FC CC CC CC 00 F8 CC CC F8 CC CC F8 00 7C C0 C0 C0 C0 C0 7C 00 F8 CC CC CC CC CC F8 00 7C C0 C0 F0 C0 C0 7C 00 7C C0 C0 F0 C0 C0 C0 00 7C CC C0 DC CC CC 7C 00 CC CC CC FC CC CC CC 00 30 30 30 30 30 30 30 00 0C 0C 0C 0C 0C CC F8 00 CC CC D8 F0 D8 CC CC 00 C0 C0 C0 C0 C0 C0 7C 00 C6 EE FE D6 C6 C6 C6 00 CC CC EC FC DC CC CC 00 7C CC CC CC CC CC F8 00 F8 CC CC F8 C0 C0 C0 00 7C CC CC CC DC DC F8 18 F8 CC CC F8 CC CC CC 00 7C C0 C0 78 0C 0C F8 00 FC 30 30 30 30 30 30 00 CC CC CC CC CC CC 7C 00 CC CC CC CC CC 78 30 00 C6 C6 C6 D6 FE EE C6 00 CC CC 78 30 78 CC CC 00 CC CC CC 78 30 30 30 00 FC 0C 18 30 60 C0 FC 00 3C 30 30 30 30 30 3C 00 80 C0 60 30 18 0C 04 00 F0 30 30 30 30 30 F0 00 10 38 6C C6 00 00 00 00 00 00 00 00 00 00 00 FE 30 20 10 00 00 00 00 00 00 00 7C CC CC CC 7C 00 C0 C0 F8 CC CC CC 78 00 00 00 7C C0 C0 C0 7C 00 0C 0C 7C CC CC CC 78 00 00 00 78 CC FC C0 7C 00 1C 30 30 78 30 30 30 00 00 00 78 CC CC 7C 0C F8 C0 C0 F8 CC CC CC CC 00 30 00 30 30 30 30 30 00 30 00 30 30 30 30 30 E0 C0 C0 CC CC F8 CC CC 00 30 30 30 30 30 30 38 00 00 00 EC FE D6 C6 C6 00 00 00 F8 CC CC CC CC 00 00 00 78 CC CC CC 78 00 00 00 78 CC CC CC F8 C0 00 00 78 CC CC CC 7C 0C 00 00 DC E0 C0 C0 C0 00 00 00 7C C0 78 0C F8 00 30 30 78 30 30 30 1C 00 00 00 CC CC CC CC 7C 00 00 00 CC CC CC 78 30 00 00 00 C6 C6 D6 FE 6C 00 00 00 CC CC 30 CC CC 00 00 00 CC CC CC 7C 0C F8 00 00 FC 0C 30 C0 FC 00 1C 30 30 E0 30 30 1C 00 30 30 30 00 30 30 30 00 E0 30 30 1C 30 30 E0 00 72 9C 00 00 00 00 00 00 FE FE FE FE FE FE FE 00 00 00 00 15 00 10 00 10 00 00 00 55 00 00 00 00 00 00 00 50 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 50 00 00 00 00 00 10 00 15 00 00 00 00 00 00 00 1F 10 10 10 10 00 00 00 FF 00 00 00 00 00 00 00 F0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 F0 00 00 00 00 10 10 10 1F 00 00 00 00 FE 82 82 82 82 82 FE 00 12 34 F0 F6 F0 34 12 00 FE 82 82 82 82 FE FE 00 FE 82 82 82 FE FE FE 00 FE 82 82 FE FE FE FE 00 FE 82 FE FE FE FE FE 00 7C C6 44 C6 44 C6 7C 00 7C C6 44 CE 5C DE 7C 00 7C C6 44 FE 7C FE 7C 00 7C FE 7C FE 7C FE 7C 00 06 06 0C 0C D8 78 30 00
</part>
</rom>
<mratimestamp>202106162102</mratimestamp>
</misterromdescription>

10
rtl/pll.qip
View File

@@ -41,11 +41,11 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjUuMTE2Mjc5::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NC41::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA4::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Mjc=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjE1::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MzAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -256,7 +256,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjUuMTE2Mjc5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NC41MDAwMDAgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
@@ -318,7 +318,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NTQsNTQsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsMjIsMjEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwxLDIwLDEwMDAwLDEwODAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTQsMTMsMiwyLGZhbHNlLGZhbHNlLHRydWUsZmFsc2UsMzgsMzcsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDYwMDAsMzM3LjUgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

2
rtl/pll.v
View File

@@ -66,7 +66,7 @@ endmodule
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="25.116279" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="4.5" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />

2
rtl/pll/pll_0002.v
View File

@@ -19,7 +19,7 @@ module pll_0002(
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("25.116279 MHz"),
.output_clock_frequency0("4.500000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),

150
rtl/soc.v
View File

@@ -1,13 +1,16 @@
`timescale 1ns / 1ps
module soc (
input clk_sys,
input clk_pix,
input ce_pix,
input reset,
input [13:0] dn_addr,
input dn_wr,
input [7:0] dn_data,
input [7:0] dn_index,
input [7:0] inputs,
// 6 joysticks, 32 buttons each
input [191:0] joystick,
output VGA_HS,
output VGA_VS,
output [7:0] VGA_R,
@@ -17,6 +20,10 @@ module soc (
output VGA_VB
);
localparam [8:0] VGA_WIDTH = 9'd320;
localparam [8:0] VGA_HEIGHT = 9'd240;
localparam [7:0] COLS = 8'd40;
wire _hb;
wire _vb;
assign VGA_HB = ~_hb;
@@ -29,12 +36,12 @@ wire vinit;
// Display timing module from JTFRAME
jtframe_vtimer #(
.HB_START(9'd320),
.VB_START(9'd240)
.HB_START(VGA_WIDTH),
.VB_START(VGA_HEIGHT)
) vtimer
(
.clk(clk_sys),
.pxl_cen(clk_pix),
.pxl_cen(ce_pix),
.V(vcnt),
.H(hcnt),
.Hinit(hinit),
@@ -45,22 +52,21 @@ jtframe_vtimer #(
.VS(VGA_VS)
);
// DEBUG OUTPUT
assign VGA_R = hcnt[7:0];
assign VGA_G = vcnt[7:0];
assign VGA_B = voff;
// reg [7:0] hoff;
reg [7:0] voff;
always @(posedge clk_sys)
begin
if(vinit == 1'b1) voff <= voff + 8'b1;
// //if(hinit == 1'b1) hoff <= hoff + 8'b1;
// $display("%d %d", vrender, vrender1);
end
// Character map
wire [3:0] chpos_x = 4'd9 - hcnt[2:0];
wire [2:0] chpos_y = vcnt[2:0];
wire [5:0] chram_x = hcnt[8:3];
wire [5:0] chram_y = vcnt[8:3];
wire [11:0] chram_addr = {chram_y, chram_x};
wire [11:0] colram_addr = chram_addr;
wire [11:0] chrom_addr = {1'b0, chram_data_out[7:0], chpos_y};
wire [5:0] chraindex = 6'd33;
wire chpixel = chrom_data_out[chpos_x[2:0]];
// RGB output
assign VGA_R = chpixel ? {{2{colram_data_out[2:0]}},2'b0} : 8'b0;
assign VGA_G = chpixel ? {{2{colram_data_out[5:3]}},2'b0} : 8'b0;
assign VGA_B = chpixel ? {{3{colram_data_out[7:6]}},2'b0} : 8'b0;
// CPU control signals
wire [15:0] cpu_addr;
@@ -96,30 +102,56 @@ wire [7:0] pgrom_data_out;
wire [7:0] chrom_data_out;
wire [7:0] wkram_data_out;
wire [7:0] chram_data_out;
wire [7:0] colram_data_out;
// RAM bank data outs
wire [10:0] chrom_addr;
// Hardware inputs
wire [7:0] in0_data_out = {VGA_HS, VGA_VS, 6'b101000};
wire [7:0] joystick_bit = cpu_addr[7:0];
//wire [7:0] joystick_low_bit = joystick_high_bit - 8'd8;
//[8*(0) +: 8]
wire [7:0] joystick_data_out = joystick[joystick_bit +: 8];
// CPU address decodes
wire pgrom_cs = cpu_addr[15:14] == 2'b00;
wire chrom_cs = cpu_addr[15:14] == 2'b00;
wire wkram_cs = cpu_addr[15] == 1'b1;
wire chram_cs = cpu_addr[15] == 1'b1;
wire in0_cs = cpu_addr == 16'h4000;
wire in1_cs = cpu_addr == 16'h4001;
wire chrom_cs = cpu_addr[15:12] == 4'b0100;
wire chram_cs = cpu_addr[15:11] == 5'b10000;
wire colram_cs = cpu_addr[15:11] == 5'b10001;
wire wkram_cs = cpu_addr[15:14] == 2'b11;
wire in0_cs = cpu_addr == 16'h6000;
wire joystick_cs = cpu_addr[15:11] == 5'b01110;
always @(posedge clk_sys) begin
if(joystick_cs) $display("%b %b", joystick_bit, joystick_data_out);
// if(pgrom_cs) $display("%x pgrom o %x", cpu_addr, pgrom_data_out);
// if(wkram_cs) $display("%x wkram i %x o %x w %b", cpu_addr, cpu_dout, wkram_data_out, wkram_wr);
// if(chram_cs) $display("%x chram i %x o %x w %b", cpu_addr, cpu_dout, chram_data_out, chram_wr);
// if(colram_cs) $display("%x colram i %x o %x w %b", cpu_addr, cpu_dout, colram_data_out, colram_wr);
// if(in0_cs) $display("%x in0 i %x o %x", cpu_addr, cpu_dout, in0_data_out);
// if(in1_cs) $display("%x in1 i %x o %x", cpu_addr, cpu_dout, inputs);
// if(!pgrom_cs && !wkram_cs && !chram_cs && !in0_cs && !in1_cs) $display("%x ??? i %x", cpu_addr, cpu_dout);
end
// CPU data mux
assign cpu_din = pgrom_cs ? pgrom_data_out :
wkram_cs ? wkram_data_out :
wkram_cs ? wkram_data_out :
in0_cs ? {VGA_HS, VGA_VS, 6'b101000} :
in1_cs ? inputs :
chram_cs ? chram_data_out :
colram_cs ? colram_data_out :
in0_cs ? in0_data_out :
joystick_cs ? joystick_data_out :
// in2_cs ? inputs2 :
8'b00000000;
// Rom upload write enables
wire pgrom_wr = dn_wr && dn_index == 8'b0;
wire chrom_wr = dn_wr && dn_index == 8'b1;
// Ram write enables
wire wkram_wr = !cpu_wr_n && wkram_cs;
wire chram_wr = !cpu_wr_n && chram_cs;
wire colram_wr = !cpu_wr_n && colram_cs;
// MEMORY
// ------
@@ -140,11 +172,11 @@ dpram #(14,8) pgrom
.q_b()
);
// Char ROM - 0x4000 - 0x43FF (0x0400 / 1024 bytes)
// Char ROM - 0x4000 - 0x47FF (0x0400 / 2048 bytes)
dpram #(11,8) chrom
(
.clock_a(clk_sys),
.address_a(chrom_addr),
.address_a(chrom_addr[10:0]),
.wren_a(1'b0),
.data_a(),
.q_a(chrom_data_out),
@@ -156,31 +188,47 @@ dpram #(11,8) chrom
.q_b()
);
// Work RAM - 0x8000 - 0xBFFF (0x4000 / 16384 bytes)
// Char RAM - 0x8000 - 0x87FF (0x0800 / 2048 bytes)
dpram #(11,8) chram
(
.clock_a(clk_sys),
.address_a(cpu_addr[10:0]),
.wren_a(chram_wr),
.data_a(cpu_dout),
.q_a(),
.clock_b(clk_sys),
.address_b(chram_addr[10:0]),
.wren_b(1'b0),
.data_b(),
.q_b(chram_data_out)
);
// Char color RAM - 0x8800 - 0x8FFF (0x0800 / 2048 bytes)
dpram #(11,8) colram
(
.clock_a(clk_sys),
.address_a(cpu_addr[10:0]),
.wren_a(colram_wr),
.data_a(cpu_dout),
.q_a(),
.clock_b(clk_sys),
.address_b(colram_addr[10:0]),
.wren_b(1'b0),
.data_b(),
.q_b(colram_data_out)
);
// Work RAM - 0xC000 - 0xFFFF (0x4000 / 16384 bytes)
spram #(14,8) wkram
(
.clock(clk_sys),
.address(cpu_addr[13:0]),
.wren(!cpu_wr_n && wkram_cs),
.wren(wkram_wr),
.data(cpu_dout),
.q(wkram_data_out)
);
// Char RAM - 0xC000 - 0xDFFF (0x2000 / 8192 bytes)
dpram #(13,8) chram
(
.clock_a(clk_sys),
.address_a(cpu_addr[12:0]),
.wren_a(!cpu_wr_n && chram_cs),
.data_a(cpu_dout),
.q_a(chram_data_out),
.clock_b(clk_sys),
.address_b(),
.wren_b(1'b0),
.data_b(),
.q_b()
);
endmodule

8
src/Makefile
View File

@@ -1,15 +1,17 @@
SDCC=sdcc
CPU=z80
CODE=boot_rom
OBJ=boot_rom.rel font.rel
OBJ=boot_rom.rel
DATALOC=0xC000
#DATALOC=0x8000
all: $(CODE).bin
%.rel: %.c
$(SDCC) -m$(CPU) -c $<
$(SDCC) -m$(CPU) -c --data-loc $(DATALOC) $<
%.ihx: $(OBJ)
$(SDCC) -m$(CPU) $(OBJ)
$(SDCC) -m$(CPU) --data-loc $(DATALOC) $(OBJ)
%.hex: %.ihx
mv $< $@

1007
src/boot_rom.asm
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File diff suppressed because it is too large Load Diff

BIN
src/boot_rom.bin
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Binary file not shown.

204
src/boot_rom.c
View File

@@ -1,146 +1,114 @@
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <stdlib.h> // for abs()
extern unsigned char font[];
// Memory maps
unsigned char __at(0x6000) input0;
unsigned char __at(0x7000) joystick[24];
unsigned char __at(0x8000) chram[2048];
unsigned char __at(0x8800) colram[2048];
const unsigned int VGA_WIDTH = 160;
const unsigned int VGA_HEIGHT = 100;
// Character map
const unsigned char chram_cols = 64;
const unsigned char chram_rows = 32;
unsigned int chram_size;
unsigned char __at (0x6000) input0;
unsigned char __at (0x6001) input1;
unsigned char y = 0;
unsigned char hsync;
unsigned char hsync_last;
unsigned char vsync;
unsigned char vsync_last;
unsigned char input0_cache;
unsigned char input1_cache;
unsigned char color;
unsigned char cur_x=0, cur_y=0;
int putchar(int c) {
unsigned char *p;
unsigned char *dptr = (unsigned char*)(160*(8*cur_y) + 8*cur_x);
char i, j;
if(c < 32) {
if(c == '\r')
cur_x=0;
if(c == '\n') {
cur_y++;
cur_x=0;
if(cur_y >= 12)
cur_y = 0;
}
return;
}
if(c < 0) return;
p = font+8*(unsigned char)(c-32);
for(i=0;i<8;i++) {
unsigned char l = *p++;
for(j=0;j<8;j++) {
*dptr++ = (l & 0x80)?color:0x00;
l <<= 1;
}
dptr += (160-8);
}
cur_x++;
if(cur_x >= 20) {
cur_x = 0;
cur_y++;
if(cur_y >= 12)
cur_y = 0;
}
void clear_chars()
{
for (unsigned int p = 0; p < chram_size; p++)
{
chram[p] = 0;
}
}
// draw a pixel
void put_pixel(unsigned int x, unsigned int y, unsigned char color) {
*((unsigned int*)(VGA_WIDTH*y+x)) = color;
void write_string(const char *string, char color, unsigned int x, unsigned int y)
{
unsigned int p = (y * chram_cols) + x;
unsigned char l = strlen(string);
for (char c = 0; c < l; c++)
{
chram[p] = string[c];
colram[p] = color;
p++;
}
}
void cls(unsigned char color) {
unsigned char i;
unsigned int *p = (unsigned int*)0;
for(i=0;i<VGA_HEIGHT;i++) {
memset(p, color, VGA_WIDTH);
p += VGA_WIDTH;
}
void write_char(unsigned char c, char color, unsigned int x, unsigned int y)
{
unsigned int p = (y * chram_cols) + x;
chram[p] = c;
colram[p] = color;
}
// bresenham algorithm to draw a line
void draw_line(unsigned int x, unsigned int y,
unsigned int x2, unsigned int y2,
unsigned char color) {
unsigned int longest, shortest, numerator, i;
int dx1 = (x<x2)?1:-1;
int dy1 = (y<y2)?1:-1;
int dx2, dy2;
longest = abs(x2 - x);
shortest = abs(y2 - y);
if(longest<shortest) {
longest = abs(y2 - y);
shortest = abs(x2 - x);
dx2 = 0;
dy2 = dy1;
} else {
dx2 = dx1;
dy2 = 0;
}
numerator = longest/2;
for(i=0;i<=longest;i++) {
put_pixel(x,y,color) ;
if(numerator >= longest-shortest) {
numerator += shortest ;
numerator -= longest ;
x += dx1;
y += dy1;
} else {
numerator += shortest ;
x += dx2;
y += dy2;
}
}
void page_border(char color)
{
write_char(128, color, 0, 0);
write_char(130, color, 39, 0);
write_char(133, color, 0, 29);
write_char(132, color, 39, 29);
for (char x = 1; x < 39; x++)
{
write_char(129, color, x, 0);
write_char(129, color, x, 29);
}
for (char y = 1; y < 29; y++)
{
write_char(131, color, 0, y);
write_char(131, color, 39, y);
}
}
char color = 0x66;
void page_inputs()
{
clear_chars();
page_border(0b00000111);
write_string("UDLR", 0xFF, 9, 3);
write_string("JOY 1)", 0xF0, 2, 4);
write_string("JOY 2)", 0xE0, 2, 5);
}
void main() {
while(1) {
char asc_0 = 48;
char asc_1 = 49;
// get inputs
input0_cache = input0;
hsync = input0_cache & 0x80;
vsync = input0_cache & 0x40;
void main()
{
chram_size = chram_cols * chram_rows;
char color = 0xAB;
page_inputs();
if(hsync && !hsync_last){
y++;
}
if(vsync && !vsync_last){
y=0;
while (1)
{
hsync = input0 & 0x80;
vsync = input0 & 0x40;
cur_x = 0;
cur_y = 0;
// if(hsync && !hsync_last){
// }
if (vsync && !vsync_last)
{
color++;
cls(~color);
puts(" << Z80 SoC >>\n");
// process inputs
input1_cache = input1;
write_string("--- MiSTer Input Tester ---", color, 6, 1);
for (char b = 0; b < 2; b++)
{
char m = 0b00000001;
for (char i = 0; i < 8; i++)
{
char x = 9 + i + (b * 10);
for (char j = 0; j < 3; j++)
{
write_char((joystick[b + (j * 32)] & m) ? asc_1 : asc_0, 0xFF, x, 4 + j);
}
m <<= 1;
}
}
}
hsync_last = hsync;
vsync_last = vsync;
}
}
}

3
src/boot_rom.lk
View File

@@ -1,12 +1,11 @@
-mjwx
-i boot_rom.ihx
-b _CODE = 0x0200
-b _DATA = 0x8000
-b _DATA = 0xc000
-k /usr/bin/../share/sdcc/lib/z80
-k /usr/share/sdcc/lib/z80
-l z80
/usr/bin/../share/sdcc/lib/z80/crt0.rel
boot_rom.rel
font.rel
-e

1211
src/boot_rom.lst
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File diff suppressed because it is too large Load Diff

93
src/boot_rom.map
View File

@@ -7,7 +7,7 @@ Area Addr Size Decimal Bytes (A
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000000 .__.ABS. puts
00000000 .__.ABS.
00000000 l__BSEG
00000000 l__BSS
00000000 l__CABS
@@ -28,6 +28,8 @@ Area Addr Size Decimal Bytes (A
00000000 s__HEADER7
00000000 s__HEADER8
00000001 l__GSFINAL
00000002 l__INITIALIZED
00000002 l__INITIALIZER
00000003 l__HEADER0
00000003 l__HEADER2
00000003 l__HEADER3
@@ -40,44 +42,43 @@ Area Addr Size Decimal Bytes (A
0000000C l__HEADER8
0000000F l__GSINIT
00000200 s__CODE
00000304 l__INITIALIZED
00000304 l__INITIALIZER
00000447 l__CODE
00000647 s__HOME
00000647 s__INITIALIZER
0000094B s__GSINIT
0000095A s__GSFINAL
0000033E l__CODE
0000053E s__HOME
0000053E s__INITIALIZER
00000540 s__GSINIT
0000054F s__GSFINAL
00006000 _input0 boot_rom
00006001 _input1 boot_rom
00008000 s__DATA
00008006 s__INITIALIZED
0000830A s__BSEG
0000830A s__BSS
0000830A s__HEAP
00007000 _joystick boot_rom
00008000 _chram boot_rom
00008800 _colram boot_rom
0000C000 s__DATA
0000C006 s__INITIALIZED
0000C008 s__BSEG
0000C008 s__BSS
0000C008 s__HEAP
ASxxxx Linker V03.00 + NoICE + sdld, page 2.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_CODE 00000200 00000447 = 1095. bytes (REL,CON)
_CODE 00000200 0000033E = 830. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000200 __clock crt0
00000204 _exit crt0
0000020A _putchar boot_rom
0000031A _VGA_WIDTH boot_rom
0000031C _VGA_HEIGHT boot_rom
0000031E _put_pixel boot_rom
00000351 _cls boot_rom
00000397 _draw_line boot_rom
0000054E _main boot_rom
000005D0 _abs
000005DC __mulint
000005E2 __mul16
000005F6 _memset _memset
00000621 _puts puts
0000020A _clear_chars boot_rom
0000021F _chram_cols boot_rom
00000220 _chram_rows boot_rom
00000221 _write_string boot_rom
0000027E _write_char boot_rom
000002B7 _page_border boot_rom
00000382 _page_inputs boot_rom
000003E6 _main boot_rom
00000515 __mulint
0000051B __mul16
0000052F _strlen
ASxxxx Linker V03.00 + NoICE + sdld, page 3.
Hexadecimal [32-Bits]
@@ -165,7 +166,7 @@ Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_INITIALIZER 00000647 00000304 = 772. bytes (REL,CON)
_INITIALIZER 0000053E 00000002 = 2. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
@@ -174,18 +175,18 @@ Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSINIT 0000094B 0000000F = 15. bytes (REL,CON)
_GSINIT 00000540 0000000F = 15. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
0000094B gsinit crt0
00000540 gsinit crt0
ASxxxx Linker V03.00 + NoICE + sdld, page 14.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_GSFINAL 0000095A 00000001 = 1. bytes (REL,CON)
_GSFINAL 0000054F 00000001 = 1. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
@@ -194,30 +195,27 @@ Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_DATA 00008000 00000006 = 6. bytes (REL,CON)
_DATA 0000C000 00000006 = 6. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008000 _hsync boot_rom
00008001 _hsync_last boot_rom
00008002 _vsync boot_rom
00008003 _vsync_last boot_rom
00008004 _input0_cache boot_rom
00008005 _input1_cache boot_rom
0000C000 _chram_size boot_rom
0000C002 _hsync boot_rom
0000C003 _hsync_last boot_rom
0000C004 _vsync boot_rom
0000C005 _vsync_last boot_rom
ASxxxx Linker V03.00 + NoICE + sdld, page 16.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
_INITIALIZED 00008006 00000304 = 772. bytes (REL,CON)
_INITIALIZED 0000C006 00000002 = 2. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008006 _y boot_rom
00008007 _cur_x boot_rom
00008008 _cur_y boot_rom
00008009 _color boot_rom
0000800A _font font
0000C006 _asc_0 boot_rom
0000C007 _asc_1 boot_rom
ASxxxx Linker V03.00 + NoICE + sdld, page 17.
@@ -225,21 +223,18 @@ Files Linked [ module(s) ]
/usr/bin/../share/sdcc/lib/z80/crt0.rel [ crt0 ]
boot_rom.rel [ boot_rom ]
font.rel [ font ]
Libraries Linked [ object file ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ abs.rel ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ mul.rel ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ _memset.rel ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ puts.rel ]
/usr/bin/../share/sdcc/lib/z80/z80.lib [ strlen.rel ]
ASxxxx Linker V03.00 + NoICE + sdld, page 18.
User Base Address Definitions
_CODE = 0x0200
_DATA = 0x8000
_DATA = 0xc000

71
src/boot_rom.noi
View File

@@ -19,6 +19,8 @@ DEF s__HEADER6 0x0
DEF s__HEADER7 0x0
DEF s__HEADER8 0x0
DEF l__GSFINAL 0x1
DEF l__INITIALIZED 0x2
DEF l__INITIALIZER 0x2
DEF l__HEADER0 0x3
DEF l__HEADER2 0x3
DEF l__HEADER3 0x3
@@ -31,44 +33,39 @@ DEF l__DATA 0x6
DEF l__HEADER8 0xC
DEF l__GSINIT 0xF
DEF s__CODE 0x200
DEF l__INITIALIZED 0x304
DEF l__INITIALIZER 0x304
DEF l__CODE 0x447
DEF s__HOME 0x647
DEF s__INITIALIZER 0x647
DEF s__GSINIT 0x94B
DEF s__GSFINAL 0x95A
DEF l__CODE 0x33E
DEF s__HOME 0x53E
DEF s__INITIALIZER 0x53E
DEF s__GSINIT 0x540
DEF s__GSFINAL 0x54F
DEF _input0 0x6000
DEF _input1 0x6001
DEF s__DATA 0x8000
DEF s__INITIALIZED 0x8006
DEF s__BSEG 0x830A
DEF s__BSS 0x830A
DEF s__HEAP 0x830A
DEF _joystick 0x7000
DEF _chram 0x8000
DEF _colram 0x8800
DEF s__DATA 0xC000
DEF s__INITIALIZED 0xC006
DEF s__BSEG 0xC008
DEF s__BSS 0xC008
DEF s__HEAP 0xC008
DEF __clock 0x200
DEF _exit 0x204
DEF _putchar 0x20A
DEF _VGA_WIDTH 0x31A
DEF _VGA_HEIGHT 0x31C
DEF _put_pixel 0x31E
DEF _cls 0x351
DEF _draw_line 0x397
DEF _main 0x54E
DEF _abs 0x5D0
DEF __mulint 0x5DC
DEF __mul16 0x5E2
DEF _memset 0x5F6
DEF _puts 0x621
DEF gsinit 0x94B
DEF _hsync 0x8000
DEF _hsync_last 0x8001
DEF _vsync 0x8002
DEF _vsync_last 0x8003
DEF _input0_cache 0x8004
DEF _input1_cache 0x8005
DEF _y 0x8006
DEF _cur_x 0x8007
DEF _cur_y 0x8008
DEF _color 0x8009
DEF _font 0x800A
DEF _clear_chars 0x20A
DEF _chram_cols 0x21F
DEF _chram_rows 0x220
DEF _write_string 0x221
DEF _write_char 0x27E
DEF _page_border 0x2B7
DEF _page_inputs 0x382
DEF _main 0x3E6
DEF __mulint 0x515
DEF __mul16 0x51B
DEF _strlen 0x52F
DEF gsinit 0x540
DEF _chram_size 0xC000
DEF _hsync 0xC002
DEF _hsync_last 0xC003
DEF _vsync 0xC004
DEF _vsync_last 0xC005
DEF _asc_0 0xC006
DEF _asc_1 0xC007
LOAD boot_rom.ihx

59
src/boot_rom.sym
View File

@@ -7,48 +7,47 @@ Symbol Table
.__.ABS. = 0000 G
.__.CPU. = 0000 L
.__.H$L. = 0000 L
0 _VGA_HEIGHT 0112 GR
0 _VGA_WIDTH 0110 GR
0 ___str_0 03B6 R
0 ___str_0 01C9 R
0 ___str_1 01CE R
0 ___str_2 01D5 R
0 ___str_3 02EF R
__mulint **** GX
7 __xinit__color 0003 R
7 __xinit__cur_x 0001 R
7 __xinit__cur_y 0002 R
7 __xinit__y 0000 R
_abs **** GX
0 _cls 0147 GR
2 _color 0003 GR
2 _cur_x 0001 GR
2 _cur_y 0002 GR
0 _draw_line 018D GR
_font **** GX
1 _hsync 0000 GR
1 _hsync_last 0001 GR
7 __xinit__asc_0 0000 R
7 __xinit__asc_1 0001 R
2 _asc_0 0000 GR
2 _asc_1 0001 GR
_chram = 8000 G
0 _chram_cols 0015 GR
0 _chram_rows 0016 GR
1 _chram_size 0000 GR
0 _clear_chars 0000 GR
_colram = 8800 G
1 _hsync 0002 GR
1 _hsync_last 0003 GR
_input0 = 6000 G
1 _input0_cache 0004 GR
_input1 = 6001 G
1 _input1_cache 0005 GR
0 _main 0344 GR
_memset **** GX
0 _put_pixel 0114 GR
0 _putchar 0000 GR
_puts **** GX
1 _vsync 0002 GR
1 _vsync_last 0003 GR
2 _y 0000 GR
_joystick = 7000 G
0 _main 01DC GR
0 _page_border 00AD GR
0 _page_inputs 0178 GR
_strlen **** GX
1 _vsync 0004 GR
1 _vsync_last 0005 GR
0 _write_char 0074 GR
0 _write_string 0017 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 2.
Hexadecimal [16-Bits]
Area Table
0 _CODE size 3C6 flags 0
0 _CODE size 30B flags 0
1 _DATA size 6 flags 0
2 _INITIALIZED size 4 flags 0
2 _INITIALIZED size 2 flags 0
3 _DABS size 0 flags 8
4 _HOME size 0 flags 0
5 _GSINIT size 0 flags 0
6 _GSFINAL size 0 flags 0
7 _INITIALIZER size 4 flags 0
7 _INITIALIZER size 2 flags 0
8 _CABS size 0 flags 8

816
src/font.asm
View File

@@ -1,816 +0,0 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.8.0 #10562 (Linux)
;--------------------------------------------------------
.module font
.optsdcc -mz80
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _font
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area _INITIALIZED
_font::
.ds 768
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area _DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area _HOME
.area _GSINIT
.area _GSFINAL
.area _GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area _HOME
.area _HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area _CODE
.area _CODE
.area _INITIALIZER
__xinit__font:
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x78 ; 120 'x'
.db #0x78 ; 120 'x'
.db #0x78 ; 120 'x'
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0xcc ; 204
.db #0x66 ; 102 'f'
.db #0x33 ; 51 '3'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x36 ; 54 '6'
.db #0x7f ; 127
.db #0x36 ; 54 '6'
.db #0x36 ; 54 '6'
.db #0x7f ; 127
.db #0x36 ; 54 '6'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xd6 ; 214
.db #0xd0 ; 208
.db #0x7c ; 124
.db #0x16 ; 22
.db #0xd6 ; 214
.db #0x7c ; 124
.db #0x10 ; 16
.db #0xe3 ; 227
.db #0xa6 ; 166
.db #0xec ; 236
.db #0x18 ; 24
.db #0x37 ; 55 '7'
.db #0x65 ; 101 'e'
.db #0xc7 ; 199
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x4c ; 76 'L'
.db #0x38 ; 56 '8'
.db #0x45 ; 69 'E'
.db #0xc6 ; 198
.db #0xce ; 206
.db #0x7a ; 122 'z'
.db #0x01 ; 1
.db #0x06 ; 6
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x10 ; 16
.db #0x54 ; 84 'T'
.db #0x38 ; 56 '8'
.db #0xfe ; 254
.db #0x38 ; 56 '8'
.db #0x54 ; 84 'T'
.db #0x10 ; 16
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x7e ; 126
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x03 ; 3
.db #0x06 ; 6
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xde ; 222
.db #0xfe ; 254
.db #0xee ; 238
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x1c ; 28
.db #0x3c ; 60
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0x0e ; 14
.db #0x3c ; 60
.db #0x0e ; 14
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0xfe ; 254
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfc ; 252
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x06 ; 6
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xc6 ; 198
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xc6 ; 198
.db #0xde ; 222
.db #0xde ; 222
.db #0xdc ; 220
.db #0xc0 ; 192
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xee ; 238
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x0e ; 14
.db #0xce ; 206
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xec ; 236
.db #0xf8 ; 248
.db #0xf0 ; 240
.db #0xf8 ; 248
.db #0xec ; 236
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xee ; 238
.db #0xfe ; 254
.db #0xd6 ; 214
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xe6 ; 230
.db #0xf6 ; 246
.db #0xfe ; 254
.db #0xee ; 238
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xea ; 234
.db #0x74 ; 116 't'
.db #0x02 ; 2
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0x7c ; 124
.db #0x0e ; 14
.db #0xce ; 206
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xc6 ; 198
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xfe ; 254
.db #0xfc ; 252
.db #0x00 ; 0
.db #0xe3 ; 227
.db #0x76 ; 118 'v'
.db #0x3c ; 60
.db #0x18 ; 24
.db #0x3c ; 60
.db #0x6e ; 110 'n'
.db #0xc7 ; 199
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x0e ; 14
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xe0 ; 224
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x1c ; 28
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x1c ; 28
.db #0x00 ; 0
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x06 ; 6
.db #0x03 ; 3
.db #0x00 ; 0
.db #0x70 ; 112 'p'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x70 ; 112 'p'
.db #0x18 ; 24
.db #0x3c ; 60
.db #0x66 ; 102 'f'
.db #0xc3 ; 195
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xff ; 255
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0x0e ; 14
.db #0x7e ; 126
.db #0xce ; 206
.db #0x7e ; 126
.db #0x00 ; 0
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x06 ; 6
.db #0x06 ; 6
.db #0x7e ; 126
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xfe ; 254
.db #0xe0 ; 224
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x3c ; 60
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0xfc ; 252
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0x70 ; 112 'p'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x7c ; 124
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0x1c ; 28
.db #0xf8 ; 248
.db #0xc0 ; 192
.db #0xc0 ; 192
.db #0xcc ; 204
.db #0xd8 ; 216
.db #0xf0 ; 240
.db #0xd8 ; 216
.db #0xcc ; 204
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7c ; 124
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xfc ; 252
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0x0e ; 14
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfc ; 252
.db #0xe6 ; 230
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0xe0 ; 224
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x7e ; 126
.db #0xe0 ; 224
.db #0x7c ; 124
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x7e ; 126
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x7e ; 126
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0xe6 ; 230
.db #0x6c ; 108 'l'
.db #0x38 ; 56 '8'
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xd6 ; 214
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xe6 ; 230
.db #0x7c ; 124
.db #0x38 ; 56 '8'
.db #0x7c ; 124
.db #0xce ; 206
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xce ; 206
.db #0xce ; 206
.db #0xce ; 206
.db #0x7e ; 126
.db #0x0e ; 14
.db #0xfc ; 252
.db #0x00 ; 0
.db #0x00 ; 0
.db #0xfe ; 254
.db #0x1c ; 28
.db #0x38 ; 56 '8'
.db #0x70 ; 112 'p'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x0c ; 12
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x0c ; 12
.db #0x00 ; 0
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x18 ; 24
.db #0x60 ; 96
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x18 ; 24
.db #0x30 ; 48 '0'
.db #0x30 ; 48 '0'
.db #0x60 ; 96
.db #0x00 ; 0
.db #0x70 ; 112 'p'
.db #0xdb ; 219
.db #0x0e ; 14
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x00 ; 0
.db #0x10 ; 16
.db #0x28 ; 40
.db #0x44 ; 68 'D'
.db #0xfe ; 254
.db #0x00 ; 0
.db #0x00 ; 0
.area _CABS (ABS)

101
src/font.c
View File

@@ -1,101 +0,0 @@
/* Autogenerated file, DO NOT EDIT !!! */
unsigned char font[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x30, 0x78, 0x78, 0x78, 0x30, 0x00, 0x30, 0x00,
0xCC, 0x66, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x36, 0x7F, 0x36, 0x36, 0x7F, 0x36, 0x00,
0x7C, 0xD6, 0xD0, 0x7C, 0x16, 0xD6, 0x7C, 0x10,
0xE3, 0xA6, 0xEC, 0x18, 0x37, 0x65, 0xC7, 0x00,
0x38, 0x4C, 0x38, 0x45, 0xC6, 0xCE, 0x7A, 0x01,
0x06, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0C,
0x60, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x60,
0x10, 0x54, 0x38, 0xFE, 0x38, 0x54, 0x10, 0x00,
0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x30,
0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00,
0x00, 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00,
0x7C, 0xCE, 0xDE, 0xFE, 0xEE, 0xCE, 0x7C, 0x00,
0x1C, 0x3C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x00,
0x7C, 0xCE, 0x0E, 0x1C, 0x38, 0x70, 0xFE, 0x00,
0x7C, 0xCE, 0x0E, 0x3C, 0x0E, 0xCE, 0x7C, 0x00,
0xCE, 0xCE, 0xCE, 0xCE, 0xFE, 0x0E, 0x0E, 0x00,
0xFE, 0xE0, 0xE0, 0xFC, 0x0E, 0x0E, 0xFC, 0x00,
0x7C, 0xE6, 0xE0, 0xFC, 0xE6, 0xE6, 0x7C, 0x00,
0xFE, 0x06, 0x0E, 0x1C, 0x38, 0x38, 0x38, 0x00,
0x7C, 0xE6, 0xE6, 0x7C, 0xE6, 0xE6, 0x7C, 0x00,
0x7C, 0xCE, 0xCE, 0x7E, 0x0E, 0x0E, 0xFC, 0x00,
0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00,
0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x60, 0x00,
0x00, 0x18, 0x30, 0x60, 0x30, 0x18, 0x00, 0x00,
0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00,
0x00, 0x30, 0x18, 0x0C, 0x18, 0x30, 0x00, 0x00,
0x7C, 0xC6, 0x0E, 0x1C, 0x38, 0x00, 0x38, 0x00,
0x7C, 0xC6, 0xDE, 0xDE, 0xDC, 0xC0, 0x7C, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xFE, 0xE6, 0xE6, 0x00,
0xFC, 0xE6, 0xE6, 0xFC, 0xE6, 0xE6, 0xFC, 0x00,
0x7C, 0xE6, 0xE0, 0xE0, 0xE6, 0xE6, 0x7C, 0x00,
0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xFC, 0x00,
0xFE, 0xE0, 0xE0, 0xFE, 0xE0, 0xE0, 0xFE, 0x00,
0xFE, 0xE0, 0xE0, 0xFE, 0xE0, 0xE0, 0xE0, 0x00,
0x7C, 0xE6, 0xE0, 0xEE, 0xE6, 0xE6, 0x7C, 0x00,
0xE6, 0xE6, 0xE6, 0xFE, 0xE6, 0xE6, 0xE6, 0x00,
0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0x0E, 0x0E, 0x0E, 0x0E, 0xCE, 0xCE, 0x7C, 0x00,
0xE6, 0xEC, 0xF8, 0xF0, 0xF8, 0xEC, 0xE6, 0x00,
0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xFE, 0x00,
0xC6, 0xEE, 0xFE, 0xD6, 0xC6, 0xC6, 0xC6, 0x00,
0xC6, 0xE6, 0xF6, 0xFE, 0xEE, 0xE6, 0xE6, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0xFC, 0xE6, 0xE6, 0xFC, 0xE0, 0xE0, 0xE0, 0x00,
0x7C, 0xE6, 0xE6, 0xE6, 0xE6, 0xEA, 0x74, 0x02,
0xFC, 0xE6, 0xE6, 0xFC, 0xE6, 0xE6, 0xE6, 0x00,
0x7C, 0xE6, 0xE0, 0x7C, 0x0E, 0xCE, 0x7C, 0x00,
0xFE, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0x7C, 0x38, 0x00,
0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0xFE, 0xFC, 0x00,
0xE3, 0x76, 0x3C, 0x18, 0x3C, 0x6E, 0xC7, 0x00,
0xE6, 0xE6, 0x7C, 0x38, 0x38, 0x38, 0x38, 0x00,
0xFE, 0x0E, 0x1C, 0x38, 0x70, 0xE0, 0xFE, 0x00,
0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1C,
0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x00,
0x70, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x70,
0x18, 0x3C, 0x66, 0xC3, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
0x30, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x7C, 0x0E, 0x7E, 0xCE, 0x7E, 0x00,
0xC0, 0xC0, 0xFC, 0xE6, 0xE6, 0xE6, 0xFC, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xE0, 0xE6, 0x7C, 0x00,
0x06, 0x06, 0x7E, 0xCE, 0xCE, 0xCE, 0x7E, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xFE, 0xE0, 0x7E, 0x00,
0x3C, 0x70, 0x70, 0xFC, 0x70, 0x70, 0x70, 0x00,
0x00, 0x00, 0x7C, 0xCE, 0xCE, 0x7E, 0x0E, 0x7C,
0xC0, 0xC0, 0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0x00,
0x18, 0x00, 0x18, 0x38, 0x38, 0x38, 0x38, 0x00,
0x0C, 0x00, 0x0C, 0x1C, 0x1C, 0x1C, 0x1C, 0xF8,
0xC0, 0xC0, 0xCC, 0xD8, 0xF0, 0xD8, 0xCC, 0x00,
0x18, 0x18, 0x38, 0x38, 0x38, 0x38, 0x38, 0x00,
0x00, 0x00, 0xFC, 0xD6, 0xD6, 0xD6, 0xD6, 0x00,
0x00, 0x00, 0xFC, 0xE6, 0xE6, 0xE6, 0xE6, 0x00,
0x00, 0x00, 0x7C, 0xE6, 0xE6, 0xE6, 0x7C, 0x00,
0x00, 0x00, 0xFC, 0xE6, 0xE6, 0xFC, 0xE0, 0xE0,
0x00, 0x00, 0x7E, 0xCE, 0xCE, 0x7E, 0x0E, 0x0E,
0x00, 0x00, 0xFC, 0xE6, 0xE0, 0xE0, 0xE0, 0x00,
0x00, 0x00, 0x7E, 0xE0, 0x7C, 0x0E, 0xFC, 0x00,
0x18, 0x18, 0x7E, 0x38, 0x38, 0x38, 0x38, 0x00,
0x00, 0x00, 0xE6, 0xE6, 0xE6, 0xE6, 0x7E, 0x00,
0x00, 0x00, 0xE6, 0xE6, 0xE6, 0x6C, 0x38, 0x00,
0x00, 0x00, 0xD6, 0xD6, 0xD6, 0xD6, 0xFC, 0x00,
0x00, 0x00, 0xE6, 0x7C, 0x38, 0x7C, 0xCE, 0x00,
0x00, 0x00, 0xCE, 0xCE, 0xCE, 0x7E, 0x0E, 0xFC,
0x00, 0x00, 0xFE, 0x1C, 0x38, 0x70, 0xFE, 0x00,
0x0C, 0x18, 0x18, 0x30, 0x18, 0x18, 0x0C, 0x00,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x60, 0x30, 0x30, 0x18, 0x30, 0x30, 0x60, 0x00,
0x70, 0xDB, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x10, 0x28, 0x44, 0xFE, 0x00, 0x00,
};

816
src/font.lst
View File

@@ -1,816 +0,0 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ANSI-C Compiler
3 ; Version 3.8.0 #10562 (Linux)
4 ;--------------------------------------------------------
5 .module font
6 .optsdcc -mz80
7
8 ;--------------------------------------------------------
9 ; Public variables in this module
10 ;--------------------------------------------------------
11 .globl _font
12 ;--------------------------------------------------------
13 ; special function registers
14 ;--------------------------------------------------------
15 ;--------------------------------------------------------
16 ; ram data
17 ;--------------------------------------------------------
18 .area _DATA
19 ;--------------------------------------------------------
20 ; ram data
21 ;--------------------------------------------------------
22 .area _INITIALIZED
0000 23 _font::
0000 24 .ds 768
25 ;--------------------------------------------------------
26 ; absolute external ram data
27 ;--------------------------------------------------------
28 .area _DABS (ABS)
29 ;--------------------------------------------------------
30 ; global & static initialisations
31 ;--------------------------------------------------------
32 .area _HOME
33 .area _GSINIT
34 .area _GSFINAL
35 .area _GSINIT
36 ;--------------------------------------------------------
37 ; Home
38 ;--------------------------------------------------------
39 .area _HOME
40 .area _HOME
41 ;--------------------------------------------------------
42 ; code
43 ;--------------------------------------------------------
44 .area _CODE
45 .area _CODE
46 .area _INITIALIZER
0000 47 __xinit__font:
0000 00 48 .db #0x00 ; 0
0001 00 49 .db #0x00 ; 0
0002 00 50 .db #0x00 ; 0
0003 00 51 .db #0x00 ; 0
0004 00 52 .db #0x00 ; 0
0005 00 53 .db #0x00 ; 0
0006 00 54 .db #0x00 ; 0
0007 00 55 .db #0x00 ; 0
0008 30 56 .db #0x30 ; 48 '0'
0009 78 57 .db #0x78 ; 120 'x'
000A 78 58 .db #0x78 ; 120 'x'
000B 78 59 .db #0x78 ; 120 'x'
000C 30 60 .db #0x30 ; 48 '0'
000D 00 61 .db #0x00 ; 0
000E 30 62 .db #0x30 ; 48 '0'
000F 00 63 .db #0x00 ; 0
0010 CC 64 .db #0xcc ; 204
0011 66 65 .db #0x66 ; 102 'f'
0012 33 66 .db #0x33 ; 51 '3'
0013 00 67 .db #0x00 ; 0
0014 00 68 .db #0x00 ; 0
0015 00 69 .db #0x00 ; 0
0016 00 70 .db #0x00 ; 0
0017 00 71 .db #0x00 ; 0
0018 00 72 .db #0x00 ; 0
0019 36 73 .db #0x36 ; 54 '6'
001A 7F 74 .db #0x7f ; 127
001B 36 75 .db #0x36 ; 54 '6'
001C 36 76 .db #0x36 ; 54 '6'
001D 7F 77 .db #0x7f ; 127
001E 36 78 .db #0x36 ; 54 '6'
001F 00 79 .db #0x00 ; 0
0020 7C 80 .db #0x7c ; 124
0021 D6 81 .db #0xd6 ; 214
0022 D0 82 .db #0xd0 ; 208
0023 7C 83 .db #0x7c ; 124
0024 16 84 .db #0x16 ; 22
0025 D6 85 .db #0xd6 ; 214
0026 7C 86 .db #0x7c ; 124
0027 10 87 .db #0x10 ; 16
0028 E3 88 .db #0xe3 ; 227
0029 A6 89 .db #0xa6 ; 166
002A EC 90 .db #0xec ; 236
002B 18 91 .db #0x18 ; 24
002C 37 92 .db #0x37 ; 55 '7'
002D 65 93 .db #0x65 ; 101 'e'
002E C7 94 .db #0xc7 ; 199
002F 00 95 .db #0x00 ; 0
0030 38 96 .db #0x38 ; 56 '8'
0031 4C 97 .db #0x4c ; 76 'L'
0032 38 98 .db #0x38 ; 56 '8'
0033 45 99 .db #0x45 ; 69 'E'
0034 C6 100 .db #0xc6 ; 198
0035 CE 101 .db #0xce ; 206
0036 7A 102 .db #0x7a ; 122 'z'
0037 01 103 .db #0x01 ; 1
0038 06 104 .db #0x06 ; 6
0039 0C 105 .db #0x0c ; 12
003A 18 106 .db #0x18 ; 24
003B 00 107 .db #0x00 ; 0
003C 00 108 .db #0x00 ; 0
003D 00 109 .db #0x00 ; 0
003E 00 110 .db #0x00 ; 0
003F 00 111 .db #0x00 ; 0
0040 0C 112 .db #0x0c ; 12
0041 18 113 .db #0x18 ; 24
0042 18 114 .db #0x18 ; 24
0043 18 115 .db #0x18 ; 24
0044 18 116 .db #0x18 ; 24
0045 18 117 .db #0x18 ; 24
0046 18 118 .db #0x18 ; 24
0047 0C 119 .db #0x0c ; 12
0048 60 120 .db #0x60 ; 96
0049 30 121 .db #0x30 ; 48 '0'
004A 30 122 .db #0x30 ; 48 '0'
004B 30 123 .db #0x30 ; 48 '0'
004C 30 124 .db #0x30 ; 48 '0'
004D 30 125 .db #0x30 ; 48 '0'
004E 30 126 .db #0x30 ; 48 '0'
004F 60 127 .db #0x60 ; 96
0050 10 128 .db #0x10 ; 16
0051 54 129 .db #0x54 ; 84 'T'
0052 38 130 .db #0x38 ; 56 '8'
0053 FE 131 .db #0xfe ; 254
0054 38 132 .db #0x38 ; 56 '8'
0055 54 133 .db #0x54 ; 84 'T'
0056 10 134 .db #0x10 ; 16
0057 00 135 .db #0x00 ; 0
0058 00 136 .db #0x00 ; 0
0059 18 137 .db #0x18 ; 24
005A 18 138 .db #0x18 ; 24
005B 7E 139 .db #0x7e ; 126
005C 18 140 .db #0x18 ; 24
005D 18 141 .db #0x18 ; 24
005E 00 142 .db #0x00 ; 0
005F 00 143 .db #0x00 ; 0
0060 00 144 .db #0x00 ; 0
0061 00 145 .db #0x00 ; 0
0062 00 146 .db #0x00 ; 0
0063 00 147 .db #0x00 ; 0
0064 00 148 .db #0x00 ; 0
0065 00 149 .db #0x00 ; 0
0066 18 150 .db #0x18 ; 24
0067 30 151 .db #0x30 ; 48 '0'
0068 00 152 .db #0x00 ; 0
0069 00 153 .db #0x00 ; 0
006A 00 154 .db #0x00 ; 0
006B 7E 155 .db #0x7e ; 126
006C 00 156 .db #0x00 ; 0
006D 00 157 .db #0x00 ; 0
006E 00 158 .db #0x00 ; 0
006F 00 159 .db #0x00 ; 0
0070 00 160 .db #0x00 ; 0
0071 00 161 .db #0x00 ; 0
0072 00 162 .db #0x00 ; 0
0073 00 163 .db #0x00 ; 0
0074 00 164 .db #0x00 ; 0
0075 00 165 .db #0x00 ; 0
0076 30 166 .db #0x30 ; 48 '0'
0077 00 167 .db #0x00 ; 0
0078 00 168 .db #0x00 ; 0
0079 03 169 .db #0x03 ; 3
007A 06 170 .db #0x06 ; 6
007B 0C 171 .db #0x0c ; 12
007C 18 172 .db #0x18 ; 24
007D 30 173 .db #0x30 ; 48 '0'
007E 60 174 .db #0x60 ; 96
007F 00 175 .db #0x00 ; 0
0080 7C 176 .db #0x7c ; 124
0081 CE 177 .db #0xce ; 206
0082 DE 178 .db #0xde ; 222
0083 FE 179 .db #0xfe ; 254
0084 EE 180 .db #0xee ; 238
0085 CE 181 .db #0xce ; 206
0086 7C 182 .db #0x7c ; 124
0087 00 183 .db #0x00 ; 0
0088 1C 184 .db #0x1c ; 28
0089 3C 185 .db #0x3c ; 60
008A 1C 186 .db #0x1c ; 28
008B 1C 187 .db #0x1c ; 28
008C 1C 188 .db #0x1c ; 28
008D 1C 189 .db #0x1c ; 28
008E 1C 190 .db #0x1c ; 28
008F 00 191 .db #0x00 ; 0
0090 7C 192 .db #0x7c ; 124
0091 CE 193 .db #0xce ; 206
0092 0E 194 .db #0x0e ; 14
0093 1C 195 .db #0x1c ; 28
0094 38 196 .db #0x38 ; 56 '8'
0095 70 197 .db #0x70 ; 112 'p'
0096 FE 198 .db #0xfe ; 254
0097 00 199 .db #0x00 ; 0
0098 7C 200 .db #0x7c ; 124
0099 CE 201 .db #0xce ; 206
009A 0E 202 .db #0x0e ; 14
009B 3C 203 .db #0x3c ; 60
009C 0E 204 .db #0x0e ; 14
009D CE 205 .db #0xce ; 206
009E 7C 206 .db #0x7c ; 124
009F 00 207 .db #0x00 ; 0
00A0 CE 208 .db #0xce ; 206
00A1 CE 209 .db #0xce ; 206
00A2 CE 210 .db #0xce ; 206
00A3 CE 211 .db #0xce ; 206
00A4 FE 212 .db #0xfe ; 254
00A5 0E 213 .db #0x0e ; 14
00A6 0E 214 .db #0x0e ; 14
00A7 00 215 .db #0x00 ; 0
00A8 FE 216 .db #0xfe ; 254
00A9 E0 217 .db #0xe0 ; 224
00AA E0 218 .db #0xe0 ; 224
00AB FC 219 .db #0xfc ; 252
00AC 0E 220 .db #0x0e ; 14
00AD 0E 221 .db #0x0e ; 14
00AE FC 222 .db #0xfc ; 252
00AF 00 223 .db #0x00 ; 0
00B0 7C 224 .db #0x7c ; 124
00B1 E6 225 .db #0xe6 ; 230
00B2 E0 226 .db #0xe0 ; 224
00B3 FC 227 .db #0xfc ; 252
00B4 E6 228 .db #0xe6 ; 230
00B5 E6 229 .db #0xe6 ; 230
00B6 7C 230 .db #0x7c ; 124
00B7 00 231 .db #0x00 ; 0
00B8 FE 232 .db #0xfe ; 254
00B9 06 233 .db #0x06 ; 6
00BA 0E 234 .db #0x0e ; 14
00BB 1C 235 .db #0x1c ; 28
00BC 38 236 .db #0x38 ; 56 '8'
00BD 38 237 .db #0x38 ; 56 '8'
00BE 38 238 .db #0x38 ; 56 '8'
00BF 00 239 .db #0x00 ; 0
00C0 7C 240 .db #0x7c ; 124
00C1 E6 241 .db #0xe6 ; 230
00C2 E6 242 .db #0xe6 ; 230
00C3 7C 243 .db #0x7c ; 124
00C4 E6 244 .db #0xe6 ; 230
00C5 E6 245 .db #0xe6 ; 230
00C6 7C 246 .db #0x7c ; 124
00C7 00 247 .db #0x00 ; 0
00C8 7C 248 .db #0x7c ; 124
00C9 CE 249 .db #0xce ; 206
00CA CE 250 .db #0xce ; 206
00CB 7E 251 .db #0x7e ; 126
00CC 0E 252 .db #0x0e ; 14
00CD 0E 253 .db #0x0e ; 14
00CE FC 254 .db #0xfc ; 252
00CF 00 255 .db #0x00 ; 0
00D0 00 256 .db #0x00 ; 0
00D1 30 257 .db #0x30 ; 48 '0'
00D2 00 258 .db #0x00 ; 0
00D3 00 259 .db #0x00 ; 0
00D4 00 260 .db #0x00 ; 0
00D5 30 261 .db #0x30 ; 48 '0'
00D6 00 262 .db #0x00 ; 0
00D7 00 263 .db #0x00 ; 0
00D8 00 264 .db #0x00 ; 0
00D9 30 265 .db #0x30 ; 48 '0'
00DA 00 266 .db #0x00 ; 0
00DB 00 267 .db #0x00 ; 0
00DC 00 268 .db #0x00 ; 0
00DD 30 269 .db #0x30 ; 48 '0'
00DE 60 270 .db #0x60 ; 96
00DF 00 271 .db #0x00 ; 0
00E0 00 272 .db #0x00 ; 0
00E1 18 273 .db #0x18 ; 24
00E2 30 274 .db #0x30 ; 48 '0'
00E3 60 275 .db #0x60 ; 96
00E4 30 276 .db #0x30 ; 48 '0'
00E5 18 277 .db #0x18 ; 24
00E6 00 278 .db #0x00 ; 0
00E7 00 279 .db #0x00 ; 0
00E8 00 280 .db #0x00 ; 0
00E9 00 281 .db #0x00 ; 0
00EA 7E 282 .db #0x7e ; 126
00EB 00 283 .db #0x00 ; 0
00EC 7E 284 .db #0x7e ; 126
00ED 00 285 .db #0x00 ; 0
00EE 00 286 .db #0x00 ; 0
00EF 00 287 .db #0x00 ; 0
00F0 00 288 .db #0x00 ; 0
00F1 30 289 .db #0x30 ; 48 '0'
00F2 18 290 .db #0x18 ; 24
00F3 0C 291 .db #0x0c ; 12
00F4 18 292 .db #0x18 ; 24
00F5 30 293 .db #0x30 ; 48 '0'
00F6 00 294 .db #0x00 ; 0
00F7 00 295 .db #0x00 ; 0
00F8 7C 296 .db #0x7c ; 124
00F9 C6 297 .db #0xc6 ; 198
00FA 0E 298 .db #0x0e ; 14
00FB 1C 299 .db #0x1c ; 28
00FC 38 300 .db #0x38 ; 56 '8'
00FD 00 301 .db #0x00 ; 0
00FE 38 302 .db #0x38 ; 56 '8'
00FF 00 303 .db #0x00 ; 0
0100 7C 304 .db #0x7c ; 124
0101 C6 305 .db #0xc6 ; 198
0102 DE 306 .db #0xde ; 222
0103 DE 307 .db #0xde ; 222
0104 DC 308 .db #0xdc ; 220
0105 C0 309 .db #0xc0 ; 192
0106 7C 310 .db #0x7c ; 124
0107 00 311 .db #0x00 ; 0
0108 7C 312 .db #0x7c ; 124
0109 E6 313 .db #0xe6 ; 230
010A E6 314 .db #0xe6 ; 230
010B E6 315 .db #0xe6 ; 230
010C FE 316 .db #0xfe ; 254
010D E6 317 .db #0xe6 ; 230
010E E6 318 .db #0xe6 ; 230
010F 00 319 .db #0x00 ; 0
0110 FC 320 .db #0xfc ; 252
0111 E6 321 .db #0xe6 ; 230
0112 E6 322 .db #0xe6 ; 230
0113 FC 323 .db #0xfc ; 252
0114 E6 324 .db #0xe6 ; 230
0115 E6 325 .db #0xe6 ; 230
0116 FC 326 .db #0xfc ; 252
0117 00 327 .db #0x00 ; 0
0118 7C 328 .db #0x7c ; 124
0119 E6 329 .db #0xe6 ; 230
011A E0 330 .db #0xe0 ; 224
011B E0 331 .db #0xe0 ; 224
011C E6 332 .db #0xe6 ; 230
011D E6 333 .db #0xe6 ; 230
011E 7C 334 .db #0x7c ; 124
011F 00 335 .db #0x00 ; 0
0120 FC 336 .db #0xfc ; 252
0121 E6 337 .db #0xe6 ; 230
0122 E6 338 .db #0xe6 ; 230
0123 E6 339 .db #0xe6 ; 230
0124 E6 340 .db #0xe6 ; 230
0125 E6 341 .db #0xe6 ; 230
0126 FC 342 .db #0xfc ; 252
0127 00 343 .db #0x00 ; 0
0128 FE 344 .db #0xfe ; 254
0129 E0 345 .db #0xe0 ; 224
012A E0 346 .db #0xe0 ; 224
012B FE 347 .db #0xfe ; 254
012C E0 348 .db #0xe0 ; 224
012D E0 349 .db #0xe0 ; 224
012E FE 350 .db #0xfe ; 254
012F 00 351 .db #0x00 ; 0
0130 FE 352 .db #0xfe ; 254
0131 E0 353 .db #0xe0 ; 224
0132 E0 354 .db #0xe0 ; 224
0133 FE 355 .db #0xfe ; 254
0134 E0 356 .db #0xe0 ; 224
0135 E0 357 .db #0xe0 ; 224
0136 E0 358 .db #0xe0 ; 224
0137 00 359 .db #0x00 ; 0
0138 7C 360 .db #0x7c ; 124
0139 E6 361 .db #0xe6 ; 230
013A E0 362 .db #0xe0 ; 224
013B EE 363 .db #0xee ; 238
013C E6 364 .db #0xe6 ; 230
013D E6 365 .db #0xe6 ; 230
013E 7C 366 .db #0x7c ; 124
013F 00 367 .db #0x00 ; 0
0140 E6 368 .db #0xe6 ; 230
0141 E6 369 .db #0xe6 ; 230
0142 E6 370 .db #0xe6 ; 230
0143 FE 371 .db #0xfe ; 254
0144 E6 372 .db #0xe6 ; 230
0145 E6 373 .db #0xe6 ; 230
0146 E6 374 .db #0xe6 ; 230
0147 00 375 .db #0x00 ; 0
0148 38 376 .db #0x38 ; 56 '8'
0149 38 377 .db #0x38 ; 56 '8'
014A 38 378 .db #0x38 ; 56 '8'
014B 38 379 .db #0x38 ; 56 '8'
014C 38 380 .db #0x38 ; 56 '8'
014D 38 381 .db #0x38 ; 56 '8'
014E 38 382 .db #0x38 ; 56 '8'
014F 00 383 .db #0x00 ; 0
0150 0E 384 .db #0x0e ; 14
0151 0E 385 .db #0x0e ; 14
0152 0E 386 .db #0x0e ; 14
0153 0E 387 .db #0x0e ; 14
0154 CE 388 .db #0xce ; 206
0155 CE 389 .db #0xce ; 206
0156 7C 390 .db #0x7c ; 124
0157 00 391 .db #0x00 ; 0
0158 E6 392 .db #0xe6 ; 230
0159 EC 393 .db #0xec ; 236
015A F8 394 .db #0xf8 ; 248
015B F0 395 .db #0xf0 ; 240
015C F8 396 .db #0xf8 ; 248
015D EC 397 .db #0xec ; 236
015E E6 398 .db #0xe6 ; 230
015F 00 399 .db #0x00 ; 0
0160 E0 400 .db #0xe0 ; 224
0161 E0 401 .db #0xe0 ; 224
0162 E0 402 .db #0xe0 ; 224
0163 E0 403 .db #0xe0 ; 224
0164 E0 404 .db #0xe0 ; 224
0165 E0 405 .db #0xe0 ; 224
0166 FE 406 .db #0xfe ; 254
0167 00 407 .db #0x00 ; 0
0168 C6 408 .db #0xc6 ; 198
0169 EE 409 .db #0xee ; 238
016A FE 410 .db #0xfe ; 254
016B D6 411 .db #0xd6 ; 214
016C C6 412 .db #0xc6 ; 198
016D C6 413 .db #0xc6 ; 198
016E C6 414 .db #0xc6 ; 198
016F 00 415 .db #0x00 ; 0
0170 C6 416 .db #0xc6 ; 198
0171 E6 417 .db #0xe6 ; 230
0172 F6 418 .db #0xf6 ; 246
0173 FE 419 .db #0xfe ; 254
0174 EE 420 .db #0xee ; 238
0175 E6 421 .db #0xe6 ; 230
0176 E6 422 .db #0xe6 ; 230
0177 00 423 .db #0x00 ; 0
0178 7C 424 .db #0x7c ; 124
0179 E6 425 .db #0xe6 ; 230
017A E6 426 .db #0xe6 ; 230
017B E6 427 .db #0xe6 ; 230
017C E6 428 .db #0xe6 ; 230
017D E6 429 .db #0xe6 ; 230
017E 7C 430 .db #0x7c ; 124
017F 00 431 .db #0x00 ; 0
0180 FC 432 .db #0xfc ; 252
0181 E6 433 .db #0xe6 ; 230
0182 E6 434 .db #0xe6 ; 230
0183 FC 435 .db #0xfc ; 252
0184 E0 436 .db #0xe0 ; 224
0185 E0 437 .db #0xe0 ; 224
0186 E0 438 .db #0xe0 ; 224
0187 00 439 .db #0x00 ; 0
0188 7C 440 .db #0x7c ; 124
0189 E6 441 .db #0xe6 ; 230
018A E6 442 .db #0xe6 ; 230
018B E6 443 .db #0xe6 ; 230
018C E6 444 .db #0xe6 ; 230
018D EA 445 .db #0xea ; 234
018E 74 446 .db #0x74 ; 116 't'
018F 02 447 .db #0x02 ; 2
0190 FC 448 .db #0xfc ; 252
0191 E6 449 .db #0xe6 ; 230
0192 E6 450 .db #0xe6 ; 230
0193 FC 451 .db #0xfc ; 252
0194 E6 452 .db #0xe6 ; 230
0195 E6 453 .db #0xe6 ; 230
0196 E6 454 .db #0xe6 ; 230
0197 00 455 .db #0x00 ; 0
0198 7C 456 .db #0x7c ; 124
0199 E6 457 .db #0xe6 ; 230
019A E0 458 .db #0xe0 ; 224
019B 7C 459 .db #0x7c ; 124
019C 0E 460 .db #0x0e ; 14
019D CE 461 .db #0xce ; 206
019E 7C 462 .db #0x7c ; 124
019F 00 463 .db #0x00 ; 0
01A0 FE 464 .db #0xfe ; 254
01A1 38 465 .db #0x38 ; 56 '8'
01A2 38 466 .db #0x38 ; 56 '8'
01A3 38 467 .db #0x38 ; 56 '8'
01A4 38 468 .db #0x38 ; 56 '8'
01A5 38 469 .db #0x38 ; 56 '8'
01A6 38 470 .db #0x38 ; 56 '8'
01A7 00 471 .db #0x00 ; 0
01A8 E6 472 .db #0xe6 ; 230
01A9 E6 473 .db #0xe6 ; 230
01AA E6 474 .db #0xe6 ; 230
01AB E6 475 .db #0xe6 ; 230
01AC E6 476 .db #0xe6 ; 230
01AD E6 477 .db #0xe6 ; 230
01AE 7C 478 .db #0x7c ; 124
01AF 00 479 .db #0x00 ; 0
01B0 E6 480 .db #0xe6 ; 230
01B1 E6 481 .db #0xe6 ; 230
01B2 E6 482 .db #0xe6 ; 230
01B3 E6 483 .db #0xe6 ; 230
01B4 E6 484 .db #0xe6 ; 230
01B5 7C 485 .db #0x7c ; 124
01B6 38 486 .db #0x38 ; 56 '8'
01B7 00 487 .db #0x00 ; 0
01B8 C6 488 .db #0xc6 ; 198
01B9 C6 489 .db #0xc6 ; 198
01BA C6 490 .db #0xc6 ; 198
01BB D6 491 .db #0xd6 ; 214
01BC D6 492 .db #0xd6 ; 214
01BD FE 493 .db #0xfe ; 254
01BE FC 494 .db #0xfc ; 252
01BF 00 495 .db #0x00 ; 0
01C0 E3 496 .db #0xe3 ; 227
01C1 76 497 .db #0x76 ; 118 'v'
01C2 3C 498 .db #0x3c ; 60
01C3 18 499 .db #0x18 ; 24
01C4 3C 500 .db #0x3c ; 60
01C5 6E 501 .db #0x6e ; 110 'n'
01C6 C7 502 .db #0xc7 ; 199
01C7 00 503 .db #0x00 ; 0
01C8 E6 504 .db #0xe6 ; 230
01C9 E6 505 .db #0xe6 ; 230
01CA 7C 506 .db #0x7c ; 124
01CB 38 507 .db #0x38 ; 56 '8'
01CC 38 508 .db #0x38 ; 56 '8'
01CD 38 509 .db #0x38 ; 56 '8'
01CE 38 510 .db #0x38 ; 56 '8'
01CF 00 511 .db #0x00 ; 0
01D0 FE 512 .db #0xfe ; 254
01D1 0E 513 .db #0x0e ; 14
01D2 1C 514 .db #0x1c ; 28
01D3 38 515 .db #0x38 ; 56 '8'
01D4 70 516 .db #0x70 ; 112 'p'
01D5 E0 517 .db #0xe0 ; 224
01D6 FE 518 .db #0xfe ; 254
01D7 00 519 .db #0x00 ; 0
01D8 1C 520 .db #0x1c ; 28
01D9 18 521 .db #0x18 ; 24
01DA 18 522 .db #0x18 ; 24
01DB 18 523 .db #0x18 ; 24
01DC 18 524 .db #0x18 ; 24
01DD 18 525 .db #0x18 ; 24
01DE 18 526 .db #0x18 ; 24
01DF 1C 527 .db #0x1c ; 28
01E0 00 528 .db #0x00 ; 0
01E1 60 529 .db #0x60 ; 96
01E2 30 530 .db #0x30 ; 48 '0'
01E3 18 531 .db #0x18 ; 24
01E4 0C 532 .db #0x0c ; 12
01E5 06 533 .db #0x06 ; 6
01E6 03 534 .db #0x03 ; 3
01E7 00 535 .db #0x00 ; 0
01E8 70 536 .db #0x70 ; 112 'p'
01E9 30 537 .db #0x30 ; 48 '0'
01EA 30 538 .db #0x30 ; 48 '0'
01EB 30 539 .db #0x30 ; 48 '0'
01EC 30 540 .db #0x30 ; 48 '0'
01ED 30 541 .db #0x30 ; 48 '0'
01EE 30 542 .db #0x30 ; 48 '0'
01EF 70 543 .db #0x70 ; 112 'p'
01F0 18 544 .db #0x18 ; 24
01F1 3C 545 .db #0x3c ; 60
01F2 66 546 .db #0x66 ; 102 'f'
01F3 C3 547 .db #0xc3 ; 195
01F4 00 548 .db #0x00 ; 0
01F5 00 549 .db #0x00 ; 0
01F6 00 550 .db #0x00 ; 0
01F7 00 551 .db #0x00 ; 0
01F8 00 552 .db #0x00 ; 0
01F9 00 553 .db #0x00 ; 0
01FA 00 554 .db #0x00 ; 0
01FB 00 555 .db #0x00 ; 0
01FC 00 556 .db #0x00 ; 0
01FD 00 557 .db #0x00 ; 0
01FE 00 558 .db #0x00 ; 0
01FF FF 559 .db #0xff ; 255
0200 30 560 .db #0x30 ; 48 '0'
0201 18 561 .db #0x18 ; 24
0202 0C 562 .db #0x0c ; 12
0203 00 563 .db #0x00 ; 0
0204 00 564 .db #0x00 ; 0
0205 00 565 .db #0x00 ; 0
0206 00 566 .db #0x00 ; 0
0207 00 567 .db #0x00 ; 0
0208 00 568 .db #0x00 ; 0
0209 00 569 .db #0x00 ; 0
020A 7C 570 .db #0x7c ; 124
020B 0E 571 .db #0x0e ; 14
020C 7E 572 .db #0x7e ; 126
020D CE 573 .db #0xce ; 206
020E 7E 574 .db #0x7e ; 126
020F 00 575 .db #0x00 ; 0
0210 C0 576 .db #0xc0 ; 192
0211 C0 577 .db #0xc0 ; 192
0212 FC 578 .db #0xfc ; 252
0213 E6 579 .db #0xe6 ; 230
0214 E6 580 .db #0xe6 ; 230
0215 E6 581 .db #0xe6 ; 230
0216 FC 582 .db #0xfc ; 252
0217 00 583 .db #0x00 ; 0
0218 00 584 .db #0x00 ; 0
0219 00 585 .db #0x00 ; 0
021A 7C 586 .db #0x7c ; 124
021B E6 587 .db #0xe6 ; 230
021C E0 588 .db #0xe0 ; 224
021D E6 589 .db #0xe6 ; 230
021E 7C 590 .db #0x7c ; 124
021F 00 591 .db #0x00 ; 0
0220 06 592 .db #0x06 ; 6
0221 06 593 .db #0x06 ; 6
0222 7E 594 .db #0x7e ; 126
0223 CE 595 .db #0xce ; 206
0224 CE 596 .db #0xce ; 206
0225 CE 597 .db #0xce ; 206
0226 7E 598 .db #0x7e ; 126
0227 00 599 .db #0x00 ; 0
0228 00 600 .db #0x00 ; 0
0229 00 601 .db #0x00 ; 0
022A 7C 602 .db #0x7c ; 124
022B E6 603 .db #0xe6 ; 230
022C FE 604 .db #0xfe ; 254
022D E0 605 .db #0xe0 ; 224
022E 7E 606 .db #0x7e ; 126
022F 00 607 .db #0x00 ; 0
0230 3C 608 .db #0x3c ; 60
0231 70 609 .db #0x70 ; 112 'p'
0232 70 610 .db #0x70 ; 112 'p'
0233 FC 611 .db #0xfc ; 252
0234 70 612 .db #0x70 ; 112 'p'
0235 70 613 .db #0x70 ; 112 'p'
0236 70 614 .db #0x70 ; 112 'p'
0237 00 615 .db #0x00 ; 0
0238 00 616 .db #0x00 ; 0
0239 00 617 .db #0x00 ; 0
023A 7C 618 .db #0x7c ; 124
023B CE 619 .db #0xce ; 206
023C CE 620 .db #0xce ; 206
023D 7E 621 .db #0x7e ; 126
023E 0E 622 .db #0x0e ; 14
023F 7C 623 .db #0x7c ; 124
0240 C0 624 .db #0xc0 ; 192
0241 C0 625 .db #0xc0 ; 192
0242 FC 626 .db #0xfc ; 252
0243 E6 627 .db #0xe6 ; 230
0244 E6 628 .db #0xe6 ; 230
0245 E6 629 .db #0xe6 ; 230
0246 E6 630 .db #0xe6 ; 230
0247 00 631 .db #0x00 ; 0
0248 18 632 .db #0x18 ; 24
0249 00 633 .db #0x00 ; 0
024A 18 634 .db #0x18 ; 24
024B 38 635 .db #0x38 ; 56 '8'
024C 38 636 .db #0x38 ; 56 '8'
024D 38 637 .db #0x38 ; 56 '8'
024E 38 638 .db #0x38 ; 56 '8'
024F 00 639 .db #0x00 ; 0
0250 0C 640 .db #0x0c ; 12
0251 00 641 .db #0x00 ; 0
0252 0C 642 .db #0x0c ; 12
0253 1C 643 .db #0x1c ; 28
0254 1C 644 .db #0x1c ; 28
0255 1C 645 .db #0x1c ; 28
0256 1C 646 .db #0x1c ; 28
0257 F8 647 .db #0xf8 ; 248
0258 C0 648 .db #0xc0 ; 192
0259 C0 649 .db #0xc0 ; 192
025A CC 650 .db #0xcc ; 204
025B D8 651 .db #0xd8 ; 216
025C F0 652 .db #0xf0 ; 240
025D D8 653 .db #0xd8 ; 216
025E CC 654 .db #0xcc ; 204
025F 00 655 .db #0x00 ; 0
0260 18 656 .db #0x18 ; 24
0261 18 657 .db #0x18 ; 24
0262 38 658 .db #0x38 ; 56 '8'
0263 38 659 .db #0x38 ; 56 '8'
0264 38 660 .db #0x38 ; 56 '8'
0265 38 661 .db #0x38 ; 56 '8'
0266 38 662 .db #0x38 ; 56 '8'
0267 00 663 .db #0x00 ; 0
0268 00 664 .db #0x00 ; 0
0269 00 665 .db #0x00 ; 0
026A FC 666 .db #0xfc ; 252
026B D6 667 .db #0xd6 ; 214
026C D6 668 .db #0xd6 ; 214
026D D6 669 .db #0xd6 ; 214
026E D6 670 .db #0xd6 ; 214
026F 00 671 .db #0x00 ; 0
0270 00 672 .db #0x00 ; 0
0271 00 673 .db #0x00 ; 0
0272 FC 674 .db #0xfc ; 252
0273 E6 675 .db #0xe6 ; 230
0274 E6 676 .db #0xe6 ; 230
0275 E6 677 .db #0xe6 ; 230
0276 E6 678 .db #0xe6 ; 230
0277 00 679 .db #0x00 ; 0
0278 00 680 .db #0x00 ; 0
0279 00 681 .db #0x00 ; 0
027A 7C 682 .db #0x7c ; 124
027B E6 683 .db #0xe6 ; 230
027C E6 684 .db #0xe6 ; 230
027D E6 685 .db #0xe6 ; 230
027E 7C 686 .db #0x7c ; 124
027F 00 687 .db #0x00 ; 0
0280 00 688 .db #0x00 ; 0
0281 00 689 .db #0x00 ; 0
0282 FC 690 .db #0xfc ; 252
0283 E6 691 .db #0xe6 ; 230
0284 E6 692 .db #0xe6 ; 230
0285 FC 693 .db #0xfc ; 252
0286 E0 694 .db #0xe0 ; 224
0287 E0 695 .db #0xe0 ; 224
0288 00 696 .db #0x00 ; 0
0289 00 697 .db #0x00 ; 0
028A 7E 698 .db #0x7e ; 126
028B CE 699 .db #0xce ; 206
028C CE 700 .db #0xce ; 206
028D 7E 701 .db #0x7e ; 126
028E 0E 702 .db #0x0e ; 14
028F 0E 703 .db #0x0e ; 14
0290 00 704 .db #0x00 ; 0
0291 00 705 .db #0x00 ; 0
0292 FC 706 .db #0xfc ; 252
0293 E6 707 .db #0xe6 ; 230
0294 E0 708 .db #0xe0 ; 224
0295 E0 709 .db #0xe0 ; 224
0296 E0 710 .db #0xe0 ; 224
0297 00 711 .db #0x00 ; 0
0298 00 712 .db #0x00 ; 0
0299 00 713 .db #0x00 ; 0
029A 7E 714 .db #0x7e ; 126
029B E0 715 .db #0xe0 ; 224
029C 7C 716 .db #0x7c ; 124
029D 0E 717 .db #0x0e ; 14
029E FC 718 .db #0xfc ; 252
029F 00 719 .db #0x00 ; 0
02A0 18 720 .db #0x18 ; 24
02A1 18 721 .db #0x18 ; 24
02A2 7E 722 .db #0x7e ; 126
02A3 38 723 .db #0x38 ; 56 '8'
02A4 38 724 .db #0x38 ; 56 '8'
02A5 38 725 .db #0x38 ; 56 '8'
02A6 38 726 .db #0x38 ; 56 '8'
02A7 00 727 .db #0x00 ; 0
02A8 00 728 .db #0x00 ; 0
02A9 00 729 .db #0x00 ; 0
02AA E6 730 .db #0xe6 ; 230
02AB E6 731 .db #0xe6 ; 230
02AC E6 732 .db #0xe6 ; 230
02AD E6 733 .db #0xe6 ; 230
02AE 7E 734 .db #0x7e ; 126
02AF 00 735 .db #0x00 ; 0
02B0 00 736 .db #0x00 ; 0
02B1 00 737 .db #0x00 ; 0
02B2 E6 738 .db #0xe6 ; 230
02B3 E6 739 .db #0xe6 ; 230
02B4 E6 740 .db #0xe6 ; 230
02B5 6C 741 .db #0x6c ; 108 'l'
02B6 38 742 .db #0x38 ; 56 '8'
02B7 00 743 .db #0x00 ; 0
02B8 00 744 .db #0x00 ; 0
02B9 00 745 .db #0x00 ; 0
02BA D6 746 .db #0xd6 ; 214
02BB D6 747 .db #0xd6 ; 214
02BC D6 748 .db #0xd6 ; 214
02BD D6 749 .db #0xd6 ; 214
02BE FC 750 .db #0xfc ; 252
02BF 00 751 .db #0x00 ; 0
02C0 00 752 .db #0x00 ; 0
02C1 00 753 .db #0x00 ; 0
02C2 E6 754 .db #0xe6 ; 230
02C3 7C 755 .db #0x7c ; 124
02C4 38 756 .db #0x38 ; 56 '8'
02C5 7C 757 .db #0x7c ; 124
02C6 CE 758 .db #0xce ; 206
02C7 00 759 .db #0x00 ; 0
02C8 00 760 .db #0x00 ; 0
02C9 00 761 .db #0x00 ; 0
02CA CE 762 .db #0xce ; 206
02CB CE 763 .db #0xce ; 206
02CC CE 764 .db #0xce ; 206
02CD 7E 765 .db #0x7e ; 126
02CE 0E 766 .db #0x0e ; 14
02CF FC 767 .db #0xfc ; 252
02D0 00 768 .db #0x00 ; 0
02D1 00 769 .db #0x00 ; 0
02D2 FE 770 .db #0xfe ; 254
02D3 1C 771 .db #0x1c ; 28
02D4 38 772 .db #0x38 ; 56 '8'
02D5 70 773 .db #0x70 ; 112 'p'
02D6 FE 774 .db #0xfe ; 254
02D7 00 775 .db #0x00 ; 0
02D8 0C 776 .db #0x0c ; 12
02D9 18 777 .db #0x18 ; 24
02DA 18 778 .db #0x18 ; 24
02DB 30 779 .db #0x30 ; 48 '0'
02DC 18 780 .db #0x18 ; 24
02DD 18 781 .db #0x18 ; 24
02DE 0C 782 .db #0x0c ; 12
02DF 00 783 .db #0x00 ; 0
02E0 18 784 .db #0x18 ; 24
02E1 18 785 .db #0x18 ; 24
02E2 18 786 .db #0x18 ; 24
02E3 18 787 .db #0x18 ; 24
02E4 18 788 .db #0x18 ; 24
02E5 18 789 .db #0x18 ; 24
02E6 18 790 .db #0x18 ; 24
02E7 18 791 .db #0x18 ; 24
02E8 60 792 .db #0x60 ; 96
02E9 30 793 .db #0x30 ; 48 '0'
02EA 30 794 .db #0x30 ; 48 '0'
02EB 18 795 .db #0x18 ; 24
02EC 30 796 .db #0x30 ; 48 '0'
02ED 30 797 .db #0x30 ; 48 '0'
02EE 60 798 .db #0x60 ; 96
02EF 00 799 .db #0x00 ; 0
02F0 70 800 .db #0x70 ; 112 'p'
02F1 DB 801 .db #0xdb ; 219
02F2 0E 802 .db #0x0e ; 14
02F3 00 803 .db #0x00 ; 0
02F4 00 804 .db #0x00 ; 0
02F5 00 805 .db #0x00 ; 0
02F6 00 806 .db #0x00 ; 0
02F7 00 807 .db #0x00 ; 0
02F8 00 808 .db #0x00 ; 0
02F9 00 809 .db #0x00 ; 0
02FA 10 810 .db #0x10 ; 16
02FB 28 811 .db #0x28 ; 40
02FC 44 812 .db #0x44 ; 68 'D'
02FD FE 813 .db #0xfe ; 254
02FE 00 814 .db #0x00 ; 0
02FF 00 815 .db #0x00 ; 0
816 .area _CABS (ABS)

27
src/font.sym
View File

@@ -1,27 +0,0 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 1.
Hexadecimal [16-Bits]
Symbol Table
.__.$$$. = 2710 L
.__.ABS. = 0000 G
.__.CPU. = 0000 L
.__.H$L. = 0000 L
7 __xinit__font 0000 R
2 _font 0000 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (Zilog Z80 / Hitachi HD64180 / ZX-Next), page 2.
Hexadecimal [16-Bits]
Area Table
0 _CODE size 0 flags 0
1 _DATA size 0 flags 0
2 _INITIALIZED size 300 flags 0
3 _DABS size 0 flags 8
4 _HOME size 0 flags 0
5 _GSINIT size 0 flags 0
6 _GSFINAL size 0 flags 0
7 _INITIALIZER size 300 flags 0
8 _CABS size 0 flags 8

13
sys/ascal.vhd
View File

@@ -382,8 +382,9 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL avl_o_vs_sync,avl_o_vs : std_logic;
SIGNAL avl_fb_ena : std_logic;
FUNCTION buf_next(a,b : natural RANGE 0 TO 2) RETURN natural IS
FUNCTION buf_next(a,b : natural RANGE 0 TO 2; freeze : std_logic := '0') RETURN natural IS
BEGIN
IF (freeze='1') THEN RETURN a; END IF;
IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF;
IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF;
RETURN 1;
@@ -400,6 +401,7 @@ ARCHITECTURE rtl OF ascal IS
----------------------------------------------------------
-- Output
SIGNAL o_run : std_logic;
SIGNAL o_freeze : std_logic;
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
SIGNAL o_format : unsigned(5 DOWNTO 0);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
@@ -1730,22 +1732,23 @@ BEGIN
-- Triple buffering.
-- For intelaced video, half frames are updated independently
-- Input : Toggle buffer at end of input frame
o_freeze <= freeze;
o_inter <=i_inter; -- <ASYNC>
o_iendframe0<=i_endframe0; -- <ASYNC>
o_iendframe02<=o_iendframe0;
IF o_iendframe0='1' AND o_iendframe02='0' THEN
o_ibuf0<=buf_next(o_ibuf0,o_obuf0);
o_ibuf0<=buf_next(o_ibuf0,o_obuf0,o_freeze);
o_bufup0<='1';
END IF;
o_iendframe1<=i_endframe1; -- <ASYNC>
o_iendframe12<=o_iendframe1;
IF o_iendframe1='1' AND o_iendframe12='0' THEN
o_ibuf1<=buf_next(o_ibuf1,o_obuf1);
o_ibuf1<=buf_next(o_ibuf1,o_obuf1,o_freeze);
o_bufup1<='1';
END IF;
-- Output : Change framebuffer, and image properties, at VS falling edge
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN
o_obuf1<=buf_next(o_obuf1,o_ibuf1);
o_obuf1<=buf_next(o_obuf1,o_ibuf1,o_freeze);
o_bufup1<='0';
o_ihsize<=i_hrsize; -- <ASYNC>
o_ivsize<=i_vrsize; -- <ASYNC>
@@ -1773,7 +1776,7 @@ BEGIN
END IF;
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
o_obuf0<=buf_next(o_obuf0,o_ibuf0);
o_obuf0<=buf_next(o_obuf0,o_ibuf0,o_freeze);
o_bufup0<='0';
END IF;

35
sys/hps_io.v → sys/hps_io.sv
View File

@@ -25,14 +25,11 @@
//
// WIDE=1 for 16 bit file I/O
// VDNUM 1-4
module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
(
input clk_sys,
inout [45:0] HPS_BUS,
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// buttons up to 32
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
@@ -156,8 +153,6 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
assign EXT_BUS[31:16] = HPS_BUS[31:16];
assign EXT_BUS[35:33] = HPS_BUS[35:33];
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
localparam DW = (WIDE) ? 15 : 7;
localparam AW = (WIDE) ? 7 : 8;
localparam VD = VDNUM-1;
@@ -221,6 +216,19 @@ video_calc video_calc
/////////////////////////////////////////////////////////
localparam STRLEN = $size(CONF_STR)>>3;
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
wire [7:0] conf_byte;
generate
if(CONF_STR_BRAM) begin
confstr_rom #(CONF_STR, STRLEN) confstr_rom(.*, .conf_addr(byte_cnt - 1'd1));
end
else begin
assign conf_byte = CONF_STR[{(STRLEN - byte_cnt),3'b000} +:8];
end
endgenerate
assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value};
reg gamma_en;
reg gamma_wr;
@@ -347,7 +355,7 @@ always@(posedge clk_sys) begin : uio_block
end
// reading config string, returning a byte from string
'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_str[{(STRLEN - byte_cnt),3'b000} +:8];
'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_byte;
// reading sd card status
'h16: if(!byte_cnt[MAX_W:3]) begin
@@ -925,3 +933,16 @@ always @(posedge clk_100) begin
end
endmodule
module confstr_rom #(parameter CONF_STR, STRLEN)
(
input clk_sys,
input [$clog2(STRLEN+1)-1:0] conf_addr,
output reg [7:0] conf_byte
);
wire [7:0] rom[STRLEN];
initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
endmodule

2
sys/osd.v
View File

@@ -72,7 +72,7 @@ always@(posedge clk_sys) begin
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4) begin
if(!io_din[0]) {osd_status,highres} <= 0;
else {osd_status,info} <= {~io_din[2],io_din[2]};
else {osd_status,info} <= {~io_din[2] & ~io_din[3],io_din[2]};
bcnt <= 0;
end
// command 0x20: OSDCMDWRITE

3
sys/sys.qip
View File

@@ -11,6 +11,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) v
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
@@ -29,4 +30,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]

7
sys/sys_top.v
View File

@@ -292,7 +292,8 @@ reg cfg_custom_t = 0;
reg [5:0] cfg_custom_p1;
reg [31:0] cfg_custom_p2;
reg [4:0] vol_att = 0;
reg [4:0] vol_att;
initial vol_att = 5'b11111;
reg [6:0] coef_addr;
reg [8:0] coef_data;
@@ -618,6 +619,7 @@ wire vbuf_write;
wire [23:0] hdmi_data;
wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
wire freeze;
`ifndef MISTER_DEBUG_NOHDMI
wire clk_hdmi = hdmi_clk_out;
@@ -639,7 +641,7 @@ ascal
(
.reset_na (~reset_req),
.run (1),
.freeze (0),
.freeze (freeze),
.i_clk (clk_ihdmi),
.i_ce (ce_hpix),
@@ -1522,6 +1524,7 @@ emu emu
.HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width),
.HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height),
.HDMI_FREEZE(freeze),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),

143
sys/video_freezer.sv Normal file
View File

@@ -0,0 +1,143 @@
//
// video freeze with sync
// (C) Alexey Melnikov
//
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
module video_freezer
(
input clk,
output sync,
input freeze,
input hs_in,
input vs_in,
input hbl_in,
input vbl_in,
output hs_out,
output vs_out,
output hbl_out,
output vbl_out
);
sync_lock #(33) vs_lock
(
.clk(clk),
.sync_in(vs_in),
.sync_out(vs_out),
.de_in(vbl_in),
.de_out(vbl_out),
.freeze(freeze)
);
wire sync_pt;
sync_lock #(21) hs_lock
(
.clk(clk),
.sync_in(hs_in),
.sync_out(hs_out),
.de_in(hbl_in),
.de_out(hbl_out),
.freeze(freeze),
.sync_pt(sync_pt)
);
reg sync_o;
always @(posedge clk) begin
reg old_hs, old_vs;
reg vs_sync;
old_vs <= vs_out;
if(~old_vs & vs_out) vs_sync <= 1;
if(sync_pt & vs_sync) begin
vs_sync <= 0;
sync_o <= ~sync_o;
end
end
assign sync = sync_o;
endmodule
module sync_lock #(parameter WIDTH)
(
input clk,
input sync_in,
input de_in,
output sync_out,
output de_out,
input freeze,
output sync_pt,
output valid
);
reg [WIDTH-1:0] f_len, s_len, de_start, de_end;
reg sync_valid;
reg old_sync;
always @(posedge clk) old_sync <= sync_in;
always @(posedge clk) begin
reg [WIDTH-1:0] cnti;
reg f_valid;
reg old_de;
cnti <= cnti + 1'd1;
if(~old_sync & sync_in) begin
if(sync_valid) f_len <= cnti;
f_valid <= 1;
sync_valid <= f_valid;
cnti <= 0;
end
if(old_sync & ~sync_in & sync_valid) s_len <= cnti;
old_de <= de_in;
if(~old_de & de_in & sync_valid) de_start <= cnti;
if(old_de & ~de_in & sync_valid) de_end <= cnti;
if(freeze) {f_valid, sync_valid} <= 0;
end
reg sync_o, de_o, sync_o_pre;
always @(posedge clk) begin
reg [WIDTH-1:0] cnto;
cnto <= cnto + 1'd1;
if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2;
if(cnto == f_len) cnto <= 0;
sync_o_pre <= (cnto == (s_len>>1)); // middle in sync
if(cnto == f_len) sync_o <= 1;
if(cnto == s_len) sync_o <= 0;
if(cnto == de_start) de_o <= 1;
if(cnto == de_end) de_o <= 0;
end
assign sync_out = freeze ? sync_o : sync_in;
assign valid = sync_valid;
assign sync_pt = sync_o_pre;
assign de_out = freeze ? de_o : de_in;
endmodule

59
sys/video_mixer.sv
View File

@@ -10,10 +10,7 @@
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// LINE_LENGTH: Length of display line in pixels when HBlank = 0;
// HALF_DEPTH: If =1 then color dept is 4 bits per component
//
// altera message_off 10720
@@ -47,6 +44,12 @@ module video_mixer
input HBlank,
input VBlank,
// Freeze engine
// HDMI: displays last frame
// VGA: black screen with HSync and VSync
input HDMI_FREEZE,
output freeze_sync,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
@@ -60,19 +63,43 @@ localparam DWIDTH = HALF_DEPTH ? 3 : 7;
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
wire frz_hs, frz_vs;
wire frz_hbl, frz_vbl;
video_freezer freezer
(
.clk(CLK_VIDEO),
.freeze(HDMI_FREEZE),
.hs_in(HSync),
.vs_in(VSync),
.hbl_in(HBlank),
.vbl_in(VBlank),
.sync(freeze_sync),
.hs_out(frz_hs),
.vs_out(frz_vs),
.hbl_out(frz_hbl),
.vbl_out(frz_vbl)
);
reg frz;
always @(posedge CLK_VIDEO) begin
reg frz1;
frz1 <= HDMI_FREEZE;
frz <= frz1;
end
generate
if(GAMMA && HALF_DEPTH) begin
wire [7:0] R_in = {R,R};
wire [7:0] G_in = {G,G};
wire [7:0] B_in = {B,B};
wire [7:0] R_in = frz ? 8'd0 : {R,R};
wire [7:0] G_in = frz ? 8'd0 : {G,G};
wire [7:0] B_in = frz ? 8'd0 : {B,B};
end else begin
wire [DWIDTH:0] R_in = R;
wire [DWIDTH:0] G_in = G;
wire [DWIDTH:0] B_in = B;
wire [DWIDTH:0] R_in = frz ? 1'd0 : R;
wire [DWIDTH:0] G_in = frz ? 1'd0 : G;
wire [DWIDTH:0] B_in = frz ? 1'd0 : B;
end
endgenerate
wire hs_g, vs_g;
wire hb_g, vb_g;
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
@@ -90,10 +117,10 @@ generate
.gamma_wr_addr(gamma_bus[17:8]),
.gamma_value(gamma_bus[7:0]),
.HSync(HSync),
.VSync(VSync),
.HBlank(HBlank),
.VBlank(VBlank),
.HSync(frz_hs),
.VSync(frz_vs),
.HBlank(frz_hbl),
.VBlank(frz_vbl),
.RGB_in({R_in,G_in,B_in}),
.HSync_out(hs_g),
@@ -105,7 +132,7 @@ generate
end else begin
assign gamma_bus[21] = 0;
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl};
end
endgenerate

21
verilator/imgui.ini
View File

@@ -4,7 +4,7 @@ Size=400,400
Collapsed=0
[Window][Debug Log]
Pos=19,8
Pos=6,18
Size=520,600
Collapsed=0
@@ -29,8 +29,8 @@ Size=560,393
Collapsed=0
[Window][CPU Registers]
Pos=738,825
Size=269,180
Pos=1308,461
Size=269,188
Collapsed=0
[Window][PGROM Editor]
@@ -43,3 +43,18 @@ Pos=19,866
Size=553,169
Collapsed=0
[Window][WKRAM Editor]
Pos=1037,656
Size=540,370
Collapsed=0
[Window][CHRAM Editor]
Pos=501,656
Size=535,370
Collapsed=0
[Window][COLRAM Editor]
Pos=-208,137
Size=738,454
Collapsed=0

97
verilator/sim.v
View File

@@ -7,55 +7,62 @@
`define USE_VGA
//`define USE_CGA
module top(VGA_R,VGA_B,VGA_G,VGA_HS,VGA_VS,VGA_HB,VGA_VB,reset,clk_sys,clk_vid,inputs,ioctl_download,ioctl_addr,ioctl_dout,ioctl_index,ioctl_wait,ioctl_wr);
module top(
input clk_sys/*verilator public_flat*/;
input clk_vid/*verilator public_flat*/;
input reset/*verilator public_flat*/;
input [11:0] inputs/*verilator public_flat*/;
input clk_sys/*verilator public_flat*/,
input clk_vid/*verilator public_flat*/,
input reset/*verilator public_flat*/,
// 6 joysticks, 32 buttons each
input [31:0] joystick_0,
input [31:0] joystick_1,
input [31:0] joystick_2,
input [31:0] joystick_3,
input [31:0] joystick_4,
input [31:0] joystick_5,
// analog -127..+127, Y: [15:8], X: [7:0]
// input [15:0] joystick_analog_0;
// input [15:0] joystick_analog_1;
// input [15:0] joystick_analog_2;
// input [15:0] joystick_analog_3;
// input [15:0] joystick_analog_4;
// input [15:0] joystick_analog_5;
output [7:0] VGA_R/*verilator public_flat*/;
output [7:0] VGA_G/*verilator public_flat*/;
output [7:0] VGA_B/*verilator public_flat*/;
output VGA_HS;
output VGA_VS;
output VGA_HB;
output VGA_VB;
input ioctl_download;
input ioctl_wr;
input [24:0] ioctl_addr;
input [7:0] ioctl_dout;
input [7:0] ioctl_index;
output reg ioctl_wait=1'b0;
wire btn_start = inputs[6];
wire btn_coin = inputs[8];
wire m_bomb = inputs[5];
wire m_fire = inputs[4];
wire m_right = inputs[0];
wire m_left = inputs[1];
wire m_down = inputs[2];
wire m_up = inputs[3];
output [7:0] VGA_R/*verilator public_flat*/,
output [7:0] VGA_G/*verilator public_flat*/,
output [7:0] VGA_B/*verilator public_flat*/,
output VGA_HS,
output VGA_VS,
output VGA_HB,
output VGA_VB,
input ioctl_download,
input ioctl_wr,
input [24:0] ioctl_addr,
input [7:0] ioctl_dout,
input [7:0] ioctl_index,
output reg ioctl_wait=1'b0
);
soc soc(
.clk_sys(clk_sys),
.clk_pix(clk_sys),
.reset(reset | ioctl_download),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HB(VGA_HB),
.VGA_VB(VGA_VB),
.dn_addr(ioctl_addr[13:0]),
.dn_data(ioctl_dout),
.dn_wr(ioctl_wr),
.dn_index(ioctl_index),
.inputs({btn_coin, btn_start, m_bomb, m_fire, m_right, m_left, m_down, m_up})
.clk_sys(clk_sys),
.ce_pix(clk_sys),
.reset(reset | ioctl_download),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HB(VGA_HB),
.VGA_VB(VGA_VB),
.dn_addr(ioctl_addr[13:0]),
.dn_data(ioctl_dout),
.dn_wr(ioctl_wr),
.dn_index(ioctl_index),
.joystick({joystick_5,joystick_4,joystick_3,joystick_2,joystick_1,joystick_0})
);
endmodule

13
verilator/sim/sim_clock.cpp
View File

@@ -1,9 +1,6 @@
#include "sim_clock.h"
#include <string>
//bool clk, old;
//int ratio, count;
SimClock::SimClock(int r) {
ratio = r;
count = 0;
@@ -11,15 +8,17 @@ SimClock::SimClock(int r) {
old = false;
}
SimClock::~SimClock() {
}
void SimClock::Tick() {
old = clk;
count++;
if (count >= ratio) {
clk = !clk; count = 0;
if (count > ratio) {
count = 0;
}
clk = (count == 0);
}
void SimClock::Reset() {
@@ -27,3 +26,7 @@ void SimClock::Reset() {
clk = false;
old = false;
}
bool SimClock::IsRising() {
return clk && !old;
}

1
verilator/sim/sim_clock.h
View File

@@ -10,6 +10,7 @@ public:
~SimClock();
void Tick();
void Reset();
bool IsRising();
private:
int ratio, count;

66
verilator/sim_main.cpp
View File

@@ -50,8 +50,8 @@ const int input_pause = 11;
// Video
// -----
#define VGA_WIDTH 400
#define VGA_HEIGHT 300
#define VGA_WIDTH 320
#define VGA_HEIGHT 240
#define VGA_ROTATE 0 // 90 degrees anti-clockwise
SimVideo video(VGA_WIDTH, VGA_HEIGHT, VGA_ROTATE);
@@ -59,7 +59,7 @@ SimVideo video(VGA_WIDTH, VGA_HEIGHT, VGA_ROTATE);
// ------------------
int initialReset = 48;
bool run_enable = 1;
int batchSize = 2500000 / 1000;
int batchSize = 150000;
bool single_step = 0;
bool multi_step = 0;
int multi_step_amount = 1024;
@@ -74,8 +74,8 @@ double sc_time_stamp() { // Called by $time in Verilog.
}
int clockSpeed = 24; // This is not used, just a reminder for the dividers below
SimClock clk_sys(2); // 12mhz
SimClock clk_pix(2); // 6mhz
SimClock clk_sys(1); // 12mhz
SimClock clk_pix(1); // 6mhz
void resetSim() {
main_time = 0;
@@ -95,14 +95,14 @@ int verilate() {
// Clock dividers
clk_sys.Tick();
clk_pix.Tick();
clk_pix.Tick();
// Set system clock in core
top->clk_sys = clk_sys.clk;
top->clk_vid = clk_pix.clk;
// Output pixels on rising edge of pixel clock
if (clk_pix.clk && !clk_pix.old) {
if (clk_pix.IsRising()) {
uint32_t colour = 0xFF000000 | top->VGA_B << 16 | top->VGA_G << 8 | top->VGA_R;
video.Clock(top->VGA_HB, top->VGA_VB, top->VGA_HS, top->VGA_VS, colour);
}
@@ -177,7 +177,7 @@ int main(int argc, char** argv, char** env) {
if (video.Initialise(windowTitle) == 1) { return 1; }
bus.QueueDownload("../src/boot_rom.bin", 0);
bus.QueueDownload("../src/font.bin", 1);
bus.QueueDownload("../MiSTer.pf", 1);
#ifdef WIN32
@@ -243,51 +243,37 @@ int main(int argc, char** argv, char** env) {
ImGui::Image(video.texture_id, ImVec2(video.output_width * m, video.output_height * m));
ImGui::End();
ImGui::Begin("PGROM Editor");
mem_edit_1.DrawContents(top->top__DOT__soc__DOT__pgrom__DOT__mem, 4096, 0);
ImGui::End();
ImGui::Begin("CHROM Editor");
mem_edit_1.DrawContents(top->top__DOT__soc__DOT__chrom__DOT__mem, 1024, 0);
ImGui::End();
//ImGui::Begin("RAM Editor");
// mem_edit_2.DrawContents(top->top__DOT__soc__DOT__ram__DOT__mem, 4096, 0);
// ImGui::End();
//ImGui::Begin("VRAM Editor");
//mem_edit_3.DrawContents(top->top__DOT__soc__DOT__video__DOT__vmem, 320*200, 0);
//ImGui::End();
//ImGui::Begin("PGROM Editor");
//mem_edit_1.DrawContents(top->top__DOT__soc__DOT__pgrom__DOT__mem, 16384, 0);
//ImGui::End();
//ImGui::Begin("CHROM Editor");
//mem_edit_1.DrawContents(top->top__DOT__soc__DOT__chrom__DOT__mem, 1024, 0);
//ImGui::End();
//ImGui::Begin("WKRAM Editor");
//mem_edit_2.DrawContents(top->top__DOT__soc__DOT__wkram__DOT__mem, 16384, 0);
//ImGui::End();
//ImGui::Begin("CHRAM Editor");
//mem_edit_3.DrawContents(top->top__DOT__soc__DOT__chram__DOT__mem, 2048, 0);
//ImGui::End();
//ImGui::Begin("COLRAM Editor");
//mem_edit_3.DrawContents(top->top__DOT__soc__DOT__colram__DOT__mem, 2048, 0);
//ImGui::End();
ImGui::Begin("CPU Registers");
ImGui::Spacing();
ImGui::Text("PC 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__PC);
ImGui::Text("ACC 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__ACC);
ImGui::Text("Main Registers");
/*
ImGui::Text("B 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__B);
ImGui::Text("C 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__C);
ImGui::Text("D 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__D);
ImGui::Text("E 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__E);
ImGui::Text("H 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__H);
ImGui::Text("L 0x%02X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__L);
*/
//ImGui::Spacing();
//ImGui::Separator();
//ImGui::Text("16 bit Registers");
/*
ImGui::Text("IX 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__IX);
ImGui::Text("IY 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__i_reg__DOT__IY);
ImGui::Text("SP 0x%04X", top->top__DOT__soc__DOT__T80x__DOT__i_tv80_core__DOT__SP);
*/
ImGui::End();
video.UpdateTexture();
// Pass inputs to sim
top->inputs = 0;
top->joystick_0 = 0;
for (int i = 0; i < input.inputCount; i++)
{
if (input.inputs[i]) { top->inputs |= (1 << i); }
if (input.inputs[i]) { top->joystick_0 |= (1 << i); }
}
top->joystick_1 = top->joystick_0;
// Run simulation
if (run_enable) {

2
verilator/verilate.sh
View File

@@ -1,5 +1,5 @@
#verilator -cc -exe --public --compiler msvc --converge-limit 2000 -Wno-WIDTH -Wno-IMPLICIT -Wno-MODDUP -Wno-UNSIGNED -Wno-CASEINCOMPLETE -Wno-CASEX -Wno-SYMRSVDWORD -Wno-COMBDLY -Wno-INITIALDLY -Wno-BLKANDNBLK -Wno-UNOPTFLAT -Wno-SELRANGE -Wno-CMPCONST -Wno-CASEOVERLAP -Wno-PINMISSING --top-module top sim.v \
verilator -cc -exe --public --compiler msvc +define+SIMULATION=1 +define+SIMULATION_VTIMER=1 --converge-limit 2000 --top-module top sim.v \
verilator -cc -exe --public --compiler msvc +define+SIMULATION=1 --converge-limit 2000 --top-module top sim.v \
../rtl/dpram.v \
../rtl/spram.v \
../rtl/JTFRAME/jtframe_vtimer.v \