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Update backup load/save.

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This commit is contained in:
sorgelig
2019-01-10 04:18:01 +08:00
parent 256d3405be
commit ffb0e5d38f
7 changed files with 269 additions and 129 deletions
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4
Genesis-vip.qsf
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@@ -366,14 +366,14 @@ set_global_assignment -name QIP_FILE FX68K/fx68k.qip
set_global_assignment -name QIP_FILE T80/t80.qip
set_global_assignment -name QIP_FILE jt12/jt12.qip
set_global_assignment -name QIP_FILE jt89/jt89.qip
set_global_assignment -name VHDL_FILE bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE compressor.sv
set_global_assignment -name VHDL_FILE vdp.vhd
set_global_assignment -name VERILOG_FILE gen_io.v
set_global_assignment -name SYSTEMVERILOG_FILE teamplayer.sv
set_global_assignment -name VERILOG_FILE fourway.v
set_global_assignment -name SYSTEMVERILOG_FILE multitap.sv
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE system.sv
set_global_assignment -name SYSTEMVERILOG_FILE Genesis.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
Genesis.qsf
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@@ -367,14 +367,14 @@ set_global_assignment -name QIP_FILE FX68K/fx68k.qip
set_global_assignment -name QIP_FILE T80/t80.qip
set_global_assignment -name QIP_FILE jt12/jt12.qip
set_global_assignment -name QIP_FILE jt89/jt89.qip
set_global_assignment -name VHDL_FILE bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE compressor.sv
set_global_assignment -name VHDL_FILE vdp.vhd
set_global_assignment -name VERILOG_FILE gen_io.v
set_global_assignment -name SYSTEMVERILOG_FILE teamplayer.sv
set_global_assignment -name VERILOG_FILE fourway.v
set_global_assignment -name SYSTEMVERILOG_FILE multitap.sv
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE system.sv
set_global_assignment -name SYSTEMVERILOG_FILE Genesis.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

22
Genesis.sv
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@@ -133,14 +133,10 @@ localparam CONF_STR1 = {
"-;",
};
localparam CONF_STR2 = {
"DE,Save Slot,1,2,3,4;"
};
localparam CONF_STR3 = {
"G,Load Backup RAM;"
};
localparam CONF_STR4 = {
localparam CONF_STR3 = {
"H,Save Backup RAM;",
"-;",
"O9,Aspect ratio,4:3,16:9;",
@@ -188,12 +184,12 @@ wire forced_scandoubler;
wire [10:0] ps2_key;
wire [24:0] ps2_mouse;
hps_io #(.STRLEN(($size(CONF_STR1)>>3) + ($size(CONF_STR2)>>3) + ($size(CONF_STR3)>>3) + ($size(CONF_STR4)>>3) + 3), .PS2DIV(1000), .WIDE(1)) hps_io
hps_io #(.STRLEN(($size(CONF_STR1)>>3) + ($size(CONF_STR2)>>3) + ($size(CONF_STR3)>>3) + 2), .PS2DIV(1000), .WIDE(1)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str({CONF_STR1,bk_ena ? "O" : "+",CONF_STR2,bk_ena ? "R" : "+",CONF_STR3,bk_ena ? "R" : "+",CONF_STR4}),
.conf_str({CONF_STR1,bk_ena ? "R" : "+",CONF_STR2,bk_ena ? "R" : "+",CONF_STR3}),
.joystick_0(joystick_0),
.joystick_1(joystick_1),
.joystick_2(joystick_2),
@@ -497,8 +493,11 @@ reg bk_loading = 0;
reg bk_state = 0;
always @(posedge clk_sys) begin
reg old_downloading = 0;
reg old_load = 0, old_save = 0, old_ack;
old_downloading <= downloading;
old_load <= bk_load;
old_save <= bk_save;
old_ack <= sd_ack;
@@ -509,10 +508,17 @@ always @(posedge clk_sys) begin
if(bk_ena & ((~old_load & bk_load) | (~old_save & bk_save))) begin
bk_state <= 1;
bk_loading <= bk_load;
sd_lba <= {23'd0,status[14:13],7'd0};
sd_lba <= 0;
sd_rd <= bk_load;
sd_wr <= ~bk_load;
end
if(old_downloading & ~ioctl_download & bk_ena) begin
bk_state <= 1;
bk_loading <= 1;
sd_lba <= 0;
sd_rd <= 1;
sd_wr <= 0;
end
end else begin
if(old_ack & ~sd_ack) begin
if(&sd_lba[6:0]) begin

4
Genesis_Q13.qsf
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@@ -367,14 +367,14 @@ set_global_assignment -name QIP_FILE FX68K/fx68k.qip
set_global_assignment -name QIP_FILE T80/t80.qip
set_global_assignment -name QIP_FILE jt12/jt12.qip
set_global_assignment -name QIP_FILE jt89/jt89.qip
set_global_assignment -name VHDL_FILE bram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE compressor.sv
set_global_assignment -name VHDL_FILE vdp.vhd
set_global_assignment -name VERILOG_FILE gen_io.v
set_global_assignment -name SYSTEMVERILOG_FILE teamplayer.sv
set_global_assignment -name VERILOG_FILE fourway.v
set_global_assignment -name SYSTEMVERILOG_FILE multitap.sv
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name SYSTEMVERILOG_FILE system.sv
set_global_assignment -name SYSTEMVERILOG_FILE Genesis.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

236
bram.vhd Normal file
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@@ -0,0 +1,236 @@
--------------------------------------------------------------
-- Single port Block RAM
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width : integer := 8;
data_width : integer := 8;
mem_init_file : string := " ";
mem_name : string := "MEM" -- for InSystem Memory content editor.
);
PORT
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable : in STD_LOGIC := '1';
wren : in STD_LOGIC := '0';
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs : in std_logic := '1'
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
spram_sz : work.spram_sz
generic map(addr_width, data_width, 2**addr_width, mem_init_file, mem_name)
port map(clock,address,data,enable,wren,q,cs);
END SYN;
--------------------------------------------------------------
-- Single port Block RAM with specific size
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram_sz IS
generic (
addr_width : integer := 8;
data_width : integer := 8;
numwords : integer := 2**8;
mem_init_file : string := " ";
mem_name : string := "MEM" -- for InSystem Memory content editor.
);
PORT
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable : in STD_LOGIC := '1';
wren : in STD_LOGIC := '0';
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs : in std_logic := '1'
);
END ENTITY;
ARCHITECTURE SYN OF spram_sz IS
signal q0 : std_logic_vector((data_width - 1) downto 0);
BEGIN
q<= q0 when cs = '1' else (others => '1');
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME="&mem_name,
lpm_type => "altsyncram",
numwords_a => numwords,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
init_file => mem_init_file,
widthad_a => addr_width,
width_a => data_width,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren and cs,
q_a => q0
);
END SYN;
--------------------------------------------------------------
-- Dual port Block RAM same parameters on both ports
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width : integer := 8;
data_width : integer := 8;
mem_init_file : string := " "
);
PORT
(
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_b : in std_logic := '1'
);
end entity;
ARCHITECTURE SYN OF dpram IS
BEGIN
ram : work.dpram_dif generic map(addr_width,data_width,addr_width,data_width,mem_init_file)
port map(clock,address_a,data_a,enable_a,wren_a,q_a,cs_a,address_b,data_b,enable_b,wren_b,q_b,cs_b);
END SYN;
--------------------------------------------------------------
-- Dual port Block RAM different parameters on ports
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram_dif is
generic (
addr_width_a : integer := 8;
data_width_a : integer := 8;
addr_width_b : integer := 8;
data_width_b : integer := 8;
mem_init_file : string := " "
);
PORT
(
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width_a-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width_b-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0);
cs_b : in std_logic := '1'
);
end entity;
ARCHITECTURE SYN OF dpram_dif IS
signal q0 : std_logic_vector((data_width_a - 1) downto 0);
signal q1 : std_logic_vector((data_width_b - 1) downto 0);
BEGIN
q_a<= q0 when cs_a = '1' else (others => '1');
q_b<= q1 when cs_b = '1' else (others => '1');
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_a,
numwords_b => 2**addr_width_b,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
init_file => mem_init_file,
widthad_a => addr_width_a,
widthad_b => addr_width_b,
width_a => data_width_a,
width_b => data_width_b,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
clock1 => clock,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a and cs_a,
wren_b => wren_b and cs_b,
q_a => q0,
q_b => q1
);
END SYN;

88
dpram.vhd
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@@ -1,88 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width : integer := 8;
data_width : integer := 8;
mem_init_file : string := " ";
outdata_reg : string := "UNREGISTERED"
);
PORT
(
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
cs_b : in std_logic := '1'
);
end entity;
ARCHITECTURE SYN OF dpram IS
signal q0 : std_logic_vector((data_width - 1) downto 0);
signal q1 : std_logic_vector((data_width - 1) downto 0);
BEGIN
q_a<= q0 when cs_a = '1' else (others => '1');
q_b<= q1 when cs_b = '1' else (others => '1');
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 2**addr_width,
numwords_b => 2**addr_width,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg,
outdata_reg_b => outdata_reg,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
init_file => mem_init_file,
widthad_a => addr_width,
widthad_b => addr_width,
width_a => data_width,
width_b => data_width,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
clock1 => clock,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a and cs_a,
wren_b => wren_b and cs_b,
q_a => q0,
q_b => q1
);
END SYN;

40
system.sv
View File

@@ -463,35 +463,21 @@ end
//-----------------------------------------------------------------------
reg SRAM_SEL;
dpram #(15) sram_u
dpram_dif #(16,8,15,16) sram
(
.clock(MCLK),
.address_a(MBUS_A[15:1]),
.data_a(MBUS_DO[15:8]),
.wren_a(SRAM_SEL & ~MBUS_RNW & ~MBUS_UDS_N),
.q_a(sram_q[15:8]),
.address_b(LOADING ? ram_rst_a : BRAM_A[14:0]),
.data_b(LOADING ? 8'h00 : BRAM_DI[15:8]),
.wren_b(LOADING | BRAM_WE),
.q_b(BRAM_DO[15:8])
);
dpram #(15) sram_l
(
.clock(MCLK),
.address_a(MBUS_A[15:1]),
.address_a(MBUS_A[16:1]),
.data_a(MBUS_DO[7:0]),
.wren_a(SRAM_SEL & ~MBUS_RNW & ~MBUS_LDS_N),
.wren_a(SRAM_SEL & ~MBUS_RNW),
.q_a(sram_q[7:0]),
.address_b(LOADING ? ram_rst_a : BRAM_A[14:0]),
.data_b(LOADING ? 8'h00 : BRAM_DI[7:0]),
.address_b(LOADING ? ram_rst_a : BRAM_A),
.data_b(LOADING ? 16'h0000 : BRAM_DI),
.wren_b(LOADING | BRAM_WE),
.q_b(BRAM_DO[7:0])
.q_b(BRAM_DO)
);
wire [15:0] sram_q;
wire [7:0] sram_q;
//-----------------------------------------------------------------------
// 68K RAM
@@ -618,11 +604,7 @@ always @(posedge MCLK) begin
//NO DEVICE (usually lockup on real HW)
mstate <= MBUS_FINISH;
if ((MULTITAP == 3) && ({MBUS_A,1'b0} == 'h3FFFFE || {MBUS_A,1'b0} == 'h38FFFE)) begin
JCART_SEL <= 1;
mstate <= MBUS_JCRT_READ;
end
else if(MBUS_A[23:20]<'hA || (msrc == MSRC_Z80 && MBUS_A[23:20]<'hE && ROMSZ[24:20]>='hA)) begin
if(MBUS_A[23:20]<'hA || (msrc == MSRC_Z80 && MBUS_A[23:20]<'hE && ROMSZ[24:20]>='hA)) begin
//ROM: 000000-9FFFFF (A00000-DFFFFF)
if (EEPROM_QUIRK && {MBUS_A,1'b0} == 'h200000) begin
@@ -637,6 +619,10 @@ always @(posedge MCLK) begin
ROM_REQ <= ~ROM_ACK;
mstate <= MBUS_ROM_READ;
end
else if ((MULTITAP == 3) && ({MBUS_A,1'b0} == 'h3FFFFE || {MBUS_A,1'b0} == 'h38FFFE)) begin
JCART_SEL <= 1;
mstate <= MBUS_JCRT_READ;
end
else if(MBUS_A[23:21] == 1 && ~&MBUS_A[20:19]) begin
// 200000-37FFFF
SRAM_SEL <= 1;
@@ -727,7 +713,7 @@ always @(posedge MCLK) begin
MBUS_SRAM_READ:
begin
data <= sram_q;
data <= {sram_q,sram_q};
mstate <= MBUS_FINISH;
end