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Update sys.

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sorgelig
2019-10-19 22:09:44 +08:00
parent c05b83ba3a
commit dcd0bb69a9
3 changed files with 16 additions and 16 deletions
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5
sys/ascal.vhd
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@@ -287,7 +287,7 @@ ARCHITECTURE rtl OF ascal IS
TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12;
----------------------------------------------------------
-- Input image
SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
@@ -386,7 +386,8 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
SIGNAL o_format : unsigned(5 DOWNTO 0);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
SIGNAL pal_mem : arr_uv24(0 TO 255);
SIGNAL pal_mem : arr_uv24(0 TO 255);
ATTRIBUTE ramstyle of pal_mem : signal is "no_rw_check";
SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
SIGNAL o_hsize,o_vsize : uint12;

25
sys/gamma_corr.sv
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@@ -19,18 +19,17 @@ module gamma_corr
output reg [23:0] RGB_out
);
reg [7:0] gamma_curve[768];
always @(posedge clk_sys) begin
if (gamma_wr) begin
gamma_curve[gamma_wr_addr] <= gamma_value;
end
end
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
reg [9:0] gamma_index;
wire [7:0] gamma = gamma_curve[gamma_index];
reg [7:0] gamma;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma, B_gamma;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb;
reg [1:0] ctr = 0;
@@ -39,7 +38,7 @@ always @(posedge clk_vid) begin
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
RGB_out <= gamma_en ? {R_gamma,G_gamma,B_gamma} : {R_in,G_in,B_in};
RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
@@ -50,10 +49,10 @@ always @(posedge clk_vid) begin
if (|ctr) ctr <= ctr + 1'd1;
case(ctr)
1: begin R_gamma <= gamma; gamma_index <= {2'b01,G_in}; end
2: begin G_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
3: begin B_gamma <= gamma; end
1: begin gamma_index <= {2'b01,G_in}; end
2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
3: begin G_gamma <= gamma; end
endcase
end
endmodule
endmodule

2
sys/osd.v
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@@ -33,7 +33,7 @@ localparam OSD_HDR = 12'd0;
`endif
reg osd_enable;
reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
reg info = 0;
reg [8:0] infoh;