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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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Fix Serial Link
There was a typo in link.v preventing internal clock from working properly
This commit is contained in:
10
Gameboy.sv
10
Gameboy.sv
@@ -599,7 +599,6 @@ gb gb (
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.serial_data_in(ser_data_in),
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.serial_clk_out(ser_clk_out),
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.serial_data_out(ser_data_out),
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.serial_ena(status[6]),
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// Palette download will disable cheats option (HPS doesn't distinguish downloads),
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// so clear the cheats and disable second option (chheats enable/disable)
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@@ -808,12 +807,13 @@ wire ser_data_in;
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wire ser_data_out;
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wire ser_clk_in;
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wire ser_clk_out;
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wire serial_ena = status[6];
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assign ser_data_in = USER_IN[2];
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assign USER_OUT[1] = ser_data_out;
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assign ser_data_in = serial_ena ? USER_IN[2] : 1'b1;
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assign USER_OUT[1] = serial_ena ? ser_data_out : 1'b1;
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assign ser_clk_in = USER_IN[0];
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assign USER_OUT[0] = sc_int_clock_out?ser_clk_out:1'b1;
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assign ser_clk_in = serial_ena ? USER_IN[0] : 1'b1;
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assign USER_OUT[0] = (serial_ena & sc_int_clock_out) ? ser_clk_out : 1'b1;
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61
rtl/gb.v
61
rtl/gb.v
@@ -65,7 +65,6 @@ module gb (
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output gg_available,
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//serial port
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input serial_ena,
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output sc_int_clock2,
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input serial_clk_in,
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output serial_clk_out,
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@@ -130,7 +129,7 @@ wire [7:0] cpu_di =
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isGBC&&sel_hdma?{hdma_do}: //hdma GBC
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isGBC&&sel_key1?{cpu_speed,6'h3f,prepare_switch}: //key1 cpu speed register(GBC)
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sel_joy?joy_do: // joystick register
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sel_sb?sb: // serial transfer data register
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sel_sb?sb_o: // serial transfer data register
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sel_sc?sc_r: // serial transfer control register
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sel_timer?timer_do: // timer registers
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sel_video_reg?video_do: // video registers
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@@ -260,16 +259,11 @@ gbc_snd audio (
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// -----------------------serial port()--------------------------------
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// --------------------------------------------------------------------
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wire serial_irq = serial_ena ? serial_irq_s : serial_irq_f;
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wire [7:0] sb = serial_ena ? sb_s : 8'hFF;
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wire sc_start = serial_ena ? sc_start_s : sc_start_f;
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wire sc_shiftclock = serial_ena ? sc_shiftclock_s : sc_shiftclock_f;
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// SNAC
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wire serial_irq_s;
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wire [7:0] sb_s;
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wire sc_start_s;
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wire sc_shiftclock_s;
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wire serial_irq;
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wire [7:0] sb_o;
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wire sc_start;
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wire sc_shiftclock;
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assign sc_int_clock2 = sc_shiftclock;
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@@ -290,50 +284,13 @@ link link (
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.serial_clk_out(serial_clk_out),
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.serial_data_out(serial_data_out),
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.sb(sb_s),
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.serial_irq(serial_irq_s),
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.sc_start(sc_start_s),
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.sc_int_clock(sc_shiftclock_s)
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.sb(sb_o),
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.serial_irq(serial_irq),
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.sc_start(sc_start),
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.sc_int_clock(sc_shiftclock)
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);
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// Fake
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reg sc_start_f,sc_shiftclock_f;
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reg serial_irq_f;
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always @(posedge clk_cpu) begin
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reg [3:0] serial_counter;
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reg [8:0] serial_clk_div; //8192Hz
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serial_irq_f <= 1'b0;
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if(reset_r) begin
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sc_start_f <= 1'b0;
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sc_shiftclock_f <= 1'b0;
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end else if (sel_sc && !cpu_wr_n) begin //cpu write
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sc_start_f <= cpu_do[7];
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sc_shiftclock_f <= cpu_do[0];
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if (cpu_do[7]) begin //enable transfer
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serial_clk_div <= 9'h1FF;
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serial_counter <= 4'd8;
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end
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end else if (sc_start_f && sc_shiftclock_f) begin // serial transfer and serial clock enabled
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serial_clk_div <= serial_clk_div - 9'd1;
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if (serial_clk_div == 9'd0 && serial_counter)
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serial_counter <= serial_counter - 4'd1;
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if (!serial_counter) begin
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serial_irq_f <= 1'b1; //trigger interrupt
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sc_start_f <= 1'b0; //reset transfer state
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serial_clk_div <= 9'h1FF;
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serial_counter <= 4'd8;
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end
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end
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end
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// --------------------------------------------------------------------
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// ------------------------------ inputs ------------------------------
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// --------------------------------------------------------------------
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@@ -69,7 +69,7 @@ always @(posedge clk) begin
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serial_clk_div <= serial_clk_div - 9'd1;
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if (serial_counter != 0) begin
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if (serial_clk_div == {1'b0,CLK_DIV[8:1]+1'd1}) begin
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if (serial_clk_div == CLK_DIV/2+1) begin
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serial_clk_out_r <= ~serial_clk_out_r;
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serial_out_r <= sb[7];
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end else if (!serial_clk_div) begin
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