Fix Serial Link

There was a typo in link.v preventing internal clock from working
properly
This commit is contained in:
paulb-nl
2020-12-15 00:30:57 +01:00
parent 45679e5068
commit f89cc5c0bb
3 changed files with 15 additions and 58 deletions

View File

@@ -599,7 +599,6 @@ gb gb (
.serial_data_in(ser_data_in),
.serial_clk_out(ser_clk_out),
.serial_data_out(ser_data_out),
.serial_ena(status[6]),
// Palette download will disable cheats option (HPS doesn't distinguish downloads),
// so clear the cheats and disable second option (chheats enable/disable)
@@ -808,12 +807,13 @@ wire ser_data_in;
wire ser_data_out;
wire ser_clk_in;
wire ser_clk_out;
wire serial_ena = status[6];
assign ser_data_in = USER_IN[2];
assign USER_OUT[1] = ser_data_out;
assign ser_data_in = serial_ena ? USER_IN[2] : 1'b1;
assign USER_OUT[1] = serial_ena ? ser_data_out : 1'b1;
assign ser_clk_in = USER_IN[0];
assign USER_OUT[0] = sc_int_clock_out?ser_clk_out:1'b1;
assign ser_clk_in = serial_ena ? USER_IN[0] : 1'b1;
assign USER_OUT[0] = (serial_ena & sc_int_clock_out) ? ser_clk_out : 1'b1;

View File

@@ -65,7 +65,6 @@ module gb (
output gg_available,
//serial port
input serial_ena,
output sc_int_clock2,
input serial_clk_in,
output serial_clk_out,
@@ -130,7 +129,7 @@ wire [7:0] cpu_di =
isGBC&&sel_hdma?{hdma_do}: //hdma GBC
isGBC&&sel_key1?{cpu_speed,6'h3f,prepare_switch}: //key1 cpu speed register(GBC)
sel_joy?joy_do: // joystick register
sel_sb?sb: // serial transfer data register
sel_sb?sb_o: // serial transfer data register
sel_sc?sc_r: // serial transfer control register
sel_timer?timer_do: // timer registers
sel_video_reg?video_do: // video registers
@@ -260,16 +259,11 @@ gbc_snd audio (
// -----------------------serial port()--------------------------------
// --------------------------------------------------------------------
wire serial_irq = serial_ena ? serial_irq_s : serial_irq_f;
wire [7:0] sb = serial_ena ? sb_s : 8'hFF;
wire sc_start = serial_ena ? sc_start_s : sc_start_f;
wire sc_shiftclock = serial_ena ? sc_shiftclock_s : sc_shiftclock_f;
// SNAC
wire serial_irq_s;
wire [7:0] sb_s;
wire sc_start_s;
wire sc_shiftclock_s;
wire serial_irq;
wire [7:0] sb_o;
wire sc_start;
wire sc_shiftclock;
assign sc_int_clock2 = sc_shiftclock;
@@ -290,50 +284,13 @@ link link (
.serial_clk_out(serial_clk_out),
.serial_data_out(serial_data_out),
.sb(sb_s),
.serial_irq(serial_irq_s),
.sc_start(sc_start_s),
.sc_int_clock(sc_shiftclock_s)
.sb(sb_o),
.serial_irq(serial_irq),
.sc_start(sc_start),
.sc_int_clock(sc_shiftclock)
);
// Fake
reg sc_start_f,sc_shiftclock_f;
reg serial_irq_f;
always @(posedge clk_cpu) begin
reg [3:0] serial_counter;
reg [8:0] serial_clk_div; //8192Hz
serial_irq_f <= 1'b0;
if(reset_r) begin
sc_start_f <= 1'b0;
sc_shiftclock_f <= 1'b0;
end else if (sel_sc && !cpu_wr_n) begin //cpu write
sc_start_f <= cpu_do[7];
sc_shiftclock_f <= cpu_do[0];
if (cpu_do[7]) begin //enable transfer
serial_clk_div <= 9'h1FF;
serial_counter <= 4'd8;
end
end else if (sc_start_f && sc_shiftclock_f) begin // serial transfer and serial clock enabled
serial_clk_div <= serial_clk_div - 9'd1;
if (serial_clk_div == 9'd0 && serial_counter)
serial_counter <= serial_counter - 4'd1;
if (!serial_counter) begin
serial_irq_f <= 1'b1; //trigger interrupt
sc_start_f <= 1'b0; //reset transfer state
serial_clk_div <= 9'h1FF;
serial_counter <= 4'd8;
end
end
end
// --------------------------------------------------------------------
// ------------------------------ inputs ------------------------------
// --------------------------------------------------------------------

View File

@@ -69,7 +69,7 @@ always @(posedge clk) begin
serial_clk_div <= serial_clk_div - 9'd1;
if (serial_counter != 0) begin
if (serial_clk_div == {1'b0,CLK_DIV[8:1]+1'd1}) begin
if (serial_clk_div == CLK_DIV/2+1) begin
serial_clk_out_r <= ~serial_clk_out_r;
serial_out_r <= sb[7];
end else if (!serial_clk_div) begin