mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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MBC: added full support for MBC5(8mb ROM and 128kb SRAM)
This commit is contained in:
Bruno Duarte Gouveia
151
Gameboy.sv
151
Gameboy.sv
@@ -237,7 +237,7 @@ wire palette_download = ioctl_download && (filetype == 8'h05 || filetype == 8'h0
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wire [1:0] sdram_ds = cart_download ? 2'b11 : {cart_addr[0], ~cart_addr[0]};
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wire [15:0] sdram_do;
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wire [15:0] sdram_di = cart_download ? ioctl_dout : 16'd0;
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wire [23:0] sdram_addr = cart_download? ioctl_addr[24:1]: {3'b000, mbc_bank, cart_addr[12:1]};
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wire [23:0] sdram_addr = cart_download? ioctl_addr[24:1]: {2'b00, mbc_bank, cart_addr[12:1]};
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wire sdram_oe = ~cart_download & cart_rd & ~cram_rd;
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wire sdram_we = cart_download & dn_write;
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@@ -283,79 +283,76 @@ end
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///////////////////////////////////////////////////
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// TODO: RAM bank
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// http://fms.komkon.org/GameBoy/Tech/Carts.html
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// 32MB SDRAM memory map using word addresses
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// 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S
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// -------------------------------------------------
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// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM
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// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM
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// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM (MBC1-3), 8MB for MBC5
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// 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0)
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// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1)
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// ---------------------------------------------------------------
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// ----------------------------- MBC1 ----------------------------
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// ---------------------------------------------------------------
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wire [8:0] mbc1_addr =
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(cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127
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wire [9:0] mbc1_addr =
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(cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{2'b00, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127
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9'd0;
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wire [8:0] mbc2_addr =
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(cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{1'b0, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15
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wire [9:0] mbc2_addr =
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(cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{2'b00, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15
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9'd0;
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wire [8:0] mbc3_addr =
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(cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{mbc3_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127
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wire [9:0] mbc3_addr =
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(cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{2'b00,mbc3_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127
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9'd0;
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wire [8:0] mbc5_addr =
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(cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{mbc5_rom_bank, cart_addr[13]}: // 16k ROM Bank 0-127 for now , TODO: 0-480 after remapping sdram memory
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wire [9:0] mbc5_addr =
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(cart_addr[15:14] == 2'b00)?{9'd0, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{mbc5_rom_bank, cart_addr[13]}: // 16k ROM Bank 0-480 (0h-1E0h)
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9'd0;
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// -------------------------- RAM banking ------------------------
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// in mode 0 (16/8 mode) the ram is not banked
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// in mode 1 (4/32 mode) four ram banks are used
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wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc_ram_bank_reg:2'b00) & ram_mask;
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wire [1:0] mbc3_ram_bank = mbc_ram_bank_reg & ram_mask;
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wire [1:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask;
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wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc_ram_bank_reg[1:0]:2'b00) & ram_mask[1:0];
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wire [1:0] mbc3_ram_bank = mbc_ram_bank_reg[1:0] & ram_mask[1:0];
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wire [3:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask;
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// -------------------------- ROM banking ------------------------
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// in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines
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// in mode 1 (4/32 mode) the upper two rom address lines are 2'b00
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wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc_ram_bank_reg, mbc_rom_bank_reg[4:0]};
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wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc_ram_bank_reg[1:0], mbc_rom_bank_reg[4:0]};
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// in mode 0 map memory at A000-BFFF
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// in mode 1 map rtc register at A000-BFFF
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//wire [6:0] mbc3_ram_bank_addr = { mbc3_mode?2'b00:mbc3_ram_bank_reg, mbc3_rom_bank_reg};
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// mask address lines to enable proper mirroring
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wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask;//128
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wire [6:0] mbc2_rom_bank = mbc_rom_bank_reg & rom_mask; //16
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wire [6:0] mbc3_rom_bank = mbc_rom_bank_reg & rom_mask; //128
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wire [6:0] mbc5_rom_bank = mbc_rom_bank_reg & rom_mask; //128 for now
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wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask[6:0]; //128
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wire [6:0] mbc2_rom_bank = mbc_rom_bank_reg[6:0] & rom_mask[6:0]; //16
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wire [6:0] mbc3_rom_bank = mbc_rom_bank_reg[6:0] & rom_mask[6:0]; //128
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wire [8:0] mbc5_rom_bank = mbc_rom_bank_reg & rom_mask; //480
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// --------------------- CPU register interface ------------------
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reg mbc_ram_enable;
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reg mbc1_mode;
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reg mbc3_mode;
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reg [6:0] mbc_rom_bank_reg; // for now reg [8:0] when remapping sdram for 8mb rom (mbc5)
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reg [1:0] mbc_ram_bank_reg; // for now reg [2:0] when remapping sdram for 8mb rom (mbc5)
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reg [8:0] mbc_rom_bank_reg;
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reg [3:0] mbc_ram_bank_reg; //0-15
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always @(posedge clk_sys) begin
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if(reset) begin
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mbc_rom_bank_reg <= 5'd1;
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mbc_ram_bank_reg <= 2'd0;
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mbc_ram_bank_reg <= 4'd0;
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mbc1_mode <= 1'b0;
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mbc3_mode <= 1'b0;
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mbc_ram_enable <= 1'b0;
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@@ -363,10 +360,15 @@ always @(posedge clk_sys) begin
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//write to ROM bank register
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if(cart_wr && (cart_addr[15:13] == 3'b001)) begin
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if(~mbc5 && cart_di[4:0]==0)
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if(~mbc5 && cart_di[6:0]==0) //special case mbc1-3 rombank 0=1
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mbc_rom_bank_reg <= 5'd1;
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else
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mbc_rom_bank_reg <= cart_di[6:0];
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else if (mbc5) begin
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if (cart_addr[13:12] == 2'b11) //3000-3FFF High bit
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mbc_rom_bank_reg[8] <= cart_di[0];
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else //2000-2FFF low 8 bits
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mbc_rom_bank_reg[7:0] <= cart_di[7:0];
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end else
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mbc_rom_bank_reg <= {2'b00,cart_di[6:0]}; //mbc1-3
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end
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//write to RAM bank register
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@@ -376,10 +378,13 @@ always @(posedge clk_sys) begin
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mbc3_mode <= 1'b1; //enable RTC
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else begin
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mbc3_mode <= 1'b0; //enable RAM
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mbc_ram_bank_reg <= cart_di[1:0];
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mbc_ram_bank_reg <= {2'b00,cart_di[1:0]};
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end
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end else
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mbc_ram_bank_reg <= cart_di[1:0];
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if (mbc5)//can probably be simplified
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mbc_ram_bank_reg <= cart_di[3:0];
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else
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mbc_ram_bank_reg <= {2'b00,cart_di[1:0]};
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end
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// MBC1 ROM/RAM Mode Select
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@@ -400,25 +405,26 @@ reg [7:0] cart_rom_size;
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reg [7:0] cart_ram_size;
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// RAM size
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wire [1:0] ram_mask = // 0 - no ram
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(cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank
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(cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank
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2'b11; // 3 - 32k, 4 banks
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wire [3:0] ram_mask = // 0 - no ram
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(cart_ram_size == 1)?4'b0000: // 1 - 2k, 1 bank
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(cart_ram_size == 2)?4'b0000: // 2 - 8k, 1 bank
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(cart_ram_size == 3)?4'b0011: // 3 - 32k, 4 banks
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4'b1111; // 4 - 128k 16 banks
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// ROM size
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wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped
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(cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k
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(cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k
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(cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k
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(cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k
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(cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M
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(cart_rom_size == 6)?7'b1111111: // 6 - 128 banks = 2M
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//? (cart_rom_size == 6)?7'b1111111: // 7 - ??? banks = 4M
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//? (cart_rom_size == 6)?7'b1111111: // 8 - ??? banks = 8M
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(cart_rom_size == 82)?7'b1000111: //$52 - 72 banks = 1.1M
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(cart_rom_size == 83)?7'b1001111: //$53 - 80 banks = 1.2M
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// (cart_rom_size == 84)?7'b1011111:
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7'b1011111; // $54 - 96 banks = 1.5M
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wire [8:0] rom_mask = // 0 - 2 banks, 32k direct mapped
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(cart_rom_size == 1)? 9'b000000011: // 1 - 4 banks = 64k
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(cart_rom_size == 2)? 9'b000000111: // 2 - 8 banks = 128k
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(cart_rom_size == 3)? 9'b000001111: // 3 - 16 banks = 256k
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(cart_rom_size == 4)? 9'b000011111: // 4 - 32 banks = 512k
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(cart_rom_size == 5)? 9'b000111111: // 5 - 64 banks = 1M
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(cart_rom_size == 6)? 9'b001111111: // 6 - 128 banks = 2M
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(cart_rom_size == 7)? 9'b011111111: // 7 - 256 banks = 4M
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(cart_rom_size == 8)? 9'b111111111: // 8 - 512 banks = 8M
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(cart_rom_size == 82)?9'b001111111: //$52 - 72 banks = 1.1M
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(cart_rom_size == 83)?9'b001111111: //$53 - 80 banks = 1.2M
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(cart_rom_size == 84)?9'b001111111:
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9'b001111111; //$54 - 96 banks = 1.5M
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wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3);
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wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6);
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@@ -431,7 +437,7 @@ wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type ==
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//wire HuC1 = (cart_mbc_type == 254);
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//wire HuC3 = (cart_mbc_type == 255);
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wire [8:0] mbc_bank =
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wire [9:0] mbc_bank =
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mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram
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mbc2?mbc2_addr: // MBC2, 16k bank 0, 16k bank 1-15 + ram
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mbc3?mbc3_addr:
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@@ -439,7 +445,7 @@ wire [8:0] mbc_bank =
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// tama5?tama5_addr:
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// HuC1?HuC1_addr:
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// HuC3?HuC3_addr:
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{7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address
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{8'd0, cart_addr[14:13]}; // no MBC, 32k linear address
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reg [127:0] palette = 128'h828214517356305A5F1A3B4900000000;
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@@ -568,7 +574,7 @@ end
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///////////////////////// BRAM SAVE/LOAD /////////////////////////////
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wire [14:0] bk_addr = {sd_lba[5:0],sd_buff_addr};
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wire [16:0] bk_addr = {sd_lba[7:0],sd_buff_addr};
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wire bk_wr = sd_buff_wr & sd_ack;
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wire [15:0] bk_data = sd_buff_dout;
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wire [15:0] bk_q;
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@@ -590,40 +596,36 @@ wire [7:0] cram_q_l;
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wire is_cram_addr = (cart_addr[15:13] == 3'b101);
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wire cram_rd = cart_rd & is_cram_addr;
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wire cram_wr = cart_wr & is_cram_addr;
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wire [14:0] cram_addr =
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mbc1 ?
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{mbc1_ram_bank, cart_addr[12:0]}:
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mbc3 ?
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{mbc3_ram_bank, cart_addr[12:0]}:
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mbc5 ?
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{mbc5_ram_bank, cart_addr[12:0]}:
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{2'b00, cart_addr[12:0]};
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wire [16:0] cram_addr = mbc1? {2'b00,mbc1_ram_bank, cart_addr[12:0]}:
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mbc3? {2'b00,mbc3_ram_bank, cart_addr[12:0]}:
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mbc5? {mbc5_ram_bank, cart_addr[12:0]}:
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{4'd0, cart_addr[12:0]};
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// Up to 8kb * 4banks of Cart Ram
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// Up to 8kb * 16banks of Cart Ram (128kb)
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dpram #(14) cram_l (
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dpram #(16) cram_l (
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.clock_a (clk_cpu),
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.address_a (cram_addr[14:1]),
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.address_a (cram_addr[16:1]),
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.wren_a (cram_wr & ~cram_addr[0]),
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.data_a (cart_di),
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.q_a (cram_q_l),
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.clock_b (clk_sys),
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.address_b (bk_addr[14:1]),
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.address_b (bk_addr[16:1]),
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.wren_b (bk_wr & ~bk_addr[0]),
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.data_b (bk_data[7:0]),
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.q_b (bk_q[7:0])
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);
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dpram #(14) cram_h (
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dpram #(16) cram_h (
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.clock_a (clk_cpu),
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.address_a (cram_addr[14:1]),
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.address_a (cram_addr[16:1]),
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.wren_a (cram_wr & cram_addr[0]),
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.data_a (cart_di),
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.q_a (cram_q_h),
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.clock_b (clk_sys),
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.address_b (bk_addr[14:1]),
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.address_b (bk_addr[16:1]),
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.wren_b (bk_wr & bk_addr[0]),
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.data_b (bk_data[15:8]),
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.q_b (bk_q[15:8])
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@@ -647,6 +649,14 @@ wire bk_save = status[10];
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reg bk_loading = 0;
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reg bk_state = 0;
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// RAM size
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wire [7:0] ram_mask_file = // 0 - no ram
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(mbc2)?8'h01: // mbc2 512x4bits
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(cart_ram_size == 1)?8'h03: // 1 - 2k, 1 bank sd_lba[1:0]
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(cart_ram_size == 2)?8'h0F: // 2 - 8k, 1 bank sd_lba[3:0]
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(cart_ram_size == 3)?8'h3F: // 3 - 32k, 4 banks sd_lba[5:0]
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8'hFF; // 4 - 128k 16 banks sd_lba[7:0] 1111
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always @(posedge clk_sys) begin
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reg old_load = 0, old_save = 0, old_ack;
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@@ -666,7 +676,8 @@ always @(posedge clk_sys) begin
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end
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end else begin
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if(old_ack & ~sd_ack) begin
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if(&sd_lba[5:0]) begin
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if(sd_lba[7:0]>=ram_mask_file) begin
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bk_loading <= 0;
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bk_state <= 0;
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end else begin
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