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Update sys, fix scandoubler.

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This commit is contained in:
sorgelig
2019-04-25 23:57:50 +08:00
parent f2a19a9f60
commit e59add678c
4 changed files with 96 additions and 64 deletions
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2
sys/ascal.vhd
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@@ -967,7 +967,7 @@ BEGIN
(i_inter='0' OR i_flm='1'));
-- Detects third line for low lag mode
i_syncline<=to_std_logic(i_vcpt=i_vmin + 4);
i_syncline<=to_std_logic(i_vcpt=i_vmin + 20);
----------------------------------------------------
IF i_pde='1' AND i_de_pre='0' THEN

34
sys/hps_io.v
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@@ -38,12 +38,12 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
output reg [15:0] joystick_0,
output reg [15:0] joystick_1,
output reg [15:0] joystick_2,
output reg [15:0] joystick_3,
output reg [15:0] joystick_4,
output reg [15:0] joystick_5,
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [31:0] joystick_5,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
@@ -182,6 +182,7 @@ integer hcnt;
always @(posedge clk_vid) begin
integer vcnt;
reg old_vs= 0, old_de = 0, old_vmode = 0;
reg [3:0] resto = 0;
reg calch = 0;
if(ce_pix) begin
@@ -195,7 +196,12 @@ always @(posedge clk_vid) begin
if(old_vs & ~vs) begin
if(hcnt && vcnt) begin
old_vmode <= new_vmode;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
//report new resolution after timeout
if(resto) resto <= resto + 1'd1;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
if(&resto) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
@@ -330,13 +336,13 @@ always@(posedge clk_sys) begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h02: joystick_0 <= io_din;
'h03: joystick_1 <= io_din;
'h10: joystick_2 <= io_din;
'h11: joystick_3 <= io_din;
'h12: joystick_4 <= io_din;
'h13: joystick_5 <= io_din;
'h01: cfg <= io_din[7:0];
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
// store incoming ps2 mouse bytes
'h04: begin

22
sys/hq2x.sv
View File

@@ -15,12 +15,15 @@
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input ce_in,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input ce_out,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel
@@ -129,6 +132,14 @@ hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_ou
.wren(wrout_en)
);
always @(posedge clk) begin
if(ce_out) begin
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
end
end
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs;
@@ -139,10 +150,7 @@ always @(posedge clk) begin
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(ce_in) begin
if(~&offs) begin
if (cyc == 1) begin
@@ -168,6 +176,7 @@ always @(posedge clk) begin
end
end
pattern <= new_pattern;
if(cyc==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
@@ -194,9 +203,6 @@ always @(posedge clk) begin
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
end

102
sys/scandoubler.v
View File

@@ -49,38 +49,27 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
//Compensate picture shift after HQ2x
assign vb_out = vbo[3];
assign hb_out = hbo[6];
reg [7:0] pix_len = 0;
reg [7:0] pix_cnt = 0;
wire [7:0] pl = pix_len + 1'b1;
wire [7:0] pc = pix_cnt + 1'b1;
reg ce_x4, ce_x2, ce_x1;
reg [7:0] pix_in_cnt = 0;
wire [7:0] pc_in = pix_in_cnt + 1'b1;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
reg ce_x4i, ce_x1i;
always @(negedge clk_sys) begin
reg old_ce, valid, hs;
reg [2:0] ce_cnt;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
if(~&pix_len) pix_len <= pl;
if(~&pix_cnt) pix_cnt <= pc;
if(~&pix_in_cnt) pix_in_cnt <= pc_in;
ce_x4 <= 0;
ce_x2 <= 0;
ce_x1 <= 0;
ce_x4i <= 0;
ce_x1i <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
if( pc == pixsz2) ce_x2 <= 1;
if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1;
old_ce <= ce_pix;
if(~old_ce & ce_pix) begin
@@ -93,41 +82,72 @@ always @(negedge clk_sys) begin
valid <= 1;
end
if(hb_in | vb_in) valid <= 0;
hs <= hs_in;
if((~hs & hs_in) || (pc_in >= pixsz)) begin
ce_x4i <= 1;
ce_x1i <= 1;
pix_in_cnt <= 0;
end
hs <= hs_out;
if((~hs & hs_out) || (pc >= pixsz)) begin
ce_x2 <= 1;
ce_x4 <= 1;
ce_x1 <= 1;
pix_cnt <= 0;
if(hb_in | vb_in) valid <= 0;
end
reg req_line_reset;
reg [DWIDTH:0] r_d, g_d, b_d;
always @(posedge clk_sys) begin
if(ce_x1i) begin
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
end
end
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4),
.ce_in(ce_x4i),
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vb_in),
.reset_line(req_line_reset),
.ce_out(ce_x4o),
.read_y(sd_line),
.hblank(hbo[0]&hbo[8]),
.outpixel({b_out,g_out,r_out})
);
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
reg [7:0] pix_out_cnt = 0;
wire [7:0] pc_out = pix_out_cnt + 1'b1;
reg ce_x4o, ce_x2o;
always @(negedge clk_sys) begin
reg hs;
if(~&pix_out_cnt) pix_out_cnt <= pc_out;
ce_x4o <= 0;
ce_x2o <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1;
if( pc_out == pixsz2) ce_x2o <= 1;
hs <= hs_out;
if((~hs & hs_out) || (pc_out >= pixsz)) begin
ce_x2o <= 1;
ce_x4o <= 1;
pix_out_cnt <= 0;
end
end
reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
reg req_line_reset;
always @(posedge clk_sys) begin
reg [31:0] hcnt;
@@ -137,7 +157,7 @@ always @(posedge clk_sys) begin
reg hs, hb;
if(ce_x4) begin
if(ce_x4o) begin
hbo[8:1] <= hbo[7:0];
end
@@ -164,13 +184,6 @@ always @(posedge clk_sys) begin
hs <= hs_in;
hb <= hb_in;
if(ce_x1) begin
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
end
hcnt <= hcnt + 1'd1;
if(hb && !hb_in) begin
hde_start <= hcnt[31:1];
@@ -192,4 +205,11 @@ always @(posedge clk_sys) begin
if(!hs && hs_in) hs_start <= hcnt[31:1];
end
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4o : ce_x2o;
//Compensate picture shift after HQ2x
assign vb_out = vbo[3];
assign hb_out = hbo[6];
endmodule