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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
synced 2026-05-17 03:03:43 +00:00
Add MBC6 & HuC3 mappers (#170)
This commit is contained in:
paulb-nl
GitHub
@@ -425,7 +425,8 @@ wire [9:0] mbc_bank;
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wire [7:0] ram_mask_file, cart_ram_size;
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wire isGBC_game, isSGB_game;
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wire cart_has_save;
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wire [31:0] RTC_timestampOut, RTC_savedtimeOut;
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wire [31:0] RTC_timestampOut;
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wire [47:0] RTC_savedtimeOut;
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wire RTC_inuse;
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cart_top cart (
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@@ -969,6 +970,7 @@ assign sd_buff_din = (sd_lba[7:0] <= ram_mask_file) ? bk_q : // normal saveram
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(sd_buff_addr == 8'd1) ? RTC_timestampOut[31:16] :
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(sd_buff_addr == 8'd2) ? RTC_savedtimeOut[15:0] :
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(sd_buff_addr == 8'd3) ? RTC_savedtimeOut[31:16] :
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(sd_buff_addr == 8'd4) ? RTC_savedtimeOut[47:32] :
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16'hFFFF;
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@@ -25,9 +25,11 @@ set_global_assignment -name VERILOG_FILE rtl/mappers/mbc1.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mbc2.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mbc3.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mbc5.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mbc6.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mbc7.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/mmm01.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/huc1.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/huc3.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/gb_camera.v
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set_global_assignment -name VERILOG_FILE rtl/mappers/tama.v
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set_global_assignment -name SDC_FILE Gameboy.sdc
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@@ -47,7 +47,7 @@ module cart_top (
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input [32:0] RTC_time,
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output [31:0] RTC_timestampOut,
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output [31:0] RTC_savedtimeOut,
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output [47:0] RTC_savedtimeOut,
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output RTC_inuse,
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input [63:0] SaveStateExt_Din,
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@@ -106,9 +106,11 @@ mappers mappers (
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.mbc3 ( mbc3 ),
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.mbc30( mbc30 ),
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.mbc5 ( mbc5 ),
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.mbc6 ( mbc6 ),
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.mbc7 ( mbc7 ),
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.mmm01 ( mmm01 ),
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.huc1 ( HuC1 ),
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.huc3 ( HuC3 ),
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.gb_camera ( gb_camera ),
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.tama ( tama ),
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@@ -196,11 +198,12 @@ wire mbc3 = (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type ==
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wire mbc30 = mbc3 && ( (cart_rom_size == 7) || (cart_ram_size == 5) );
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//wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23);
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wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30);
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wire mbc6 = (cart_mbc_type == 32);
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wire mbc7 = (cart_mbc_type == 34);
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wire gb_camera = (cart_mbc_type == 252);
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wire tama = (cart_mbc_type == 253);
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//wire HuC3 = (cart_mbc_type == 254);
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wire HuC3 = (cart_mbc_type == 254);
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wire HuC1 = (cart_mbc_type == 255);
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239
rtl/mappers/huc3.v
Normal file
239
rtl/mappers/huc3.v
Normal file
@@ -0,0 +1,239 @@
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module huc3 (
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input enable,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [63:0] savestate_data,
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inout [63:0] savestate_back_b,
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input [32:0] RTC_time,
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inout [31:0] RTC_timestampOut_b,
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inout [47:0] RTC_savedtimeOut_b,
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inout RTC_inuse_b,
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input bk_rtc_wr,
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input [16:0] bk_addr,
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input [15:0] bk_data,
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input has_ram,
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input [3:0] ram_mask,
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input [8:0] rom_mask,
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input [15:0] cart_addr,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [9:0] mbc_bank_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [9:0] mbc_bank;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [63:0] savestate_back;
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reg [31:0] RTC_timestampOut;
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reg [47:0] RTC_savedtimeOut;
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wire RTC_inuse = 1;
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assign mbc_bank_b = enable ? mbc_bank : 10'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 64'hZ;
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assign RTC_timestampOut_b = enable ? RTC_timestampOut : 32'hZ;
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assign RTC_savedtimeOut_b = enable ? RTC_savedtimeOut : 48'hZ;
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assign RTC_inuse_b = enable ? RTC_inuse : 1'hZ;
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// --------------------- CPU register interface ------------------
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reg [6:0] rom_bank_reg;
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reg [1:0] ram_bank_reg;
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reg [3:0] mode;
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assign savestate_back[ 6: 0] = rom_bank_reg;
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assign savestate_back[ 8: 7] = ram_bank_reg;
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assign savestate_back[12: 9] = mode;
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assign savestate_back[63:13] = 0;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg <= savestate_data[ 6: 0]; // 7'd0;
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ram_bank_reg <= savestate_data[ 8: 7]; // 2'd0;
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mode <= savestate_data[12: 9]; // 4'd0;
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end else if(~enable) begin
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rom_bank_reg <= 7'd0;
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ram_bank_reg <= 2'd0;
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mode <= 4'd0;
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end else if(ce_cpu) begin
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if (cart_wr) begin
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if (~cart_addr[15]) begin
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case(cart_addr[14:13])
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2'b00: mode <= cart_di[3:0];
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2'b01: rom_bank_reg <= cart_di[6:0]; // ROM bank register
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2'b10: ram_bank_reg <= cart_di[1:0]; // RAM bank register
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default: ;
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endcase
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end
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end
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end
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end
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reg [ 7:0] rtc_index;
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reg [ 3:0] rtc_flags;
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reg [ 3:0] rtc_out;
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reg [ 5:0] rtc_seconds;
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reg [24:0] rtc_subseconds;
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reg [11:0] rtc_minutes; // Minutes of the day 0-1439
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reg [15:0] rtc_days;
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reg [31:0] RTC_timestampSaved;
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reg [47:0] RTC_savedtimeIn;
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reg RTC_timestampNew_1;
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reg RTC_saveLoaded;
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wire rtc_subseconds_end = &rtc_subseconds;
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reg [31:0] diffSeconds;
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wire diffSeconds_fast_count = (diffSeconds > 0);
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always @(posedge clk_sys) begin
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rtc_subseconds <= rtc_subseconds + 1'b1;
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if (rtc_subseconds_end) begin
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RTC_timestampOut <= RTC_timestampOut + 1'd1;
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end else if (diffSeconds_fast_count) begin // fast counting loaded seconds
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diffSeconds <= diffSeconds - 1'd1;
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end
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if (rtc_subseconds_end | diffSeconds_fast_count) begin
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rtc_seconds <= rtc_seconds + 1'b1;
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if (rtc_seconds == 59) begin
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rtc_seconds <= 0;
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rtc_minutes <= rtc_minutes + 1'b1;
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if (rtc_minutes == 1439) begin
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rtc_minutes <= 0;
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rtc_days <= rtc_days + 1'b1;
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end
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end
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end
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RTC_saveLoaded <= 1'b0;
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if (bk_rtc_wr) begin // load data from savefile to intermediate register
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case (bk_addr[7:0])
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0: RTC_timestampSaved[15:0] <= bk_data;
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1: RTC_timestampSaved[31:16] <= bk_data;
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2: RTC_savedtimeIn[15:0] <= bk_data;
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3: RTC_savedtimeIn[31:16] <= bk_data;
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4: RTC_savedtimeIn[47:32] <= bk_data;
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5: RTC_saveLoaded <= 1'b1;
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endcase
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end
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if (RTC_saveLoaded) begin // load data from intermediate register to RTC registers
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if (RTC_timestampOut > RTC_timestampSaved) begin
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diffSeconds <= RTC_timestampOut - RTC_timestampSaved;
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end
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rtc_seconds <= RTC_savedtimeIn[ 5: 0];
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rtc_minutes <= RTC_savedtimeIn[17: 6];
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rtc_days <= RTC_savedtimeIn[33:18];
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end
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RTC_savedtimeOut[33: 0] <= { rtc_days, rtc_minutes, rtc_seconds };
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RTC_savedtimeOut[47:34] <= 0;
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if (~enable) begin
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rtc_index <= 8'd0;
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rtc_flags <= 4'd0;
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rtc_out <= 4'd0;
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end else if(ce_cpu & cart_wr & (cart_addr[15:13] == 3'b101)) begin // $A000-BFFF
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if (mode == 4'hB) begin
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if (cart_di[7:4] == 4'd1) begin
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case(rtc_index)
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8'h00: rtc_out <= rtc_minutes[ 3: 0];
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8'h01: rtc_out <= rtc_minutes[ 7: 4];
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8'h02: rtc_out <= rtc_minutes[11: 8];
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8'h03: rtc_out <= rtc_days[ 3: 0];
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8'h04: rtc_out <= rtc_days[ 7: 4];
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8'h05: rtc_out <= rtc_days[11: 8];
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8'h06: rtc_out <= rtc_days[15:12];
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endcase
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rtc_index <= rtc_index + 1'b1;
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end
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if (cart_di[7:4] == 4'd2 || cart_di[7:4] == 4'd3) begin
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case(rtc_index)
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8'h00: begin
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rtc_minutes[ 3: 0] <= cart_di[3:0];
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rtc_seconds <= 0;
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rtc_subseconds <= 0;
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end
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8'h01: rtc_minutes[ 7: 4] <= cart_di[3:0];
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8'h02: rtc_minutes[11: 8] <= cart_di[3:0];
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8'h03: rtc_days[ 3: 0] <= cart_di[3:0];
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8'h04: rtc_days[ 7: 4] <= cart_di[3:0];
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8'h05: rtc_days[11: 8] <= cart_di[3:0];
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8'h06: rtc_days[15:12] <= cart_di[3:0];
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endcase
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if (cart_di[4]) rtc_index <= rtc_index + 1'b1;
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end
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case(cart_di[7:4])
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4'd4: rtc_index[3:0] <= cart_di[3:0];
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4'd5: rtc_index[7:4] <= cart_di[3:0];
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4'd6: rtc_flags <= cart_di[3:0];
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default: ;
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endcase
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end
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end
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RTC_timestampNew_1 <= RTC_time[32]; // saving timestamp from HPS
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if (RTC_timestampNew_1 != RTC_time[32]) begin
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RTC_timestampOut <= RTC_time[31:0];
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end
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end
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wire [1:0] ram_bank = ram_bank_reg & ram_mask[1:0];
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// 0x0000-0x3FFF = Bank 0
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wire [6:0] rom_bank = (cart_addr[15:14] == 2'b00) ? 7'd0 : rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [6:0] rom_bank_m = rom_bank & rom_mask[6:0]; //64
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reg [7:0] cram_do_r;
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always @* begin
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cram_do_r = 8'hFF;
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case(mode)
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// 0: RAM read, A: RAM read/write. Robopon reads from RAM with mode 0.
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4'h0, 4'hA: if (has_ram) cram_do_r = cram_di; // RAM
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4'hC: cram_do_r[3:0] = (rtc_flags == 4'd2) ? 4'h1 : rtc_out; // RTC
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4'hD: cram_do_r[3:0] = 4'h1; //RTC
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4'hE: cram_do_r[0] = 1'b0; // Light detected
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default: ;
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endcase
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end
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assign mbc_bank = { 2'b00, rom_bank_m, cart_addr[13] }; // 16k ROM Bank 0-127
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assign ram_enabled = (mode == 4'hA) & has_ram; // RAM write enable
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assign cram_do = cram_do_r;
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assign cram_addr = { 2'b00, ram_bank, cart_addr[12:0] };
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assign has_battery = has_ram;
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endmodule
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@@ -12,9 +12,11 @@ module mappers(
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input mbc3,
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input mbc30,
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input mbc5,
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input mbc6,
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input mbc7,
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input mmm01,
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input huc1,
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input huc3,
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input gb_camera,
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input tama,
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@@ -22,7 +24,7 @@ module mappers(
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input [32:0] RTC_time,
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output [31:0] RTC_timestampOut,
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output [31:0] RTC_savedtimeOut,
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output [47:0] RTC_savedtimeOut,
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output RTC_inuse,
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input bk_wr,
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@@ -69,10 +71,13 @@ tri0 [15:0] savestate_back_b;
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tri0 [63:0] savestate_back2_b;
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tri0 [7:0] cram_wr_do_b;
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tri0 cram_wr_b;
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tri0 [31:0] RTC_timestampOut_b;
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tri0 [47:0] RTC_savedtimeOut_b;
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tri0 RTC_inuse_b;
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wire ce = speed ? ce_cpu2x : ce_cpu;
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wire no_mapper = ~(mbc1 | mbc2 | mbc3 | mbc5 | mbc7 | mmm01 | huc1 | gb_camera | tama);
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wire no_mapper = ~(mbc1 | mbc2 | mbc3 | mbc5 | mbc6 | mbc7 | mmm01 | huc1 | huc3 | gb_camera | tama);
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mbc1 map_mbc1 (
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.enable ( mbc1 ),
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@@ -145,9 +150,9 @@ mbc3 map_mbc3 (
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.savestate_back_b ( savestate_back_b ),
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.RTC_time ( RTC_time ),
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.RTC_timestampOut ( RTC_timestampOut ),
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.RTC_savedtimeOut ( RTC_savedtimeOut ),
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.RTC_inuse ( RTC_inuse ),
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.RTC_timestampOut_b( RTC_timestampOut_b ),
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.RTC_savedtimeOut_b( RTC_savedtimeOut_b ),
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.RTC_inuse_b ( RTC_inuse_b ),
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.bk_wr ( bk_wr ),
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.bk_rtc_wr ( bk_rtc_wr ),
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@@ -203,6 +208,35 @@ mbc5 map_mbc5 (
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.has_battery_b ( has_battery_b )
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);
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mbc6 map_mbc6 (
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.enable ( mbc6 ),
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.clk_sys ( clk_sys ),
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.ce_cpu ( ce ),
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.savestate_load ( savestate_load ),
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.savestate_data ( savestate_data2 ),
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.savestate_back_b ( savestate_back2_b ),
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.has_ram ( has_ram ),
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.ram_mask ( ram_mask ),
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.rom_mask ( rom_mask ),
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.cart_addr ( cart_addr ),
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.cart_mbc_type ( cart_mbc_type ),
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.cart_wr ( cart_wr ),
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.cart_di ( cart_di ),
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.cram_di ( cram_di ),
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.cram_do_b ( cram_do_b ),
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.cram_addr_b ( cram_addr_b ),
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.mbc_bank_b ( mbc_bank_b ),
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.ram_enabled_b ( ram_enabled_b ),
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.has_battery_b ( has_battery_b )
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);
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mbc7 map_mbc7 (
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.enable ( mbc7 ),
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@@ -299,6 +333,45 @@ huc1 map_huc1 (
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.has_battery_b ( has_battery_b )
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);
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huc3 map_huc3 (
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.enable ( huc3 ),
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.clk_sys ( clk_sys ),
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.ce_cpu ( ce ),
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.savestate_load ( savestate_load ),
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.savestate_data ( savestate_data2 ),
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.savestate_back_b ( savestate_back2_b ),
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.RTC_time ( RTC_time ),
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.RTC_timestampOut_b( RTC_timestampOut_b ),
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.RTC_savedtimeOut_b( RTC_savedtimeOut_b ),
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.RTC_inuse_b ( RTC_inuse_b ),
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.bk_rtc_wr ( bk_rtc_wr ),
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.bk_addr ( bk_addr ),
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.bk_data ( bk_data ),
|
||||
|
||||
.has_ram ( has_ram ),
|
||||
.ram_mask ( ram_mask ),
|
||||
.rom_mask ( rom_mask ),
|
||||
|
||||
.cart_addr ( cart_addr ),
|
||||
.cart_mbc_type ( cart_mbc_type ),
|
||||
|
||||
.cart_wr ( cart_wr ),
|
||||
.cart_di ( cart_di ),
|
||||
|
||||
.cram_di ( cram_di ),
|
||||
.cram_do_b ( cram_do_b ),
|
||||
.cram_addr_b ( cram_addr_b ),
|
||||
|
||||
.mbc_bank_b ( mbc_bank_b ),
|
||||
.ram_enabled_b ( ram_enabled_b ),
|
||||
.has_battery_b ( has_battery_b )
|
||||
);
|
||||
|
||||
|
||||
gb_camera map_gb_camera (
|
||||
.enable ( gb_camera ),
|
||||
|
||||
@@ -362,8 +435,11 @@ tama map_tama (
|
||||
.has_battery_b ( has_battery_b )
|
||||
);
|
||||
|
||||
assign { cram_do, ram_enabled, savestate_back, savestate_back2 } = { cram_do_b, ram_enabled_b, savestate_back_b, savestate_back2_b };
|
||||
assign { cram_do, ram_enabled } = { cram_do_b, ram_enabled_b };
|
||||
assign { savestate_back, savestate_back2 } = { savestate_back_b, savestate_back2_b };
|
||||
assign { RTC_timestampOut, RTC_savedtimeOut, RTC_inuse } = { RTC_timestampOut_b, RTC_savedtimeOut_b, RTC_inuse_b };
|
||||
assign { cram_wr_do, cram_wr } = { cram_wr_do_b, cram_wr_b };
|
||||
|
||||
assign mbc_bank = no_mapper ? {8'd0, cart_addr[14:13]} : mbc_bank_b;
|
||||
assign cram_addr = no_mapper ? {4'd0, cart_addr[12:0]} : cram_addr_b;
|
||||
assign has_battery = no_mapper ? (cart_mbc_type == 8'h09) : has_battery_b;
|
||||
|
||||
@@ -11,9 +11,9 @@ module mbc3 (
|
||||
inout [15:0] savestate_back_b,
|
||||
|
||||
input [32:0] RTC_time,
|
||||
output reg [31:0] RTC_timestampOut,
|
||||
output reg [31:0] RTC_savedtimeOut,
|
||||
output reg RTC_inuse,
|
||||
inout [31:0] RTC_timestampOut_b,
|
||||
inout [47:0] RTC_savedtimeOut_b,
|
||||
inout RTC_inuse_b,
|
||||
|
||||
input bk_wr,
|
||||
input bk_rtc_wr,
|
||||
@@ -47,12 +47,19 @@ wire ram_enabled;
|
||||
wire has_battery;
|
||||
wire [15:0] savestate_back;
|
||||
|
||||
assign mbc_bank_b = enable ? mbc_bank : 10'hZ;
|
||||
assign cram_do_b = enable ? cram_do : 8'hZ;
|
||||
assign cram_addr_b = enable ? cram_addr : 17'hZ;
|
||||
assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
|
||||
assign has_battery_b = enable ? has_battery : 1'hZ;
|
||||
assign savestate_back_b = enable ? savestate_back : 16'hZ;
|
||||
reg [31:0] RTC_timestampOut;
|
||||
reg [47:0] RTC_savedtimeOut;
|
||||
reg RTC_inuse;
|
||||
|
||||
assign mbc_bank_b = enable ? mbc_bank : 10'hZ;
|
||||
assign cram_do_b = enable ? cram_do : 8'hZ;
|
||||
assign cram_addr_b = enable ? cram_addr : 17'hZ;
|
||||
assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
|
||||
assign has_battery_b = enable ? has_battery : 1'hZ;
|
||||
assign savestate_back_b = enable ? savestate_back : 16'hZ;
|
||||
assign RTC_timestampOut_b = enable ? RTC_timestampOut : 32'hZ;
|
||||
assign RTC_savedtimeOut_b = enable ? RTC_savedtimeOut : 48'hZ;
|
||||
assign RTC_inuse_b = enable ? RTC_inuse : 1'hZ;
|
||||
|
||||
// --------------------- CPU register interface ------------------
|
||||
|
||||
@@ -165,9 +172,9 @@ always @(posedge clk_sys) begin
|
||||
RTC_inuse <= 1'b0;
|
||||
rtc_latch <= 1'b0;
|
||||
end else begin
|
||||
|
||||
RTC_savedtimeOut[47:29] <= 0;
|
||||
if (rtc_change == 1'b0) begin // when RTC hasn't changed recently, update the register which will be written after savegame
|
||||
RTC_savedtimeOut <= {3'd0, rtc_halt, rtc_overflow, rtc_days, rtc_hours, rtc_minutes, rtc_seconds};
|
||||
RTC_savedtimeOut[28:0] <= {rtc_halt, rtc_overflow, rtc_days, rtc_hours, rtc_minutes, rtc_seconds};
|
||||
end
|
||||
|
||||
rtc_change <= 1'b0;
|
||||
|
||||
128
rtl/mappers/mbc6.v
Normal file
128
rtl/mappers/mbc6.v
Normal file
@@ -0,0 +1,128 @@
|
||||
module mbc6 (
|
||||
input enable,
|
||||
|
||||
input clk_sys,
|
||||
input ce_cpu,
|
||||
|
||||
input savestate_load,
|
||||
input [63:0] savestate_data,
|
||||
inout [63:0] savestate_back_b,
|
||||
|
||||
input has_ram,
|
||||
input [1:0] ram_mask,
|
||||
input [5:0] rom_mask,
|
||||
|
||||
input [15:0] cart_addr,
|
||||
input [7:0] cart_mbc_type,
|
||||
|
||||
input cart_wr,
|
||||
input [7:0] cart_di,
|
||||
|
||||
input [7:0] cram_di,
|
||||
inout [7:0] cram_do_b,
|
||||
inout [16:0] cram_addr_b,
|
||||
|
||||
inout [9:0] mbc_bank_b,
|
||||
inout ram_enabled_b,
|
||||
inout has_battery_b
|
||||
);
|
||||
|
||||
wire [9:0] mbc_bank;
|
||||
wire [7:0] cram_do;
|
||||
wire [16:0] cram_addr;
|
||||
wire ram_enabled;
|
||||
wire has_battery;
|
||||
wire [63:0] savestate_back;
|
||||
|
||||
assign mbc_bank_b = enable ? mbc_bank : 10'hZ;
|
||||
assign cram_do_b = enable ? cram_do : 8'hZ;
|
||||
assign cram_addr_b = enable ? cram_addr : 17'hZ;
|
||||
assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
|
||||
assign has_battery_b = enable ? has_battery : 1'hZ;
|
||||
assign savestate_back_b = enable ? savestate_back : 64'hZ;
|
||||
|
||||
// --------------------- CPU register interface ------------------
|
||||
|
||||
reg [6:0] rom_bank_reg_a;
|
||||
reg [6:0] rom_bank_reg_b;
|
||||
reg [2:0] ram_bank_reg_a;
|
||||
reg [2:0] ram_bank_reg_b;
|
||||
reg ram_enable;
|
||||
|
||||
assign savestate_back[ 6: 0] = rom_bank_reg_a;
|
||||
assign savestate_back[13: 7] = rom_bank_reg_b;
|
||||
assign savestate_back[16:14] = ram_bank_reg_a;
|
||||
assign savestate_back[19:17] = ram_bank_reg_b;
|
||||
assign savestate_back[ 20] = ram_enable;
|
||||
assign savestate_back[63:21] = 0;
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(savestate_load & enable) begin
|
||||
rom_bank_reg_a <= savestate_data[ 6: 0]; // 7'd0;
|
||||
rom_bank_reg_b <= savestate_data[13: 7]; // 7'd0;
|
||||
ram_bank_reg_a <= savestate_data[16:14]; // 3'd0;
|
||||
ram_bank_reg_b <= savestate_data[19:17]; // 3'd0;
|
||||
ram_enable <= savestate_data[ 20]; // 1'b0;
|
||||
end else if(~enable) begin
|
||||
rom_bank_reg_a <= 7'd0;
|
||||
rom_bank_reg_b <= 7'd0;
|
||||
ram_bank_reg_a <= 3'd0;
|
||||
ram_bank_reg_b <= 3'd0;
|
||||
ram_enable <= 1'b0;
|
||||
end else if(ce_cpu) begin
|
||||
if (cart_wr) begin
|
||||
if (!cart_addr[15:13]) begin // $0000-1FFF
|
||||
case(cart_addr[12:10])
|
||||
3'd0: ram_enable <= (cart_di[3:0] == 4'hA); //RAM enable/disable
|
||||
3'd1: ram_bank_reg_a <= cart_di[2:0]; // 4KB RAM bank A ($A000-AFFF)
|
||||
3'd2: ram_bank_reg_b <= cart_di[2:0]; // 4KB RAM bank B ($B000-BFFF)
|
||||
3'd3: ; // Flash enable
|
||||
3'd4: ; // Flash write enable
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
if (cart_addr[15:13] == 3'b001) begin // $2000-3FFF
|
||||
case(cart_addr[12:11])
|
||||
2'd0: rom_bank_reg_a <= cart_di[6:0]; // 8KB ROM bank A ($4000-5FFF)
|
||||
2'd1: ; //rom_flash_sel_a <= (cart_di[3:0] == 4'h8); // ROM/Flash A select
|
||||
2'd2: rom_bank_reg_b <= cart_di[6:0]; // 8KB ROM bank B ($6000-7FFF)
|
||||
2'd3: ; //rom_flash_sel_b <= (cart_di[3:0] == 4'h8); // ROM/Flash B select
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [6:0] rom_bank;
|
||||
always @* begin
|
||||
if (~cart_addr[14]) begin // $0000-3FFF
|
||||
rom_bank = { 6'd0, cart_addr[13] };
|
||||
end else if (~cart_addr[13]) begin // $4000-5FFF
|
||||
rom_bank = rom_bank_reg_a;
|
||||
end else begin // $6000-7FFF
|
||||
rom_bank = rom_bank_reg_b;
|
||||
end
|
||||
end
|
||||
|
||||
reg [2:0] ram_bank;
|
||||
always @* begin
|
||||
if (~cart_addr[12]) begin // $A000-AFFF
|
||||
ram_bank = ram_bank_reg_a;
|
||||
end else begin // $B000-BFFF
|
||||
ram_bank = ram_bank_reg_b;
|
||||
end
|
||||
end
|
||||
|
||||
// mask address lines to enable proper mirroring
|
||||
wire [6:0] rom_bank_m = rom_bank & { rom_mask[5:0], 1'b1 }; // 64x16KB Mask
|
||||
wire [2:0] ram_bank_m = ram_bank & { ram_mask[1:0], 1'b1 }; // 4x8KB Mask
|
||||
|
||||
assign mbc_bank = { 3'd0, rom_bank_m }; // 8KB ROM Bank 0-127
|
||||
|
||||
assign cram_do = ram_enabled ? cram_di : 8'hFF;
|
||||
assign cram_addr = { 2'd0, ram_bank_m, cart_addr[11:0] }; // 4KB RAM Bank 0-7
|
||||
|
||||
assign has_battery = has_ram;
|
||||
assign ram_enabled = ram_enable & has_ram;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user