mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
synced 2026-05-24 03:03:25 +00:00
Update sys.
This commit is contained in:
sorgelig
@@ -204,7 +204,7 @@ assign DDRAM_DIN = {ram_data,ram_data};
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assign DDRAM_WE = ram_wr;
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assign DDRAM_RD = 0;
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assign FB_EN = ~no_rotate;
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assign FB_EN = fb_en[2];
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assign FB_FORMAT = 5'b00110;
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assign FB_BASE = {MEM_BASE,o_fb,23'd0};
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assign FB_WIDTH = vsz;
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@@ -236,6 +236,11 @@ always @(posedge CLK_VIDEO) begin
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end
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end
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initial begin
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fb_en = 0;
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end
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reg [2:0] fb_en = 0;
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reg [11:0] hsz = 320, vsz = 240;
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reg [11:0] bwidth;
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reg [22:0] bufsize;
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@@ -257,6 +262,7 @@ always @(posedge CLK_VIDEO) begin
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vsz <= vcnt;
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bwidth <= vcnt + 2'd3;
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vcnt <= 0;
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fb_en <= {fb_en[1:0], ~no_rotate};
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end
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if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
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end
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17
sys/hps_io.v
17
sys/hps_io.v
@@ -126,7 +126,8 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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output reg [32:0] TIMESTAMP,
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// UART flags
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input [15:0] uart_mode,
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output reg [7:0] uart_mode,
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output reg [31:0] uart_speed,
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// ps2 keyboard emulation
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output ps2_kbd_clk_out,
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@@ -248,6 +249,8 @@ always@(posedge clk_sys) begin : uio_block
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reg old_status_set = 0;
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reg old_info = 0;
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reg [7:0] info_n = 0;
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reg [15:0] tmp1;
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reg [7:0] tmp2;
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old_status_set <= status_set;
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if(~old_status_set & status_set) begin
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@@ -453,9 +456,6 @@ always@(posedge clk_sys) begin : uio_block
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//RTC
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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//UART flags
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'h28: io_dout <= uart_mode;
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//status set
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'h29: if(!byte_cnt[MAX_W:3]) begin
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case(byte_cnt[2:0])
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@@ -479,6 +479,15 @@ always@(posedge clk_sys) begin : uio_block
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{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
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if (byte_cnt[1:0] == 3) byte_cnt <= 1;
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end
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// UART
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'h3b: if(!byte_cnt[MAX_W:2]) begin
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case(byte_cnt[1:0])
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1: tmp2 <= io_din[7:0];
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2: tmp1 <= io_din;
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3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2};
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endcase
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end
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endcase
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end
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end
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283
sys/mt32pi.sv
Normal file
283
sys/mt32pi.sv
Normal file
@@ -0,0 +1,283 @@
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//
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// Communication module to MT32-pi (external MIDI emulator on RPi)
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// (C) 2020 Sorgelig, Kitrinx
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//
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// https://github.com/dwhinham/mt32-pi
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//
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module mt32pi
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(
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input CLK_AUDIO,
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input CLK_VIDEO,
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input CE_PIXEL,
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input VGA_VS,
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input VGA_DE,
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input reset,
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input midi_tx,
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output midi_rx,
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output reg [15:0] mt32_i2s_r,
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output reg [15:0] mt32_i2s_l,
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output reg mt32_available,
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input mt32_mode_req,
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input [1:0] mt32_rom_req,
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input [7:0] mt32_sf_req,
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output reg [7:0] mt32_mode,
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output reg [7:0] mt32_rom,
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output reg [7:0] mt32_sf,
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output reg mt32_newmode,
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output reg mt32_lcd_en,
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output reg mt32_lcd_pix,
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output reg mt32_lcd_update
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);
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//
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// Pin | USB Name | Signal
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// ----+----------+--------------
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// 0 | D+ | I/O I2C_SDA / RX (midi in)
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// 1 | D- | O TX (midi out)
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// 2 | TX- | I I2S_WS (1 == right)
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// 3 | GND_d | I I2C_SCL
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// 4 | RX+ | I I2S_BCLK
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// 5 | RX- | I I2S_DAT
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// 6 | TX+ | - none
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//
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assign USER_OUT[0] = sda_out;
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assign USER_OUT[1] = midi_tx;
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assign USER_OUT[6:2] = '1;
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//
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// crossed/straight cable selection
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//
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generate
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genvar i;
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for(i = 0; i<2; i++) begin : clk_rate
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wire clk_in = i ? USER_IN[6] : USER_IN[4];
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reg [4:0] cnt;
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always @(posedge CLK_AUDIO) begin : clkr
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reg clk_sr, clk, old_clk;
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reg [4:0] cnt_tmp;
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clk_sr <= clk_in;
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if (clk_sr == clk_in) clk <= clk_sr;
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if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1;
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else cnt <= '1;
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old_clk <= clk;
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if(~old_clk & clk) begin
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cnt <= cnt_tmp;
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cnt_tmp <= 0;
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end
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end
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end
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reg crossed;
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always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt);
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endgenerate
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wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5];
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wire i2s_data = crossed ? USER_IN[5] : USER_IN[2];
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wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6];
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assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4];
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//
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// i2s receiver
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//
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always @(posedge CLK_AUDIO) begin : i2s_proc
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reg [15:0] i2s_buf = 0;
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reg [4:0] i2s_cnt = 0;
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reg clk_sr;
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reg i2s_clk = 0;
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reg old_clk, old_ws;
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reg i2s_next = 0;
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// Debounce clock
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clk_sr <= i2s_bclk;
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if (clk_sr == i2s_bclk) i2s_clk <= clk_sr;
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// Latch data and ws on rising edge
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old_clk <= i2s_clk;
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if (i2s_clk && ~old_clk) begin
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if (~i2s_cnt[4]) begin
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i2s_cnt <= i2s_cnt + 1'd1;
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i2s_buf[~i2s_cnt[3:0]] <= i2s_data;
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end
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// Word Select will change 1 clock before the new word starts
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old_ws <= i2s_ws;
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if (old_ws != i2s_ws) i2s_next <= 1;
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end
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if (i2s_next) begin
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i2s_next <= 0;
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i2s_cnt <= 0;
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i2s_buf <= 0;
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if (i2s_ws) mt32_i2s_l <= i2s_buf;
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else mt32_i2s_r <= i2s_buf;
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end
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if (reset) begin
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i2s_buf <= 0;
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mt32_i2s_l <= 0;
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mt32_i2s_r <= 0;
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end
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end
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//
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// i2c slave
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//
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reg sda_out;
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reg [7:0] lcd_data[1024];
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reg lcd_sz;
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reg reset_r = 0;
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wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1;
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wire [7:0] rom_req = {6'd0, mt32_rom_req};
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always @(posedge CLK_AUDIO) begin : i2c_slave
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reg sda_sr, scl_sr;
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reg old_sda, old_scl;
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reg sda, scl;
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reg [7:0] tmp;
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reg [3:0] cnt = 0;
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reg [10:0] bcnt = 0;
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reg ack;
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reg i2c_rw;
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reg disp, dispdata;
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reg [2:0] div;
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reg old_reset;
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old_reset <= reset;
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if(old_reset & ~reset) sda_out <= 1;
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div <= div + 1'd1;
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if(!div) begin
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sda_sr <= USER_IN[0];
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if(sda_sr == USER_IN[0]) sda <= sda_sr;
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old_sda <= sda;
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scl_sr <= USER_IN[3];
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if(scl_sr == USER_IN[3]) scl <= scl_sr;
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old_scl <= scl;
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//start
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if(old_scl & scl & old_sda & ~sda) begin
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cnt <= 9;
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bcnt <= 0;
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ack <= 0;
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i2c_rw <= 0;
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disp <= 0;
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dispdata <= 0;
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end
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//stop
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if(old_scl & scl & ~old_sda & sda) begin
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cnt <= 0;
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if(dispdata) begin
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lcd_sz <= ~bcnt[9];
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mt32_lcd_update <= ~mt32_lcd_update;
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end
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end
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//data latch
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if(~old_scl && scl && cnt) begin
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tmp <= {tmp[6:0], sda};
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cnt <= cnt - 1'd1;
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end
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if(!cnt) sda_out <= 1;
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//data set
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if(old_scl && ~scl) begin
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sda_out <= 1;
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if(cnt == 1) begin
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if(!bcnt) begin
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if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin
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disp <= (tmp[7:1] == 'h3c);
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sda_out <= 0;
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mt32_available <= 1;
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ack <= 1;
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i2c_rw <= tmp[0];
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bcnt <= bcnt + 1'd1;
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cnt <= 10;
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end
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else begin
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// wrong address, stop
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cnt <= 0;
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end
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end
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else if(ack) begin
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if(~i2c_rw) begin
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if(disp) begin
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if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01);
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else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp;
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end
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else begin
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if(bcnt == 1) mt32_mode <= tmp;
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if(bcnt == 2) mt32_rom <= tmp;
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if(bcnt == 3) mt32_sf <= tmp;
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if(bcnt == 3) mt32_newmode <= ~mt32_newmode;
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end
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end
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if(~&bcnt) bcnt <= bcnt + 1'd1;
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sda_out <= 0;
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cnt <= 10;
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end
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end
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else if(i2c_rw && ack && cnt && ~disp) begin
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if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2];
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if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2];
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if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2];
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if(bcnt == 3) reset_r <= 0;
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end
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end
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end
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if(reset) begin
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reset_r <= 1;
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mt32_available <= 0;
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end
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end
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always @(posedge CLK_VIDEO) begin
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reg old_de, old_vs;
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reg [7:0] hcnt;
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reg [6:0] vcnt;
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reg [7:0] sh;
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if(CE_PIXEL) begin
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old_de <= VGA_DE;
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old_vs <= VGA_VS;
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if(~&hcnt) hcnt <= hcnt + 1'd1;
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sh <= (sh << 1) | (~old_de & VGA_DE);
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if(sh[7]) hcnt <= 0;
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if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1;
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if(~old_vs & VGA_VS) vcnt <= 0;
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mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]);
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mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]];
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end
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end
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endmodule
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19
sys/spdif.v
19
sys/spdif.v
@@ -67,6 +67,8 @@ reg spdif_out_q;
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reg [5:0] parity_count_q;
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reg channel_status_bit;
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//-----------------------------------------------------------------
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// Subframe Counter
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//-----------------------------------------------------------------
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@@ -142,7 +144,7 @@ assign subframe_w[28] = 1'b0; // Valid
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assign subframe_w[29] = 1'b0;
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// Timeslots 30 = Channel status bit
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assign subframe_w[30] = 1'b0;
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assign subframe_w[30] = channel_status_bit ; //was constant 1'b0 enabling copy-bit;
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// Timeslots 31 = Even Parity bit (31:4)
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assign subframe_w[31] = 1'b0;
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@@ -150,9 +152,9 @@ assign subframe_w[31] = 1'b0;
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//-----------------------------------------------------------------
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// Preamble
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//-----------------------------------------------------------------
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localparam PREAMBLE_Z = 8'b00010111;
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localparam PREAMBLE_Y = 8'b00100111;
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localparam PREAMBLE_X = 8'b01000111;
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localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block
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localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data
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localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block
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reg [7:0] preamble_r;
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@@ -168,6 +170,15 @@ begin
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// Left Channel (but not start of block)?
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else
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preamble_r = PREAMBLE_X; // X(M)
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if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted
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channel_status_bit = 1'b1;
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else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media
|
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channel_status_bit = 1'b1;
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else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r)
|
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channel_status_bit = 1'b1;
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else
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channel_status_bit = 1'b0; // everything else defaults to 0
|
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end
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||||
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||||
always @ (posedge rst_i or posedge clk_i )
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||||
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||||
@@ -20,6 +20,7 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a
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||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
|
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
|
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
|
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
|
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
|
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
|
||||
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@@ -21,29 +21,30 @@ set_clock_groups -exclusive \
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||||
|
||||
set_false_path -from [get_ports {KEY*}]
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||||
set_false_path -from [get_ports {BTN_*}]
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
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set_false_path -to [get_ports {AUDIO_SPDIF}]
|
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set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
set_false_path -to {cfg[*]}
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
set_false_path -to {cfg[*]}
|
||||
set_false_path -from {cfg[*]}
|
||||
set_false_path -from {VSET[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {width[*] height[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {width[*] height[*]}
|
||||
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||
set_false_path -to {*_osd|v_cnt*}
|
||||
set_false_path -to {*_osd|v_osd_start*}
|
||||
set_false_path -to {*_osd|v_info_start*}
|
||||
set_false_path -to {*_osd|h_osd_start*}
|
||||
|
||||
set_false_path -to {*_osd|v_cnt*}
|
||||
set_false_path -to {*_osd|v_osd_start*}
|
||||
set_false_path -to {*_osd|v_info_start*}
|
||||
set_false_path -to {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|v_osd_start*}
|
||||
set_false_path -from {*_osd|v_info_start*}
|
||||
set_false_path -from {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|rot*}
|
||||
set_false_path -from {*_osd|dsp_width*}
|
||||
set_false_path -to {*_osd|half}
|
||||
set_false_path -to {*_osd|half}
|
||||
|
||||
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
@@ -51,7 +52,8 @@ set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*]
|
||||
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
|
||||
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {aflt_* acx* acy* areset*}
|
||||
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
||||
set_false_path -from {vs_line*}
|
||||
|
||||
set_false_path -from {ascal|o_ihsize*}
|
||||
set_false_path -from {ascal|o_ivsize*}
|
||||
|
||||
@@ -1210,21 +1210,29 @@ wire vga_cs_osd;
|
||||
csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
|
||||
`ifndef DUAL_SDRAM
|
||||
wire [23:0] vga_o;
|
||||
vga_out vga_out
|
||||
(
|
||||
.ypbpr_full(0),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.dout(vga_o),
|
||||
.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
|
||||
);
|
||||
|
||||
wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd;
|
||||
wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd;
|
||||
wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd;
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1;
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1;
|
||||
wire [23:0] vga_o;
|
||||
wire vga_hs, vga_vs, vga_cs;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_full(0),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(hs1),
|
||||
.vsync(vs1),
|
||||
.csync(cs1),
|
||||
.dout(vga_o),
|
||||
.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd),
|
||||
.hsync_o(vga_hs),
|
||||
.vsync_o(vga_vs),
|
||||
.csync_o(vga_cs)
|
||||
);
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vga_vs;
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~vga_cs : ~vga_hs;
|
||||
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[23:18];
|
||||
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[15:10];
|
||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
|
||||
|
||||
@@ -1,11 +1,20 @@
|
||||
|
||||
module vga_out
|
||||
(
|
||||
input clk,
|
||||
input ypbpr_full,
|
||||
input ypbpr_en,
|
||||
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
@@ -49,17 +58,32 @@ wire [5:0] blue = din[7:2];
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
wire [7:0] y = ( y_2[17:8] < 16) ? 8'd16 : ( y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
|
||||
wire [7:0] pb = (pb_2[17:8] < 16) ? 8'd16 : (pb_2[17:8] > 240) ? 8'd240 : pb_2[15:8];
|
||||
wire [7:0] pr = (pr_2[17:8] < 16) ? 8'd16 : (pr_2[17:8] > 240) ? 8'd240 : pr_2[15:8];
|
||||
|
||||
assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
|
||||
assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8];
|
||||
assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
|
||||
reg [7:0] y_3, pb_3, pr_3;
|
||||
reg [23:0] din2, din3;
|
||||
reg hsync2, vsync2, csync2;
|
||||
always @(posedge clk) begin
|
||||
y_2 <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
pb_2 <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
pr_2 <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
y_3 <= {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00};
|
||||
pb_3 <= {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00};
|
||||
pr_3 <= {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00};
|
||||
|
||||
hsync_o <= hsync2; hsync2 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync;
|
||||
|
||||
din2 <= din;
|
||||
din3 <= din2;
|
||||
end
|
||||
|
||||
assign dout = ypbpr_en ? {pr_3, y_3, pb_3} : din3;
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user