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T80: fixed rotate, cpl, scf and ccf opcodes, finally passed blargg's cpu_instr tests

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This commit is contained in:
Bruno Duarte Gouveia
2019-01-07 00:53:26 +00:00
parent 8a7617db46
commit 6edc3bfdce
4 changed files with 59 additions and 24 deletions
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74
t80/T80.vhd
View File

@@ -213,6 +213,7 @@ architecture rtl of T80 is
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal Rot_Akku : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
@@ -283,6 +284,7 @@ begin
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
Rot_Akku => Rot_Akku,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
@@ -336,6 +338,7 @@ begin
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
Rot_Akku => Rot_Akku,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
@@ -560,31 +563,54 @@ begin
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if Mode = 3 then
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_H) <= '1';
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
else
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then

4
t80/T80_ALU.vhd
View File

@@ -85,6 +85,7 @@ entity T80_ALU is
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
Rot_Akku : in std_logic;
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
@@ -392,6 +393,9 @@ begin
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
if Mode = 3 and Rot_Akku = '1' then
F_Out(Flag_Z) <= '0';
end if;
when others =>
null;
end case;

3
t80/T80_MCode.vhd
View File

@@ -112,6 +112,7 @@ entity T80_MCode is
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
Rot_Akku : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -213,6 +214,7 @@ begin
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
Rot_Akku <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
@@ -956,6 +958,7 @@ begin
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Rot_Akku <= '1';
Save_ALU <= '1';
-- JUMP GROUP

2
t80/T80_Pack.vhd
View File

@@ -161,6 +161,7 @@ package T80_Pack is
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
Rot_Akku : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -217,6 +218,7 @@ package T80_Pack is
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
Rot_Akku : in std_logic;
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);