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initial SNAC support

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blue212
2019-12-03 16:12:01 -05:00
committed by sorgelig
parent 9ab28a8450
commit 67dc9c0dae
4 changed files with 1085 additions and 948 deletions
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1814
Gameboy.sv
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File diff suppressed because it is too large Load Diff

37
files.qip
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@@ -1,18 +1,19 @@
set_global_assignment -name QIP_FILE t80/T80.qip
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VHDL_FILE spram.vhd
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name VHDL_FILE boot_rom.vhd
set_global_assignment -name SYSTEMVERILOG_FILE cheatcodes.sv
set_global_assignment -name VERILOG_FILE video.v
set_global_assignment -name VERILOG_FILE timer.v
set_global_assignment -name VERILOG_FILE sprite_sort.v
set_global_assignment -name VERILOG_FILE sprites.v
set_global_assignment -name VERILOG_FILE sprite.v
set_global_assignment -name VERILOG_FILE lcd.v
set_global_assignment -name VHDL_FILE gbc_snd.vhd
set_global_assignment -name VERILOG_FILE gb.v
set_global_assignment -name VERILOG_FILE hdma.v
set_global_assignment -name SDC_FILE Gameboy.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Gameboy.sv
set_global_assignment -name VERILOG_FILE sgb.v
set_global_assignment -name QIP_FILE t80/T80.qip
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VHDL_FILE spram.vhd
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name VHDL_FILE boot_rom.vhd
set_global_assignment -name SYSTEMVERILOG_FILE cheatcodes.sv
set_global_assignment -name VERILOG_FILE video.v
set_global_assignment -name VERILOG_FILE timer.v
set_global_assignment -name VERILOG_FILE sprite_sort.v
set_global_assignment -name VERILOG_FILE sprites.v
set_global_assignment -name VERILOG_FILE sprite.v
set_global_assignment -name VERILOG_FILE lcd.v
set_global_assignment -name VHDL_FILE gbc_snd.vhd
set_global_assignment -name VERILOG_FILE gb.v
set_global_assignment -name VERILOG_FILE hdma.v
set_global_assignment -name VERILOG_FILE link.v
set_global_assignment -name SDC_FILE Gameboy.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Gameboy.sv
set_global_assignment -name VERILOG_FILE sgb.v

74
gb.v
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@@ -61,7 +61,14 @@ module gb (
input gg_reset,
input gg_en,
input [128:0] gg_code,
output gg_available
output gg_available,
//serial port
output sc_int_clock2,
input serial_clk_in,
output serial_clk_out,
input serial_data_in,
output serial_data_out
);
// include cpu
@@ -121,7 +128,7 @@ wire [7:0] cpu_di =
isGBC&&sel_hdma?{hdma_do}: //hdma GBC
isGBC&&sel_key1?{cpu_speed,6'h3f,prepare_switch}: //key1 cpu speed register(GBC)
sel_joy?joy_do: // joystick register
sel_sb?8'hFF: // serial transfer data register
sel_sb?sb: // serial transfer data register
sel_sc?sc_r: // serial transfer control register
sel_timer?timer_do: // timer registers
sel_video_reg?video_do: // video registers
@@ -240,46 +247,39 @@ gbc_snd audio (
);
// --------------------------------------------------------------------
// -----------------------serial port(dummy)---------------------------
// -----------------------serial port()--------------------------------
// --------------------------------------------------------------------
reg [3:0] serial_counter;
reg sc_start,sc_shiftclock;
wire serial_irq;
wire [7:0] sb;
wire sc_start;
wire sc_shiftclock;
reg serial_irq;
reg [8:0] serial_clk_div; //8192Hz
assign sc_int_clock2 = sc_shiftclock;
always @(posedge clk_cpu) begin
serial_irq <= 1'b0;
if(reset) begin
sc_start <= 1'b0;
sc_shiftclock <= 1'b0;
end else if (sel_sc && !cpu_wr_n) begin //cpu write
sc_start <= cpu_do[7];
sc_shiftclock <= cpu_do[0];
if (cpu_do[7]) begin //enable transfer
serial_clk_div <= 9'h1FF;
serial_counter <= 4'd8;
end
end else if (sc_start && sc_shiftclock) begin // serial transfer and serial clock enabled
serial_clk_div <= serial_clk_div - 9'd1;
if (serial_clk_div == 9'd0 && serial_counter)
serial_counter <= serial_counter - 4'd1;
if (!serial_counter) begin
serial_irq <= 1'b1; //trigger interrupt
sc_start <= 1'b0; //reset transfer state
serial_clk_div <= 9'h1FF;
serial_counter <= 4'd8;
end
end
end
link link (
.clk(clk_cpu),
.rst(reset),
.sel_sc(sel_sc),
.sel_sb(sel_sb),
.cpu_wr_n(cpu_wr_n),
.sc_start_in(cpu_do[7]),
.sc_int_clock_in(cpu_do[0]),
.sb_in(cpu_do),
.serial_clk_in(serial_clk_in),
.serial_data_in(serial_data_in),
.serial_clk_out(serial_clk_out),
.serial_data_out(serial_data_out),
.sb(sb),
.serial_irq(serial_irq),
.sc_start(sc_start),
.sc_int_clock(sc_shiftclock)
);
// --------------------------------------------------------------------
// ------------------------------ inputs ------------------------------

108
link.v Normal file
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@@ -0,0 +1,108 @@
module link #(
parameter CLK_DIV = 511
)(
// system signals
input clk,
input rst,
input sel_sc,
input sel_sb,
input cpu_wr_n,
input sc_start_in,
input sc_int_clock_in,
input [7:0] sb_in,
input serial_clk_in,
input serial_data_in,
output serial_clk_out,
output serial_data_out,
output [7:0] sb,
output serial_irq,
output reg sc_start,
output reg sc_int_clock
);
assign sb = sb_r;
reg [3:0] serial_counter;
reg [7:0] sb_r = 0;
reg serial_out_r = 0;
assign serial_data_out = serial_out_r;
reg serial_clk_out_r = 1;
assign serial_clk_out = serial_clk_out_r;
assign serial_irq = serial_irq_r;
reg serial_irq_r;
reg [8:0] serial_clk_div; //8192Hz
reg [1:0] serial_clk_in_last;
// serial master
always @(posedge clk) begin
serial_irq_r <= 1'b0;
if(rst) begin
sc_start <= 1'b0;
sc_int_clock <= 1'b0;
sb_r <= sb_in;
//serial_clk_in_last <= serial_clk_in;
serial_clk_in_last <= {1'b0,serial_clk_in};
end else if (sel_sc && !cpu_wr_n) begin //cpu write
sc_start <= sc_start_in;
sc_int_clock <= sc_int_clock_in;
if (sc_start_in) begin //enable transfer
serial_clk_div <= CLK_DIV[8:0];
serial_counter <= 4'd8;
serial_clk_out_r <= 1'b1;
//serial_clk_in_last <= serial_clk_in;
serial_clk_in_last <= {1'b0,serial_clk_in};
end
end else if (sel_sb && !cpu_wr_n) begin
sb_r <= sb_in;
end else if (sc_start) begin // serial transfer
if (sc_int_clock) begin // internal clock
serial_clk_div <= serial_clk_div - 9'd1;
if (serial_counter != 0) begin
if (serial_clk_div == {1'b0,CLK_DIV[8:1]+1'd1}) begin
serial_clk_out_r <= ~serial_clk_out_r;
serial_out_r <= sb[7];
end else if (!serial_clk_div) begin
sb_r <= {sb[6:0], serial_data_in};
serial_clk_out_r <= ~serial_clk_out;
serial_counter <= serial_counter - 1'd1;
serial_clk_div <= CLK_DIV[8:0];
end
end else begin
serial_irq_r <= 1'b1;
sc_start <= 1'b0;
serial_clk_div <= CLK_DIV[8:0];
serial_counter <= 4'd8;
end
end else begin // external clock
serial_clk_in_last[0] <= serial_clk_in;
serial_clk_in_last[1] <= serial_clk_in_last[0] ;
if (serial_clk_in_last[1] != serial_clk_in_last[0]) begin
if (serial_clk_in_last[1] == 0) begin
serial_out_r <= sb[7]; // send out bit to linked gb
serial_counter <= serial_counter - 1'd1;
end else begin // posedge external clock
sb_r <= {sb[6:0], serial_data_in}; // capture bit into sb
if (serial_counter == 0) begin // read in 8 bits?
serial_irq_r <= 1'b1; // set interrupt, reset counter/sc_start for next read
sc_start <= 1'b0;
serial_counter <= 4'd8;
end
end
end
end
end
end
endmodule
// vim:sw=3:ts=3:et: