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Update sys.

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This commit is contained in:
sorgelig
2018-12-29 03:33:32 +08:00
parent a5495aafe6
commit 6227c8acc2
6 changed files with 559 additions and 543 deletions
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1031
sys/ascal.vhd
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File diff suppressed because it is too large Load Diff

4
sys/lpf48k.sv
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@@ -76,7 +76,7 @@ always @(posedge RESET or posedge CLK) begin
end
end
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * $signed(IDATA);
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_INTEG <= 0;
@@ -84,7 +84,7 @@ always @(posedge RESET or posedge CLK) begin
begin
if (CE) begin
if (W_ADDR_END) FF_INTEG <= 0;
else FF_INTEG <= FF_INTEG + W_DATA;
else FF_INTEG <= $signed(FF_INTEG) + $signed(W_DATA);
end
end
end

50
sys/reset_source.v Normal file
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@@ -0,0 +1,50 @@
// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire reset_vip, // .reset_vip
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
wire reset_m = sys_reset | reset_hps | reset_req;
assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

3
sys/sys.qip
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@@ -18,7 +18,8 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ip/reset_source.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1

3
sys/sys_q13.qip
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@@ -22,7 +22,8 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ip/reset_source.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1

11
sys/sys_top.v
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@@ -523,14 +523,15 @@ ascal
(
.reset_na (~reset_req),
.run (1),
.freeze (0),
.i_clk (clk_vid),
.i_ce (ce_pix),
.i_r (r_out),
.i_g (g_out),
.i_b (b_out),
.i_hs (hs_emu),
.i_vs (vs_emu),
.i_hs (hs),
.i_vs (vs),
.i_fl (f1),
.i_de (de),
.iauto (1),
@@ -560,7 +561,7 @@ ascal
.vmin (vmin),
.vmax (vmax),
.mode ({1'b1,scaler_flt ? 3'd4 : 3'd0}),
.mode ({1'b1,scaler_flt,2'b00}),
.poly_clk (clk_sys),
.poly_a (coef_addr),
.poly_dw (coef_data),
@@ -901,8 +902,8 @@ wire [1:0] led_power;
wire [1:0] led_disk;
wire vs_emu, hs_emu;
sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs);
sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs);
sync_fix sync_v(clk_vid, vs_emu, vs);
sync_fix sync_h(clk_vid, hs_emu, hs);
wire uart_dtr;
wire uart_dsr;