mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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sys: update the scaler.
This commit is contained in:
sorgelig
791
sys/ascal.vhd
791
sys/ascal.vhd
File diff suppressed because it is too large
Load Diff
@@ -5,14 +5,15 @@
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-- Changes the HDMI PLL frequency according to the scaler suggestions.
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--------------------------------------------
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-- LLTUNE :
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-- 15 : Toggle
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-- 14 : Unused
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-- 13 : Sign phase difference
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-- 12:8 : Phase difference. Log (0=Large 31=Small)
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-- 7:6 : Unused
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-- 5 : Sign period difference.
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-- 4:0 : Period difference. Log (0=Large 31=Small)
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-- 0 : Input Syncline
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-- 1 :
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-- 2 : Input Interlaced mode
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-- 3 : Input Interlaced field
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-- 4 : Output Syncline
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-- 5 :
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-- 6 : Input clock
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-- 7 : Output clock
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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@@ -23,6 +24,8 @@ ENTITY pll_hdmi_adj IS
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llena : IN std_logic; -- 0=Disabled 1=Enabled
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lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler
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locked : OUT std_logic;
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-- Signals from reconfig commands
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i_waitrequest : OUT std_logic;
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i_write : IN std_logic;
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@@ -51,24 +54,115 @@ ARCHITECTURE rtl OF pll_hdmi_adj IS
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SIGNAL pwrite : std_logic;
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SIGNAL paddress : unsigned(5 DOWNTO 0);
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SIGNAL pdata : unsigned(31 DOWNTO 0);
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TYPE enum_state IS (sIDLE,sW1,sW2,sW3);
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TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
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SIGNAL state : enum_state;
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SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
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SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
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SIGNAL mfrac,mfrac_mem : unsigned(31 DOWNTO 0);
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SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
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SIGNAL mul : unsigned(15 DOWNTO 0);
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SIGNAL sign,sign_pre : std_logic;
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SIGNAL up,modo,phm,dir : std_logic;
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SIGNAL fcpt : natural RANGE 0 TO 3;
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SIGNAL cptx : natural RANGE 0 TO 3;
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SIGNAL cpt : natural RANGE 0 TO 4095;
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SIGNAL phcor : natural RANGE 0 TO 3;
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SIGNAL diff : unsigned(31 DOWNTO 0);
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TYPE enum_tstate IS (sWAIT,sADJ,sADJ2);
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SIGNAL tstate : enum_tstate;
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SIGNAL cpt : natural RANGE 0 TO 3;
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SIGNAL col : natural RANGE 0 TO 15;
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SIGNAL icpt,ocpt,ssh : natural RANGE 0 TO 2**24-1;
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SIGNAL isync,isync2,itog,ipulse : std_logic;
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SIGNAL osync,osync2,otog,opulse : std_logic;
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SIGNAL sync,pulse,los,lop : std_logic;
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SIGNAL osize,isize,offset,osizep : signed(23 DOWNTO 0);
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SIGNAL logcpt : natural RANGE 0 TO 31;
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SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
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BEGIN
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----------------------------------------------------------------------------
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-- Sample image sizes
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Sampler:PROCESS(clk,reset_na) IS
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BEGIN
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IF reset_na='0' THEN
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--pragma synthesis_off
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otog<='0';
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itog<='0';
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isync<='0';
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isync2<='0';
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osync<='0';
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osync2<='0';
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--pragma synthesis_on
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ELSIF rising_edge(clk) THEN
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-- Clock domain crossing
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isync<=lltune(0); -- <ASYNC>
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isync2<=isync;
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osync<=lltune(4); -- <ASYNC>
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osync2<=osync;
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itog<=itog XOR (isync AND NOT isync2);
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otog<=otog XOR (osync AND NOT osync2);
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ipulse<=isync AND NOT isync2 AND itog;
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opulse<=osync AND NOT osync2 AND otog;
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-- Measure output image size
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IF osync='1' AND osync2='0' AND otog='1' THEN
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ocpt<=0;
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osizep<=to_signed(ocpt,24);
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ELSE
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ocpt<=ocpt+1;
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END IF;
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-- Measure input image size
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IF isync='1' AND isync2='0' AND itog='1' THEN
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icpt<=0;
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isize<=to_signed(icpt,24);
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osize<=osizep;
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offset<=to_signed(ocpt,24);
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udiff<=integer(to_integer(osizep)) - integer(icpt);
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sync<='1';
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ELSE
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icpt<=icpt+1;
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sync<='0';
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END IF;
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--------------------------------------------
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pulse<='0';
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IF sync='1' THEN
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logcpt<=0;
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ssh<=to_integer(osize);
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los<='0';
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lop<='0';
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ELSIF logcpt<24 THEN
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-- Frequency difference
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IF udiff>0 AND ssh<udiff AND los='0' THEN
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tune_freq<='0' & to_unsigned(logcpt,5);
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los<='1';
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ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
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tune_freq<='1' & to_unsigned(logcpt,5);
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los<='1';
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END IF;
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-- Phase difference
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IF offset<osize/2 AND ssh<offset AND lop='0' THEN
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tune_phase<='0' & to_unsigned(logcpt,5);
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lop<='1';
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ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
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tune_phase<='1' & to_unsigned(logcpt,5);
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lop<='1';
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END IF;
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ssh<=ssh/2;
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logcpt<=logcpt+1;
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ELSIF logcpt=24 THEN
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pulse<='1';
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ssh<=ssh/2;
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logcpt<=logcpt+1;
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END IF;
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END IF;
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END PROCESS Sampler;
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----------------------------------------------------------------------------
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-- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
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-- 000111 : M counter Fractional Value
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-- 000100 : M counter
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-- 000111 : M counter Fractional Value K
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Comb:PROCESS(i_write,i_address,
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i_writedata,pwrite,paddress,pdata) IS
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@@ -88,141 +182,169 @@ BEGIN
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----------------------------------------------------------------------------
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Schmurtz:PROCESS(clk,reset_na) IS
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VARIABLE off,ofp : natural RANGE 0 TO 63;
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VARIABLE dif : unsigned(31 DOWNTO 0);
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VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
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VARIABLE diff_v : unsigned(40 DOWNTO 0);
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VARIABLE mulco : unsigned(15 DOWNTO 0);
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VARIABLE up_v,sign_v : std_logic;
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BEGIN
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IF reset_na='0' THEN
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modo<='0';
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state<=sIDLE;
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ELSIF rising_edge(clk) THEN
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IF i_address="000111" AND i_write='1' THEN
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mfrac<=i_writedata;
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mfrac_mem<=i_writedata;
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------------------------------------------------------
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-- Snoop accesses to PLL reconfiguration
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IF i_address="000100" AND i_write='1' THEN
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mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
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('0' & i_writedata(7 DOWNTO 0));
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mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
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('0' & i_writedata(7 DOWNTO 0));
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mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
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('0' & i_writedata(7 DOWNTO 0));
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mul<=i_writedata(15 DOWNTO 0);
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modo<='1';
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END IF;
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lltune_sync<=lltune; -- <ASYNC>
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lltune_sync2<=lltune_sync;
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lltune_sync3<=lltune_sync2;
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off:=to_integer('0' & lltune_sync(4 DOWNTO 0));
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ofp:=to_integer('0' & lltune_sync(12 DOWNTO 8));
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IF lltune_sync(15)/=lltune_sync2(15) THEN
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fcpt<=fcpt+1;
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IF fcpt=2 THEN fcpt<=0; END IF;
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IF i_address="000111" AND i_write='1' THEN
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mfrac (31 DOWNTO 0)<=i_writedata;
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mfrac_ref(31 DOWNTO 0)<=i_writedata;
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mfrac_mem(31 DOWNTO 0)<=i_writedata;
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modo<='1';
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END IF;
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CASE tstate IS
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WHEN sWAIT =>
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cpt<=0;
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IF lltune_sync3(15)/=lltune_sync2(15) AND llena='1' THEN
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IF llena='0' THEN
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-- Recover original freq when disabling low lag mode
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phm<='0';
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IF modo='1' THEN
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mfrac<=mfrac_mem;
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up<='1';
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modo<='0';
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END IF;
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ELSIF phm='0' AND fcpt=2 THEN
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-- Frequency adjust
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IF off<10 THEN off:=10; END IF;
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dif:=shift_right(mfrac,off + 1);
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diff<=dif;
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sign<=lltune_sync(5);
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IF off>=18 THEN
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phm<='1';
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ELSE
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tstate<=sADJ;
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END IF;
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cptx<=0;
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ELSIF phm='1' THEN
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-- Phase adjust
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IF ofp<5 THEN ofp:=5; END IF;
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dif:=shift_right(mfrac,ofp + 3 + 1);
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IF (ofp>=18 OR off<16) AND fcpt=2 AND phcor=0 THEN
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phm<='0';
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END IF;
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IF phcor=0 THEN
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IF cptx=0 THEN
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sign<=NOT lltune_sync(13);
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sign_pre<=sign;
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diff<=dif;
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IF sign_pre/=NOT lltune_sync(13) THEN
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diff<='0' & dif(31 DOWNTO 1);
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END IF;
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END IF;
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cptx<=cptx+1;
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IF cptx=2 THEN
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cptx<=0;
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sign<=NOT sign;
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phcor<=1;
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END IF;
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tstate<=sADJ;
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ELSIF phcor=1 THEN
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cptx<=cptx+1;
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IF cptx=2 THEN
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cptx<=0;
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phcor<=2;
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tstate<=sADJ;
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END IF;
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ELSIF fcpt=2 THEN
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phcor<=0;
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cptx<=0;
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END IF;
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END IF;
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END IF;
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WHEN sADJ =>
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IF sign='0' THEN
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mfrac<=mfrac + diff(31 DOWNTO 8);
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ELSE
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mfrac<=mfrac - diff(31 DOWNTO 8);
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END IF;
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IF up='0' THEN
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up<='1';
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tstate<=sADJ2;
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END IF;
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WHEN sADJ2 =>
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cpt<=cpt+1;
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IF cpt=1023 THEN
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tstate<=sWAIT;
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ELSE
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tstate<=sADJ;
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END IF;
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END CASE;
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------------------------------------------------------
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-- Tuning
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off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
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ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
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--IF off_v<8 THEN off_v:=8; END IF;
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--IF ofp_v<7 THEN ofp_v:=7; END IF;
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IF off_v<4 THEN off_v:=4; END IF;
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IF ofp_v<4 THEN ofp_v:=4; END IF;
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IF off_v>=18 AND ofp_v>=18 THEN
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locked<=llena;
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ELSE
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locked<='0';
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END IF;
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up_v:='0';
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IF pulse='1' THEN
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cpt<=(cpt+1) MOD 4;
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IF llena='0' THEN
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-- Recover original freq when disabling low lag mode
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cpt<=0;
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col<=0;
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IF modo='1' THEN
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mfrac<=mfrac_mem;
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mfrac_ref<=mfrac_mem;
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up<='1';
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modo<='0';
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END IF;
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ELSIF phm='0' AND cpt=0 THEN
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-- Frequency adjust
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sign_v:=tune_freq(5);
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IF col<10 THEN col<=col+1; END IF;
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IF off_v>=16 AND col>=10 THEN
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phm<='1';
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col<=0;
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ELSE
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off_v:=off_v+1;
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IF off_v>17 THEN
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off_v:=off_v + 3;
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END IF;
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up_v:='1';
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up<='1';
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END IF;
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ELSIF cpt=0 THEN
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-- Phase adjust
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sign_v:=NOT tune_phase(5);
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col<=col+1;
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IF col>=10 THEN
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phm<='0';
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up_v:='1';
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off_v:=31;
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col<=0;
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ELSE
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off_v:=ofp_v + 1;
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IF ofp_v>7 THEN
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off_v:=off_v + 1;
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END IF;
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IF ofp_v>14 THEN
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off_v:=off_v + 2;
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END IF;
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IF ofp_v>17 THEN
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off_v:=off_v + 3;
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END IF;
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up_v:='1';
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END IF;
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up<='1';
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END IF;
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END IF;
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diff_v:=shift_right(mfrac_ref,off_v);
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IF sign_v='0' THEN
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diff_v:=mfrac_ref + diff_v;
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ELSE
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diff_v:=mfrac_ref - diff_v;
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END IF;
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IF up_v='1' THEN
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mfrac<=diff_v;
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END IF;
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IF up_v='1' AND phm='0' THEN
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mfrac_ref<=diff_v;
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END IF;
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------------------------------------------------------
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-- Update PLL registers
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mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
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CASE state IS
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WHEN sIDLE =>
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pwrite<='0';
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IF up='1' THEN
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up<='0';
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state<=sW1;
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pdata<=mfrac;
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paddress<="000111";
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pwrite<='1';
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IF mulco/=mul THEN
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state<=sW1;
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ELSE
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state<=sW3;
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END IF;
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END IF;
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WHEN sW1 =>
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WHEN sW1 => -- Change M multiplier
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mul<=mulco;
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pdata<=x"0000" & mulco;
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paddress<="000100";
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pwrite<='1';
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state<=sW2;
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WHEN sW2 =>
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IF pwrite='1' AND o_waitrequest='0' THEN
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state<=sW2;
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state<=sW3;
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pwrite<='0';
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END IF;
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WHEN sW2 =>
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WHEN sW3 => -- Change M fractional value
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pdata<=mfrac(31 DOWNTO 0);
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paddress<="000111";
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pwrite<='1';
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state<=sW4;
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WHEN sW4 =>
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IF pwrite='1' AND o_waitrequest='0' THEN
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state<=sW5;
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pwrite<='0';
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END IF;
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WHEN sW5 =>
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pdata<=x"0000_0001";
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paddress<="000010";
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pwrite<='1';
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state<=sW3;
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state<=sW6;
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WHEN sW3 =>
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WHEN sW6 =>
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IF pwrite='1' AND o_waitrequest='0' THEN
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pwrite<='0';
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state<=sIDLE;
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@@ -233,7 +355,6 @@ BEGIN
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END PROCESS Schmurtz;
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----------------------------------------------------------------------------
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END ARCHITECTURE rtl;
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