mister-devel/Gameboy_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/Gameboy_MiSTer.git synced 2026-04-26 03:04:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

CPU: Read on TCycle 3 instead of 2

Browse Source
This commit is contained in:
paulb-nl
2021-03-11 22:31:47 +01:00
parent 553e0a8609
commit 2ce35cccd5
2 changed files with 19 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
rtl/T80/GBse.vhd
View File

@@ -206,7 +206,7 @@ begin
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
if TState = "001" or TState = "010" then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
end if;
@@ -214,11 +214,11 @@ begin
MREQ_n <= '0';
end if;
elsif MCycle = "011" and IntCycle_n = '0' then
if TState = "001" then
if TState = "010" then
IORQ_n <= '0'; -- Acknowledge IRQ
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
if (TState = "001" or TState = "010") and (NoRead = '0' and Write = '0') then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
@@ -237,7 +237,7 @@ begin
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
if TState = "011" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;

18
rtl/T80/T80.vhd
View File

@@ -698,7 +698,11 @@ begin
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
if (Mode = 3) then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DInst));
else
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
@@ -732,10 +736,18 @@ begin
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
if (Mode = 3) then
TmpAddr(7 downto 0) <= DInst;
else
TmpAddr(7 downto 0) <= DI_Reg;
end if;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
if (Mode = 3) then
TmpAddr(15 downto 8) <= DInst;
else
TmpAddr(15 downto 8) <= DI_Reg;
end if;
end if;
if Special_LD(2) = '1' then