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69 lines
1.6 KiB
Systemverilog
69 lines
1.6 KiB
Systemverilog
module divider (
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input wire clk,
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input wire clk_en,
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input wire reset,
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input wire [3:0] cpu_id,
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input wire reset_gamma,
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input wire reset_divider,
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input wire reset_divider_keep_6,
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output reg gamma = 0,
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output reg divider_1s_tick = 0, // Temp value to wake from halt
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output wire divider_4hz,
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output wire divider_32hz,
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output wire divider_64hz,
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output wire divider_1khz,
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output reg [14:0] divider = 0
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);
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assign divider_4hz = divider[14];
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assign divider_32hz = divider[11];
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assign divider_64hz = divider[10];
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assign divider_1khz = divider[4];
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always @(posedge clk) begin
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if (reset) begin
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case (cpu_id)
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4: gamma <= 1; // SM5a
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default: gamma <= 0; // SM510/SM510 Tiger
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endcase
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divider <= 0;
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divider_1s_tick <= 0;
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end else if (clk_en) begin
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divider_1s_tick <= 0;
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if (reset_gamma) begin
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gamma <= 0;
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end
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if (reset_divider) begin
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// TODO: Remove. This is to match MAME testing
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// divider <= 2;
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divider <= 0;
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end else if (reset_divider_keep_6) begin
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reg [14:0] inc_divider;
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// Increment divider as if we were incrementing normally
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inc_divider = divider + 15'h1;
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divider[14:6] <= 0;
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// Grab only the lower 6 bits
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divider[5:0] <= inc_divider[5:0];
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end else begin
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// Increment
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divider <= divider + 15'h1;
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if (divider == 15'h7FFF) begin
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// Will wrap to 0 next cycle. 1 second has elapsed
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gamma <= 1;
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divider_1s_tick <= 1;
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end
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end
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end
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end
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endmodule
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