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Support for SM510 Tiger

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This commit is contained in:
Adam Gastineau
2023-06-26 08:15:13 -07:00
parent 4484e95b33
commit cdba567a39
6 changed files with 26 additions and 10 deletions
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2
rtl/cpu/divider.sv
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@@ -28,7 +28,7 @@ module divider (
if (reset) begin
case (cpu_id)
4: gamma <= 1; // SM5a
default: gamma <= 0; // SM510
default: gamma <= 0; // SM510/SM510 Tiger
endcase
divider <= 0;

2
rtl/cpu/instructions.sv
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@@ -170,7 +170,7 @@ interface instructions (
output_r <= {~stored_output_r[3:1], r0_mask && ~stored_output_r[0]};
end
default: begin
// SM510
// SM510/SM510 Tiger
if (output_r_mask == R_MASK_DIRECT) begin
output_r <= {2'b0, stored_output_r[1:0]};
end else begin

2
rtl/input_config.sv
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@@ -47,7 +47,7 @@ module input_config (
else if (output_r[3]) active_input_config = sys_config.input_s2_config;
end
default: begin
// SM510
// SM510/SM510 Tiger
if (output_shifter_s[0]) active_input_config = sys_config.input_s0_config;
else if (output_shifter_s[1]) active_input_config = sys_config.input_s1_config;
else if (output_shifter_s[2]) active_input_config = sys_config.input_s2_config;

2
rtl/ram.sv
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@@ -56,7 +56,7 @@ module ram (
end
end
default: begin
// SM510
// SM510/SM510 Tiger
computed_addr = addr;
end
endcase

26
rtl/sm510.sv
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@@ -208,15 +208,21 @@ module sm510 (
////////////////////////////////////////////////////////////////////////////////////////
// Stages
// SM510 | SM510 Tiger
wire is_sm510 = cpu_id == 0 || cpu_id == 5;
// SM5a
wire is_sm5a = cpu_id == 4;
// LBL xy | TL/TML xyz
wire is_two_bytes_sm510 = opcode == 8'h5F || opcode[7:4] == 4'h7;
// LBL xy | CEND/DTA
wire is_two_bytes_sm5a = opcode == 8'h5F || opcode == 8'h5E;
wire is_two_bytes = cpu_id == 4 ? is_two_bytes_sm5a : is_two_bytes_sm510;
wire is_two_bytes = is_sm5a ? is_two_bytes_sm5a : is_two_bytes_sm510;
// TM x
wire is_tm = cpu_id == 0 && opcode[7:6] == 2'b11;
wire is_tm = is_sm510 && opcode[7:6] == 2'b11;
// LAX x
wire is_lax = opcode[7:4] == 4'h2;
@@ -514,6 +520,8 @@ module sm510 (
// TODO: Is this correct, it doesn't match MAME?
wire [11:0] pc_inc = {inst.Pu, inst.Pm, inst.Pl[0] == inst.Pl[1], inst.Pl[5:1]};
reg [11:0] last_pc /* synthesis noprune */;
always @(posedge clk) begin
if (reset) begin
// WARNING: Reset must be high for greater than one cycle so that data can cascade through
@@ -573,8 +581,14 @@ module sm510 (
// SM5a
inst.stored_output_r <= 4'hF;
inst.output_r_mask <= inst.R_MASK_DIRECT;
inst.stack_s <= inst.pc;
end
5: begin
// SM510 Tiger
inst.output_r_mask <= inst.R_MASK_DIRECT;
end
default: begin
// SM510
inst.stored_output_r <= 0;
@@ -614,6 +628,8 @@ module sm510 (
last_Pl <= inst.Pl;
end
last_pc <= inst.pc;
case (stage)
STAGE_LOAD_PC: begin
inst.skip_next_instr <= 0;
@@ -637,7 +653,7 @@ module sm510 (
// Load PC at 1_0_00
case (cpu_id)
4: {inst.Pu, inst.Pm, inst.Pl} <= {2'b0, 4'b0, 6'b0}; // SM5a
default: {inst.Pu, inst.Pm, inst.Pl} <= {2'b1, 4'b0, 6'b0}; // SM510
default: {inst.Pu, inst.Pm, inst.Pl} <= {2'b1, 4'b0, 6'b0}; // SM510/SM510 Tiger
endcase
inst.cb_bank <= 0;
@@ -652,7 +668,7 @@ module sm510 (
case (cpu_id)
4: sm5a_decode();
default: sm510_decode();
default: sm510_decode(); // SM510/SM510 Tiger
endcase
end
STAGE_PERF_3: begin
@@ -671,7 +687,7 @@ module sm510 (
end
8'h7X: begin
// Only is TL/TML if SM510
if (cpu_id == 0) begin
if (is_sm510) begin
// This is weird and goes up to 0xA for some reason, so we need the nested checks
// Notice there is a gap where 0xB is not handled (in the actual CPU)
if (last_opcode[3:0] < 4'hB) begin

2
rtl/video/normalize.sv
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@@ -38,7 +38,7 @@ module normalize #(
end
end
default: begin
// SM510
// SM510/SM510 Tiger
for (y = 0; y < MAX_Y_SEGMENT; y += 1) begin
segments[0][y][output_lcd_h_index] <= current_segment_a[y];
segments[1][y][output_lcd_h_index] <= current_segment_b[y];