mirror of
https://github.com/MiSTer-devel/GameAndWatch_MiSTer.git
synced 2026-05-24 03:03:25 +00:00
Normalize segment data and pass everything through deflicker and vsync
This commit is contained in:
Adam Gastineau
@@ -7,6 +7,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "input_config.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/counts.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/lcd.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/normalize.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/rgb_controller.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/segments.sv"]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "video/video.sv"]
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144
rtl/video/lcd.sv
144
rtl/video/lcd.sv
@@ -26,34 +26,48 @@ module lcd (
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output wire segment_en
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);
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// Segments, over all H's, as last seen
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reg [15:0] segment_a[4];
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reg [15:0] segment_b[4];
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reg [1:0] segment_bs;
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reg [15:0] cache_segment_a[4];
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reg [15:0] cache_segment_b[4];
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reg [1:0] cache_segment_bs;
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reg [3:0] w_prime[9];
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reg [3:0] w_main[9];
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reg [3:0] cache_w_prime[9];
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reg [3:0] cache_w_main[9];
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reg [4:0] decay_w_prime[9][4];
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reg [4:0] decay_w_main[9][4];
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reg prev_divider_1khz = 0;
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// Comb
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reg [1:0] current_h_index;
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reg prev_vblank = 0;
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localparam DECAY_MAX = 5'h1F;
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localparam DECAY_MIN_DISPLAY = 5'h10;
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segments segments (
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localparam MAX_X_SEGMENT = 9;
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localparam MAX_Y_SEGMENT = 16;
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localparam MAX_Z_SEGMENT = 4;
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wire [MAX_Z_SEGMENT-1:0] raw_segments[MAX_X_SEGMENT][MAX_Y_SEGMENT];
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reg [MAX_Z_SEGMENT-1:0] decayed_segments[MAX_X_SEGMENT][MAX_Y_SEGMENT];
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reg [MAX_Z_SEGMENT-1:0] vsync_segments[MAX_X_SEGMENT][MAX_Y_SEGMENT];
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reg [4:0] segment_current_decays[MAX_X_SEGMENT][MAX_Y_SEGMENT][MAX_Z_SEGMENT-1:0];
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reg prev_divider_1khz = 0;
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reg prev_vblank = 0;
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normalize #(
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.MAX_X_SEGMENT(MAX_X_SEGMENT),
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.MAX_Y_SEGMENT(MAX_Y_SEGMENT),
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.MAX_Z_SEGMENT(MAX_Z_SEGMENT)
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) normalize (
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.clk(clk),
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.cpu_id(cpu_id),
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.current_segment_a (current_segment_a),
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.current_segment_b (current_segment_b),
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.current_segment_bs(current_segment_bs),
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.current_w_prime(current_w_prime),
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.current_w_main (current_w_main),
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.output_lcd_h_index(output_lcd_h_index),
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.segments(raw_segments)
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);
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segments #(
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.MAX_X_SEGMENT(MAX_X_SEGMENT),
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.MAX_Y_SEGMENT(MAX_Y_SEGMENT),
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.MAX_Z_SEGMENT(MAX_Z_SEGMENT)
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) lcd_segments (
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.clk(clk),
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.cpu_id(cpu_id),
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@@ -61,13 +75,7 @@ module lcd (
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.mask_data_wr(mask_data_wr),
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.mask_data(mask_data),
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// Segments
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.cache_segment_a (cache_segment_a),
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.cache_segment_b (cache_segment_b),
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.cache_segment_bs(cache_segment_bs),
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.cache_w_prime(cache_w_prime),
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.cache_w_main (cache_w_main),
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.segments(vsync_segments),
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.vblank_int(vblank_int),
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.hblank_int(hblank_int),
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@@ -78,67 +86,39 @@ module lcd (
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);
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always @(posedge clk) begin
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int i;
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int j;
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int x, y, z;
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prev_vblank <= vblank_int;
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prev_divider_1khz <= divider_1khz;
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// TODO: This is very similar to the logic already in `ram.sv`
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segment_a[output_lcd_h_index] <= current_segment_a;
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segment_b[output_lcd_h_index] <= current_segment_b;
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segment_bs[output_lcd_h_index] <= current_segment_bs;
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if (output_lcd_h_index[0]) begin
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// W'
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w_prime <= current_w_prime;
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end else begin
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// W
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w_main <= current_w_main;
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end
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// Pass raw segments through deflicker stage
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if (divider_1khz && ~prev_divider_1khz) begin
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for (i = 0; i < 9; i += 1) begin
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for (j = 0; j < 4; j += 1) begin
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// W'
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// Modify decay
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if (w_prime[i][j] && decay_w_prime[i][j] < DECAY_MAX) begin
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// Segment is on, and decay isn't max
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// Increment decay
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decay_w_prime[i][j] <= decay_w_prime[i][j] + 5'h1;
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end else if (~w_prime[i][j] && decay_w_prime[i][j] > 5'h0) begin
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// Segment is off, and decay isn't min
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// Decrement decay
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decay_w_prime[i][j] <= decay_w_prime[i][j] - 5'h1;
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for (x = 0; x < MAX_X_SEGMENT; x += 1) begin
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for (y = 0; y < MAX_Y_SEGMENT; y += 1) begin
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for (z = 0; z < MAX_Z_SEGMENT; z += 1) begin
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reg [4:0] current_decay;
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current_decay = segment_current_decays[x][y][z];
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if (raw_segments[x][y][z] && current_decay < DECAY_MAX) begin
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// Segment is on, and decay isn't max
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// Increment decay
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segment_current_decays[x][y][z] <= current_decay + 5'h1;
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end else if (~raw_segments[x][y][z] && current_decay > 5'h0) begin
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// Segment is off, and decay isn't min
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// Decrement decay
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segment_current_decays[x][y][z] <= current_decay - 5'h1;
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end
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// Update segment array (an iteration delayed)
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decayed_segments[x][y][z] <= current_decay > DECAY_MIN_DISPLAY;
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end
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// Update segment array (an iteration delayed)
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cache_w_prime[i][j] <= decay_w_prime[i][j] > DECAY_MIN_DISPLAY;
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// W
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if (w_main[i][j] && decay_w_main[i][j] < DECAY_MAX) begin
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decay_w_main[i][j] <= decay_w_main[i][j] + 5'h1;
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end else if (~w_main[i][j] && decay_w_main[i][j] > 5'h0) begin
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decay_w_main[i][j] <= decay_w_main[i][j] - 5'h1;
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end
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cache_w_main[i][j] <= decay_w_main[i][j] > DECAY_MIN_DISPLAY;
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end
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end
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end
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// Pass deflickered segment through vblank buffer stage
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if (vblank_int && ~prev_vblank) begin
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cache_segment_a[0] <= segment_a[0];
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cache_segment_a[1] <= segment_a[1];
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cache_segment_a[2] <= segment_a[2];
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cache_segment_a[3] <= segment_a[3];
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cache_segment_b[0] <= segment_b[0];
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cache_segment_b[1] <= segment_b[1];
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cache_segment_b[2] <= segment_b[2];
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cache_segment_b[3] <= segment_b[3];
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cache_segment_bs <= segment_bs;
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vsync_segments <= decayed_segments;
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end
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end
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endmodule
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53
rtl/video/normalize.sv
Normal file
53
rtl/video/normalize.sv
Normal file
@@ -0,0 +1,53 @@
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module normalize #(
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parameter MAX_X_SEGMENT = 9,
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parameter MAX_Y_SEGMENT = 16,
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parameter MAX_Z_SEGMENT = 4
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) (
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input wire clk,
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input wire [3:0] cpu_id,
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input wire [15:0] current_segment_a,
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input wire [15:0] current_segment_b,
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input wire current_segment_bs,
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input wire [3:0] current_w_prime[9],
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input wire [3:0] current_w_main [9],
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input wire [1:0] output_lcd_h_index,
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// Z is used for one hot bit selection, hence the width
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output reg [MAX_Z_SEGMENT-1:0] segments[MAX_X_SEGMENT][MAX_Y_SEGMENT]
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);
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always @(posedge clk) begin
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int x, y, z;
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case (cpu_id)
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4: begin
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// SM5a
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for (x = 0; x < MAX_X_SEGMENT; x += 1) begin
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// Only 4 Y segments
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for (y = 0; y < 4; y += 1) begin
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if (output_lcd_h_index[0]) begin
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segments[x][y][0] <= current_w_main[x][y];
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end else begin
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segments[x][y][1] <= current_w_prime[x][y];
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end
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end
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end
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end
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default: begin
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// SM510
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for (y = 0; y < MAX_Y_SEGMENT; y += 1) begin
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segments[0][y][output_lcd_h_index] <= current_segment_a[y];
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segments[1][y][output_lcd_h_index] <= current_segment_b[y];
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// BS is a special case as a single bit, and is set for all Y
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segments[2][y][output_lcd_h_index] <= current_segment_bs;
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end
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end
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endcase
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end
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endmodule
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@@ -1,4 +1,8 @@
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module segments (
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module segments #(
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parameter MAX_X_SEGMENT = 9,
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parameter MAX_Y_SEGMENT = 16,
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parameter MAX_Z_SEGMENT = 4
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) (
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input wire clk,
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input wire [3:0] cpu_id,
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@@ -6,13 +10,7 @@ module segments (
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input wire mask_data_wr,
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input wire [15:0] mask_data,
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// Segments
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input wire [15:0] cache_segment_a [4],
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input wire [15:0] cache_segment_b [4],
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input wire [ 1:0] cache_segment_bs,
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input wire [3:0] cache_w_prime[9],
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input wire [3:0] cache_w_main [9],
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input wire [MAX_Z_SEGMENT-1:0] segments[MAX_X_SEGMENT][MAX_Y_SEGMENT],
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// Video counters
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input wire vblank_int,
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@@ -53,29 +51,7 @@ module segments (
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segment_en = 0;
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if (has_segment) begin
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case (cpu_id)
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4: begin
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// SM5a
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if (segment_row == 2'h1) begin
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// W'
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segment_en = cache_w_prime[segment_line_select][segment_column];
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end else begin
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// W
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segment_en = cache_w_main[segment_line_select][segment_column];
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end
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end
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default: begin
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// SM510
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case (segment_line_select)
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4'h0: segment_en = cache_segment_a[segment_row][segment_column];
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4'h1: segment_en = cache_segment_b[segment_row][segment_column];
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4'h2: segment_en = cache_segment_bs[segment_row];
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default: begin
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// TODO: What happens in these cases?
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end
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endcase
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end
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endcase
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segment_en = segments[segment_line_select][segment_column][segment_row];
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end
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end
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endmodule
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