mister-devel/GBA_MiSTer
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15 Commits

Author SHA1 Message Date
Robert Peip
f64e1afb41 add vhdl conversion of the ddram module for testbench 2022-11-01 18:46:09 +01:00
Robert Peip
18fb0bd3d2 removed not needed file from vcom compile list 2021-07-31 15:30:47 +02:00
Robert Peip
c3419951c3 add missing file 2021-07-31 15:30:06 +02:00
Robert Peip
aaa82231bb turned off soundchannels are no longer reactivated upon savestate loading 
Implement savestate for SoundDMA to load back at correct sound fifo fillcount to have correct timing
 2021-05-09 13:29:38 +02:00
Robert Peip
1d61873746 correct behavior for undefined opcode (ret from nonstoring alu commands), thanks to JSMolka testsuite. Updated testbench 2020-11-08 11:11:21 +01:00
Robert Peip
cbeb6da8cc - added 2x resolution mode 
- updated framework
- improved ddr3 access latency
- 30Hz flickereduce option
 2020-06-17 15:33:34 +02:00
Robert Peip
32b88edc69 fix sprite drawing in fastforward mode 2020-04-08 09:18:33 +02:00
Robert Peip
a4518bc62d rtc counting with GBA time, save/load interface for RTC added 2020-03-24 12:58:21 +01:00
Robert Peip
dd977c498c add shared GPIO module with RTC + Gyro + Solar + Rumble 2020-03-03 18:37:55 +01:00
Robert Peip
8078d0b4f5 fix savestate position, so saving to disk works again 2020-01-25 13:46:13 +01:00
Robert Peip
69e47d95ba rewind added 2020-01-23 20:31:20 +01:00
Robert Peip
7946a73d14 speedup savestate creation/load 2020-01-22 19:24:04 +01:00
Robert Peip
e16206b254 testbench: fixed ddrram model, added automatic test for savestates 2020-01-22 16:12:07 +01:00
Robert Peip
592c32fbdf simulation: loading of ROM + savestate added, fix bug where savestate loading could hang savestate processing until reboot 2020-01-22 13:59:12 +01:00
Robert Peip
bac5249ef5 added simulation framework 2020-01-22 12:29:33 +01:00