mirror of
https://github.com/MiSTer-devel/FlappyBird_MiSTer.git
synced 2026-04-19 03:04:06 +00:00
235 lines
4.0 KiB
Verilog
235 lines
4.0 KiB
Verilog
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module TopModule(Clk,Button,sys_reset, vga_h_sync, vga_v_sync, vga_h_blank, vga_v_blank, vga_R, vga_G, vga_B,Speaker);
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input Clk,Button,sys_reset;
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output vga_h_sync, vga_v_sync, vga_h_blank, vga_v_blank, vga_R, vga_G, vga_B ,Speaker;
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wire [15:0] CounterX;
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wire [15:0] CounterY;
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wire [24:0] Clks;
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wire Status;
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wire [15:0] Pattern1;
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wire [15:0] Pattern2;
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wire [15:0] PipesPosition1;
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wire [15:0] PipesPosition2;
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wire Button;
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wire [2:0] background, onbackground_on, onbackground_off, bird_on, bird_off, pipes_on, pipes_off,
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pipes2_on, pipes2_off, score_on, score_off, item_on, item_off, board_on, board_off;
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wire hblank, vblank;
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VGAOut syncgen(
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.Clk(Clk),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vblank(vblank),
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.hblank(hblank),
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.CounterX(CounterX),
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.CounterY(CounterY)
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);
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//Debouncer deb (Clk,Button,Button);
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reg [14:0] reset_cnt = 0;
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wire Reset = ~|reset_cnt;
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always @(posedge Clk) begin
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if (~sys_reset)
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reset_cnt <= 1;
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if (reset_cnt > 0)
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reset_cnt <= reset_cnt + 1'd1;
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end
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SlowClock s1 (
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Clk,
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Reset,
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Clks
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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StatusChecker s7 (
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Clk,
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Reset,
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CounterX,
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pipes_off[0],
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pipes2_off[0],
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bird_off[0],
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Status
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);
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DrawBackground s2 (
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Clk,
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Clks,
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Status,
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CounterX,
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CounterY,
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background[0],
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background[1],
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background[2]
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);
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DrawOnBackground s22 (
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Clk,
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Clks,
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CounterX,
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CounterY,
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onbackground_on[0],
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onbackground_on[1],
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onbackground_on[2],
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onbackground_off[0],
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onbackground_off[1],
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onbackground_off[2]
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);
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DrawBird s3 (
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Clk,
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Clks,
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Reset,
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CounterX,
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CounterY,
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Button,
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Status,
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bird_on[0],
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bird_on[1],
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bird_on[2],
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bird_off[0],
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bird_off[1],
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bird_off[2]
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);
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DrawPipes s4 (
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Clk,
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Clks,
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Reset,
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CounterX,
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CounterY,
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Button,
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Status,
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Pattern1,
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pipes_on[0],
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pipes_on[1],
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pipes_on[2],
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pipes_off[0],
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pipes_off[1],
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pipes_off[2],
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PipesPosition1
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);
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DrawPipes2 s44 (
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Clk,
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Clks,
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Reset,
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CounterX,
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CounterY,
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Button,
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Status,
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Pattern2,
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pipes2_on[0],
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pipes2_on[1],
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pipes2_on[2],
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pipes2_off[0],
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pipes2_off[1],
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pipes2_off[2],
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PipesPosition2
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);
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Pattern p (
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Clk,
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Clks,
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Reset,
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PipesPosition1,
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PipesPosition2,
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Button,
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Pattern1,
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Pattern2
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);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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DrawScore s5 (
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Clk,
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Clks,
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Reset,
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PipesPosition1,
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PipesPosition2,
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CounterX,
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CounterY,
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Button,
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Status,
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score_on[0],
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score_on[1],
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score_on[2],
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score_off[0],
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score_off[1],
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score_off[2]
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);
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Sound so (
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Clk,
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PipesPosition1,
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PipesPosition2,
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Speaker
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);
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DrawItem s6 (
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Clk,
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Clks,
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CounterX,
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CounterY,
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Button,
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item_on[0],
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item_on[1],
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item_on[2],
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item_off[0],
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item_off[1],
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item_off[2]
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);
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DrawBoard dd (
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Clk,
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Clks,
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Reset,
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CounterX,
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CounterY,
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Button,
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Status,
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board_on[0],
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board_on[1],
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board_on[2],
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board_off[0],
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board_off[1],
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board_off[2]
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);
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wire RLayer0 = (background[0] | onbackground_on[0]) & ~onbackground_off[0];
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wire GLayer0 = (background[1] | onbackground_on[1]) & ~onbackground_off[1];
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wire BLayer0 = (background[2] | onbackground_on[2]) & ~onbackground_off[2];
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wire RLayer1 = (RLayer0 & ~pipes_off[0]) & ~pipes2_off[0];
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wire GLayer1 = ((GLayer0 | pipes_on[1] | pipes2_on[1]) & ~pipes_off[1]) & ~pipes2_off[1];
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wire BLayer1 = (BLayer0 & ~pipes_off[2]) & ~pipes2_off[2];
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wire RLayer2 = (RLayer1 | board_on[0]) &~board_off[0];
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wire GLayer2 = (GLayer1 | board_on[1]) &~board_off[1];
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wire BLayer2 = (BLayer1 | board_on[2]) &~board_off[2];
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wire RLayer3 = (RLayer2 | bird_on[0]) & ~bird_off[0];
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wire GLayer3 = (GLayer2 | bird_on[1]) & ~bird_off[1];
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wire BLayer3 = (BLayer2 | bird_on[2]) & ~bird_off[2];
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wire RLayer4 = (RLayer3 | score_on[0]) & ~score_off[0];
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wire GLayer4 = (GLayer3 | score_on[1]) & ~score_off[1];
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wire BLayer4 = (BLayer3 | score_on[2]) & ~score_off[2];
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reg vga_R, vga_G, vga_B;
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reg vga_h_blank, vga_v_blank;
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always @(posedge Clk)
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begin
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vga_R <= RLayer4;
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vga_G <= GLayer4;
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vga_B <= BLayer4;
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vga_h_blank <= hblank;
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vga_v_blank <= vblank;
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end
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endmodule
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