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Flappy Bird

Ported from original project here.

This core is written entirely in discrete logic, apparently. Not recommended as a reference example.

Instructions

  • Press Flap
  • When you die, press reset.
Description
Flappy Bird written entirely in discreet logic for MiSTer
Readme 2.6 MiB
Languages
Verilog 69.6%
SystemVerilog 15.7%
VHDL 12.1%
Tcl 2.5%