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12 lines
317 B
Verilog
12 lines
317 B
Verilog
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module StatusChecker(input clk, input Reset,CounterX,input [15:0] R_Pipes_off,input [15:0] R_Pipes2_off,input [15:0] R_Bird_off,output reg Status);
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initial Status = 1;
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always @ (posedge clk)
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begin
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if (!Reset) Status <= 1;
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if ((R_Pipes_off && R_Bird_off) || (R_Pipes2_off && R_Bird_off)) Status <= 0;
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end
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endmodule
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