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21 lines
413 B
Verilog
21 lines
413 B
Verilog
module Sound (
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input clk,
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input [15:0] PipesPosition1,
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input [15:0] PipesPosition2,
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output reg speaker
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);
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wire sound_on = (PipesPosition1 < 10 || PipesPosition2 < 10);
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reg [14:0] counter;
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always @(posedge clk) begin
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if (counter == 0) begin
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speaker <= sound_on ? ~speaker : 1'b0;
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counter <= 28489;
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end else begin
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counter <= counter - 15'd1;
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end
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end
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endmodule
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