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32 lines
681 B
Verilog
32 lines
681 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:51:28 04/23/2014
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// Design Name:
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// Module Name: SlowClock
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SlowClock(input Clk,Reset,output reg [24:0] Clks);
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initial Clks = 0;
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always @ (posedge Clk)
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begin
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if (!Reset) Clks <= 0;
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if(Clks > 25000000) Clks <= 0;
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else Clks <= Clks + 24'd1;
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end
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endmodule
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