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91 lines
2.8 KiB
Verilog
91 lines
2.8 KiB
Verilog
//-------------------------------------------------------------------------------------------------
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// Elan Enterprise memory
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//-------------------------------------------------------------------------------------------------
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// This file is part of the Elan Enterprise FPGA implementation project.
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// Copyright (C) 2023 Kyp069 <kyp069@gmail.com>
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//
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// This program is free software; you can redistribute it and/or modify it under the terms
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// of the GNU General Public License as published by the Free Software Foundation;
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// either version 3 of the License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along with this program;
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// if not, If not, see <https://www.gnu.org/licenses/>.
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//-------------------------------------------------------------------------------------------------
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module memory
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//-------------------------------------------------------------------------------------------------
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(
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input wire clock,
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input wire ce,
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input wire reset,
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input wire iorq,
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input wire mreq,
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input wire rd,
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input wire wr,
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input wire[15:0] a,
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input wire[ 7:0] d,
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output wire[ 7:0] q,
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output wire[21:0] memA2,
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output wire[ 7:0] memD2,
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input wire[ 7:0] memQ2,
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output wire memR2,
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output wire memW2
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);
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//-------------------------------------------------------------------------------------------------
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wire ioB0 = !iorq && a[7:0] == 8'hB0;
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wire ioB1 = !iorq && a[7:0] == 8'hB1;
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wire ioB2 = !iorq && a[7:0] == 8'hB2;
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wire ioB3 = !iorq && a[7:0] == 8'hB3;
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reg[7:0] regB0;
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reg[7:0] regB1;
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reg[7:0] regB2;
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reg[7:0] regB3;
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always @(posedge clock, negedge reset)
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if(!reset) begin
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regB0 <= 8'h00;
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regB1 <= 8'h00;
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regB2 <= 8'h00;
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regB3 <= 8'h00;
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end
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else if(ce) begin
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if(ioB0 && !wr) regB0 <= d;
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if(ioB1 && !wr) regB1 <= d;
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if(ioB2 && !wr) regB2 <= d;
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if(ioB3 && !wr) regB3 <= d;
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end
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reg[7:0] page;
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always @(*) case(a[15:14])
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0: page = regB0;
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1: page = regB1;
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2: page = regB2;
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3: page = regB3;
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endcase
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//-------------------------------------------------------------------------------------------------
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assign q
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= ioB0 ? regB0
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: ioB1 ? regB1
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: ioB2 ? regB2
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: ioB3 ? regB3
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: memQ2;
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assign memA2 = { page, a[13:0] };
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assign memD2 = d;
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assign memR2 = !mreq && !rd;
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assign memW2 = !mreq && !wr;
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//-------------------------------------------------------------------------------------------------
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endmodule
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//-------------------------------------------------------------------------------------------------
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