albconde 86ed4fd6ac First oficial Release
First oficial Release
2025-11-25 20:44:02 +01:00
2025-11-25 20:44:02 +01:00
2025-11-09 20:17:06 +01:00
2025-11-09 20:17:06 +01:00
2025-11-09 20:17:06 +01:00
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2025-11-09 20:17:06 +01:00
2025-11-09 20:17:06 +01:00
2025-11-25 20:40:11 +01:00
2025-11-09 20:17:06 +01:00
2025-11-09 20:17:06 +01:00

Elan Enterprise FPGA implementation for Mister.

Original source : https://github.com/Kyp069/ep by Kyp

Description
Elan Enterprise for MiSTer
Readme 1.9 MiB
Languages
Verilog 46.6%
VHDL 33.5%
SystemVerilog 17%
Tcl 2.5%
Coq 0.3%