mirror of
https://github.com/MiSTer-devel/CoCo2_MiSTer.git
synced 2026-05-17 03:03:29 +00:00
updated sys, new cassette status
This commit is contained in:
Alan Steremberg
129
CoCo2.qsf
129
CoCo2.qsf
@@ -1,63 +1,70 @@
|
||||
# --------------------------------------------------------------------------
|
||||
#
|
||||
# MiSTer project
|
||||
#
|
||||
# WARNING WARNING WARNING:
|
||||
# Do not add files to project in Quartus IDE! It will mess this file!
|
||||
# Add the files manually to files.qip file.
|
||||
#
|
||||
# --------------------------------------------------------------------------
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
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||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# --------------------------------------------------------------------------
|
||||
#
|
||||
# MiSTer project
|
||||
#
|
||||
# WARNING WARNING WARNING:
|
||||
# Do not add files to project in Quartus IDE! It will mess this file!
|
||||
# Add the files manually to files.qip file.
|
||||
#
|
||||
# --------------------------------------------------------------------------
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
|
||||
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
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||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
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||||
set_global_assignment -name SEED 1
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||||
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#set_global_assignment -name VERILOG_MACRO "ARCADE_SYS=1"
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#set_global_assignment -name VERILOG_MACRO "USE_FB=1"
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#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1"
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#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1"
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#do not enable DEBUG_NOHDMI in release!
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#set_global_assignment -name VERILOG_MACRO "DEBUG_NOHDMI=1"
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
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set_global_assignment -name SEED 1
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
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#enable it only if 8bit indexed mode is used in core
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
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#do not enable DEBUG_NOHDMI in release!
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#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
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# disable bilinear filtering when downscaling
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#set_global_assignment -name VERILOG_MACRO "MISTER_DOWNSCALE_NN=1"
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# disable adaptive scanline filtering
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#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ADAPTIVE=1"
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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18
CoCo2.sv
18
CoCo2.sv
@@ -19,6 +19,7 @@
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// Enable overlay (or not)
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`define USE_OVERLAY
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module emu
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(
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//Master input clock
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@@ -29,7 +30,7 @@ module emu
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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@@ -281,7 +282,7 @@ wire [3:0] sd_ack;
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// SD byte level access. Signals for 2-PORT altsyncram.
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din[4];
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wire [7:0] sd_buff_din[4];
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wire sd_buff_wr;
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@@ -331,15 +332,13 @@ hps_io #(.CONF_STR(CONF_STR),.VDNUM(4),.BLKSZ(2)) hps_io
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.joystick_0(joy1),
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.joystick_1(joy2),
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.joystick_analog_0(joya1),
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.joystick_analog_1(joya2),
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.joystick_1(joy2),
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.joystick_l_analog_0(joya1),
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.joystick_l_analog_1(joya2),
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.ps2_key(ps2_key),
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.gamma_bus(gamma_bus)
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);
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@@ -633,8 +632,8 @@ overlay #( .RGB(24'hFFFFFF) ) coverlay
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(
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.reset(reset),
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.i_r(red),
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.i_g(green),
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.i_b(blue),
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.i_g(green),
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.i_b(blue),
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.i_clk(clk_sys),
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.i_pix(CE_PIXEL),
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@@ -648,6 +647,7 @@ overlay #( .RGB(24'hFFFFFF) ) coverlay
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.pos(sdram_addr),
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.max(tape_end),
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.tape_data(sdram_data),
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.ena(cas_relay)
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);
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@@ -11,31 +11,31 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00
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00 87 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88
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00 87 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8f 90 88
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00
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00 87 00 00 00 00 95 83 89 00 00 00 00 00 00 95 83 89 00 00 00 00 88
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00 87 00 00 00 00 95 83 89 00 00 00 00 00 00 95 83 89 00 00 a5 a7 88
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
|
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00 87 00 00 00 00 87 2a 88 00 00 00 00 00 00 87 96 88 00 00 00 00 88
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00 87 00 00 00 00 87 2a 88 00 00 00 00 00 00 87 96 88 00 00 a5 a7 88
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
|
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00 87 00 00 00 00 8A 83 8B 00 00 00 00 00 00 8A 83 8B 00 00 00 00 88
|
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00 87 00 00 00 00 8A 83 8B 00 00 00 00 00 00 8A 83 8B 00 00 a5 a7 88
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
|
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00 87 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88
|
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00 87 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a5 a7 88
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
|
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00 87 00 00 00 00 AF AF AF AF AF AF AF AF AF AF AF AF 00 00 00 00 88
|
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00 87 00 00 00 00 AF AF AF AF AF AF AF AF AF AF AF AF 00 00 a5 a7 88
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
|
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00 87 00 00 00 8E 00 00 00 00 00 00 00 00 00 00 00 00 8D 00 00 00 88
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00 87 00 00 00 8E 00 00 00 00 00 00 00 00 00 00 00 00 8D 00 8c ba 88
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
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00 00 00 00 00 00 00 00 00
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@@ -49,4 +49,3 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@@ -1,6 +1,5 @@
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`timescale 1ns / 1ps
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module overlay #(
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parameter [23:0] RGB = 24'hFFFFFF
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) (
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@@ -23,7 +22,8 @@ module overlay #(
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input ena,
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input [24:0] max,
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input [24:0] pos
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input [24:0] pos,
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input [7:0] tape_data
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|
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);
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@@ -44,12 +44,19 @@ wire [7:0] chmap_data_out;
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|
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wire in_box = new_h > 'd8*'d5 && new_h < 'd8*('d24+'d3) && new_v > 'd8*1 && new_v < 'd8*'d12;
|
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|
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// height - 96-8 -> 84
|
||||
//
|
||||
// Mix the colors, we use the RGB constant, but we darken the background by shifting it right
|
||||
//
|
||||
assign o_r= ~ena | ~in_box ? i_r : (charmap_a ) ? RGB[23:16] : i_r >> 2;
|
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assign o_g= ~ena | ~in_box ? i_g : (charmap_a ) ? RGB[15:8] : i_g >> 2;
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assign o_b= ~ena | ~in_box ? i_b : (charmap_a ) ? RGB[7:0] : i_b >> 2;
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assign o_r = o_r_a | meter_red;
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wire [7:0] o_r_a;
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assign o_g = o_g_a | meter_green;
|
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wire [7:0] o_g_a;
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assign o_b = o_b_a | meter_blue;
|
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wire [7:0] o_b_a;
|
||||
assign o_r_a= ~ena | ~in_box ? i_r : (charmap_a ) ? RGB[23:16] : i_r >> 2;
|
||||
assign o_g_a= ~ena | ~in_box ? i_g : (charmap_a ) ? RGB[15:8] : i_g >> 2;
|
||||
assign o_b_a= ~ena | ~in_box ? i_b : (charmap_a ) ? RGB[7:0] : i_b >> 2;
|
||||
|
||||
reg [24:0] pos_r;
|
||||
reg [11:0] wr_addr;
|
||||
@@ -91,6 +98,7 @@ begin
|
||||
//
|
||||
if (pos!=pos_r)
|
||||
begin
|
||||
$display("pos: %d tape_data %x",pos,tape_data);
|
||||
//$display("pos: %d pos_r %d blocks %d inc_pos %d increment %d\n",pos,pos_r,blocks,inc_pos,increment);
|
||||
inc_pos<=inc_pos+25'd1;
|
||||
if (inc_pos==increment)
|
||||
@@ -163,8 +171,39 @@ begin
|
||||
state<=2'b00;
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//
|
||||
// some code to draw a waveform
|
||||
//
|
||||
reg [255:0] seq;
|
||||
wire [7:0] meter_red;
|
||||
wire [7:0] meter_green;
|
||||
wire [7:0] meter_blue;
|
||||
//assign color = ena & vcnt > 480-db[7:1] ? 8'h80 : 0;
|
||||
//255,127, - 84
|
||||
//
|
||||
// one line:
|
||||
//assign meter_green = ena & in_box & new_v == db[7:2] & new_v > 'd88 - db[7:2] & new_v > 'd40 ? 8'h80: 8'h00;
|
||||
//assign meter_red = ena & in_box & new_v == db[7:2] & new_v > 'd88 - db[7:2] & new_v < 'd60 ? 8'h80: 8'h00;
|
||||
|
||||
// bars:
|
||||
//assign meter_green = ena & in_box & new_v > 'd88 - db[7:2] & new_v > 'd40 ? 8'h80: 8'h00;
|
||||
//assign meter_red = ena & in_box & new_v > 'd88 - db[7:2] & new_v < 'd60 ? 8'h80: 8'h00;
|
||||
|
||||
// one white bar on right:
|
||||
assign meter_green = meter_blue;
|
||||
assign meter_red = meter_blue;
|
||||
assign meter_blue = ena & in_box & new_h > 'd195 & new_h < 'd204 & new_v > 'd88 - tape_data[7:2] & new_v < 'd80 ? 8'hFF: 8'h00;
|
||||
|
||||
//wire [6:0] idx = hcnt[10:4] - 7'd11;
|
||||
wire [6:0] idx = new_h[8:2] ;
|
||||
wire [7:0] db = seq >> { idx, 2'b0 };
|
||||
|
||||
always @(posedge i_pix)
|
||||
begin
|
||||
if (vcnt==0)
|
||||
seq <= { seq[247:0], tape_data};
|
||||
end
|
||||
|
||||
//
|
||||
|
||||
@@ -174,15 +174,16 @@ module screen_rotate
|
||||
|
||||
input rotate_ccw,
|
||||
input no_rotate,
|
||||
input flip,
|
||||
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output [11:0] FB_WIDTH,
|
||||
output [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output reg [11:0] FB_WIDTH,
|
||||
output reg [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
|
||||
output DDRAM_CLK,
|
||||
input DDRAM_BUSY,
|
||||
@@ -196,6 +197,8 @@ module screen_rotate
|
||||
|
||||
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
|
||||
|
||||
reg do_flip;
|
||||
|
||||
assign DDRAM_CLK = CLK_VIDEO;
|
||||
assign DDRAM_BURSTCNT = 1;
|
||||
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
|
||||
@@ -207,8 +210,6 @@ assign DDRAM_RD = 0;
|
||||
assign FB_EN = fb_en[2];
|
||||
assign FB_FORMAT = 5'b00110;
|
||||
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
|
||||
assign FB_WIDTH = vsz;
|
||||
assign FB_HEIGHT = hsz;
|
||||
assign FB_STRIDE = stride;
|
||||
|
||||
function [1:0] buf_next;
|
||||
@@ -220,6 +221,17 @@ function [1:0] buf_next;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
do_flip <= no_rotate && flip;
|
||||
if( do_flip ) begin
|
||||
FB_WIDTH <= hsz;
|
||||
FB_HEIGHT <= vsz;
|
||||
end else begin
|
||||
FB_WIDTH <= vsz;
|
||||
FB_HEIGHT <= hsz;
|
||||
end
|
||||
end
|
||||
|
||||
reg [1:0] i_fb,o_fb;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_vbl,old_vs;
|
||||
@@ -251,20 +263,23 @@ always @(posedge CLK_VIDEO) begin
|
||||
if(CE_PIXEL) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
|
||||
hcnt <= hcnt + 1'd1;
|
||||
if(~old_de & VGA_DE) begin
|
||||
hcnt <= 1;
|
||||
vcnt <= vcnt + 1'd1;
|
||||
end
|
||||
if(old_de & ~VGA_DE) hsz <= hcnt;
|
||||
if(old_de & ~VGA_DE) begin
|
||||
hsz <= hcnt;
|
||||
if( do_flip ) bwidth <= hcnt + 2'd3;
|
||||
end
|
||||
if(~old_vs & VGA_VS) begin
|
||||
vsz <= vcnt;
|
||||
bwidth <= vcnt + 2'd3;
|
||||
if( !do_flip ) bwidth <= vcnt + 2'd3;
|
||||
vcnt <= 0;
|
||||
fb_en <= {fb_en[1:0], ~no_rotate};
|
||||
fb_en <= {fb_en[1:0], ~no_rotate | flip};
|
||||
end
|
||||
if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
|
||||
if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -278,21 +293,25 @@ always @(posedge CLK_VIDEO) begin
|
||||
reg old_vs, old_de;
|
||||
|
||||
ram_wr <= 0;
|
||||
if(CE_PIXEL) begin
|
||||
if(CE_PIXEL && FB_EN) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
if(~old_vs & VGA_VS) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
|
||||
next_addr <=
|
||||
do_flip ? bufsize-3'd4 :
|
||||
rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
|
||||
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
|
||||
end
|
||||
if(VGA_DE) begin
|
||||
ram_wr <= 1;
|
||||
ram_data <= {VGA_B,VGA_G,VGA_R};
|
||||
ram_data <= {8'd0,VGA_B,VGA_G,VGA_R};
|
||||
ram_addr <= next_addr;
|
||||
next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
|
||||
next_addr <=
|
||||
do_flip ? next_addr-3'd4 :
|
||||
rotate_ccw ? (next_addr - stride) : (next_addr + stride);
|
||||
end
|
||||
if(old_de & ~VGA_DE) begin
|
||||
if(old_de & ~VGA_DE & ~do_flip) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
|
||||
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
|
||||
end
|
||||
|
||||
737
sys/ascal.vhd
737
sys/ascal.vhd
File diff suppressed because it is too large
Load Diff
@@ -24,13 +24,13 @@
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
//
|
||||
// WIDE=1 for 16 bit file I/O
|
||||
// VDNUM 1..4
|
||||
// VDNUM 1..10
|
||||
// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
|
||||
//
|
||||
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
|
||||
(
|
||||
input clk_sys,
|
||||
inout [45:0] HPS_BUS,
|
||||
inout [48:0] HPS_BUS,
|
||||
|
||||
// buttons up to 32
|
||||
output reg [31:0] joystick_0,
|
||||
@@ -41,12 +41,19 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
|
||||
output reg [31:0] joystick_5,
|
||||
|
||||
// analog -127..+127, Y: [15:8], X: [7:0]
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output reg [15:0] joystick_analog_2,
|
||||
output reg [15:0] joystick_analog_3,
|
||||
output reg [15:0] joystick_analog_4,
|
||||
output reg [15:0] joystick_analog_5,
|
||||
output reg [15:0] joystick_l_analog_0,
|
||||
output reg [15:0] joystick_l_analog_1,
|
||||
output reg [15:0] joystick_l_analog_2,
|
||||
output reg [15:0] joystick_l_analog_3,
|
||||
output reg [15:0] joystick_l_analog_4,
|
||||
output reg [15:0] joystick_l_analog_5,
|
||||
|
||||
output reg [15:0] joystick_r_analog_0,
|
||||
output reg [15:0] joystick_r_analog_1,
|
||||
output reg [15:0] joystick_r_analog_2,
|
||||
output reg [15:0] joystick_r_analog_3,
|
||||
output reg [15:0] joystick_r_analog_4,
|
||||
output reg [15:0] joystick_r_analog_5,
|
||||
|
||||
// paddle 0..255
|
||||
output reg [7:0] paddle_0,
|
||||
@@ -309,12 +316,17 @@ always@(posedge clk_sys) begin : uio_block
|
||||
'h0X17,
|
||||
'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
|
||||
'h29: io_dout <= {4'hA, stflg};
|
||||
'h2B: io_dout <= 1;
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
'h2B: io_dout <= {HPS_BUS[48:46],4'b0010};
|
||||
`else
|
||||
'h2B: io_dout <= {HPS_BUS[48:46],4'b0011};
|
||||
`endif
|
||||
'h2F: io_dout <= 1;
|
||||
'h32: io_dout <= gamma_bus[21];
|
||||
'h36: begin io_dout <= info_n; info_n <= 0; end
|
||||
'h39: io_dout <= 1;
|
||||
'h3C: if(upload_req) begin io_dout <= 1; upload_req <= 0; end
|
||||
'h3E: io_dout <= 1; // shadow mask
|
||||
endcase
|
||||
|
||||
sd_buff_addr <= 0;
|
||||
@@ -387,17 +399,17 @@ always@(posedge clk_sys) begin : uio_block
|
||||
io_dout <= sd_buff_din[sdn_ack];
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
// joystick left analog
|
||||
'h1a: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
|
||||
2: case(stick_idx)
|
||||
0: joystick_analog_0 <= io_din;
|
||||
1: joystick_analog_1 <= io_din;
|
||||
2: joystick_analog_2 <= io_din;
|
||||
3: joystick_analog_3 <= io_din;
|
||||
4: joystick_analog_4 <= io_din;
|
||||
5: joystick_analog_5 <= io_din;
|
||||
0: joystick_l_analog_0 <= io_din;
|
||||
1: joystick_l_analog_1 <= io_din;
|
||||
2: joystick_l_analog_2 <= io_din;
|
||||
3: joystick_l_analog_3 <= io_din;
|
||||
4: joystick_l_analog_4 <= io_din;
|
||||
5: joystick_l_analog_5 <= io_din;
|
||||
15: case(pdsp_idx)
|
||||
0: paddle_0 <= io_din[7:0];
|
||||
1: paddle_1 <= io_din[7:0];
|
||||
@@ -416,6 +428,21 @@ always@(posedge clk_sys) begin : uio_block
|
||||
endcase
|
||||
end
|
||||
|
||||
// joystick right analog
|
||||
'h3d: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: stick_idx <= io_din[3:0]; // first byte is joystick index
|
||||
2: case(stick_idx)
|
||||
0: joystick_r_analog_0 <= io_din;
|
||||
1: joystick_r_analog_1 <= io_din;
|
||||
2: joystick_r_analog_2 <= io_din;
|
||||
3: joystick_r_analog_3 <= io_din;
|
||||
4: joystick_r_analog_4 <= io_din;
|
||||
5: joystick_r_analog_5 <= io_din;
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
'h1c: begin
|
||||
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
|
||||
|
||||
@@ -5,11 +5,11 @@ module scanlines #(parameter v2=0)
|
||||
input [1:0] scanlines,
|
||||
input [23:0] din,
|
||||
input hs_in,vs_in,
|
||||
input de_in,
|
||||
input de_in,ce_in,
|
||||
|
||||
output reg [23:0] dout,
|
||||
output reg hs_out,vs_out,
|
||||
output reg de_out
|
||||
output reg de_out,ce_out
|
||||
);
|
||||
|
||||
reg [1:0] scanline;
|
||||
@@ -56,12 +56,13 @@ end
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [23:0] dout1, dout2;
|
||||
reg de1,de2,vs1,vs2,hs1,hs2;
|
||||
reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2;
|
||||
|
||||
dout <= dout2; dout2 <= dout1; dout1 <= d;
|
||||
vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in;
|
||||
hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in;
|
||||
de_out <= de2; de2 <= de1; de1 <= de_in;
|
||||
ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -7,6 +7,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) m
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
|
||||
|
||||
@@ -47,4 +47,4 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
|
||||
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
|
||||
|
||||
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"
|
||||
set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
|
||||
|
||||
@@ -295,7 +295,7 @@ reg [31:0] cfg_custom_p2;
|
||||
reg [4:0] vol_att;
|
||||
initial vol_att = 5'b11111;
|
||||
|
||||
reg [6:0] coef_addr;
|
||||
reg [9:0] coef_addr;
|
||||
reg [8:0] coef_data;
|
||||
reg coef_wr = 0;
|
||||
|
||||
@@ -336,6 +336,10 @@ always@(posedge clk_sys) begin
|
||||
old_strobe <= io_strobe;
|
||||
coef_wr <= 0;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
shadowmask_wr <= 0;
|
||||
`endif
|
||||
|
||||
if(~io_uio) begin
|
||||
has_cmd <= 0;
|
||||
cmd <= 0;
|
||||
@@ -363,6 +367,7 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cmd == 1) begin
|
||||
cfg <= io_din;
|
||||
cfg_set <= 1;
|
||||
@@ -370,7 +375,6 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
if(cmd == 'h20) begin
|
||||
cfg_set <= 0;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt<8) begin
|
||||
case(cnt[2:0])
|
||||
0: if(WIDTH != io_din[11:0]) WIDTH <= io_din[11:0];
|
||||
@@ -402,7 +406,6 @@ always@(posedge clk_sys) begin
|
||||
end
|
||||
end
|
||||
if(cmd == 'h2F) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt[3:0])
|
||||
0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
|
||||
1: LFB_BASE[15:0] <= io_din[15:0];
|
||||
@@ -419,12 +422,14 @@ always@(posedge clk_sys) begin
|
||||
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
|
||||
if(cmd == 'h26) vol_att <= io_din[4:0];
|
||||
if(cmd == 'h27) VSET <= io_din[11:0];
|
||||
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
|
||||
if(cmd == 'h2A) begin
|
||||
if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[8:0]};
|
||||
else coef_addr <= io_din[9:0];
|
||||
end
|
||||
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
|
||||
if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
|
||||
if(cmd == 'h38) vs_line <= io_din[11:0];
|
||||
if(cmd == 'h39) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt[3:0])
|
||||
0: acx_att <= io_din[4:0];
|
||||
1: aflt_rate[15:0] <= io_din;
|
||||
@@ -444,7 +449,6 @@ always@(posedge clk_sys) begin
|
||||
endcase
|
||||
end
|
||||
if(cmd == 'h3A) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt[3:0])
|
||||
0: arc1x <= io_din[12:0];
|
||||
1: arc1y <= io_din[12:0];
|
||||
@@ -452,6 +456,9 @@ always@(posedge clk_sys) begin
|
||||
3: arc2y <= io_din[12:0];
|
||||
endcase
|
||||
end
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din};
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
@@ -618,7 +625,7 @@ wire [15:0] vbuf_byteenable;
|
||||
wire vbuf_write;
|
||||
|
||||
wire [23:0] hdmi_data;
|
||||
wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
|
||||
wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
|
||||
wire freeze;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
@@ -634,6 +641,13 @@ ascal
|
||||
.PALETTE2("false"),
|
||||
`endif
|
||||
`endif
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
.ADAPTIVE("false"),
|
||||
`endif
|
||||
`ifdef MISTER_DOWNSCALE_NN
|
||||
.DOWNSCALE_NN("true"),
|
||||
`endif
|
||||
.FRAC(6),
|
||||
.N_DW(128),
|
||||
.N_AW(28)
|
||||
)
|
||||
@@ -667,6 +681,7 @@ ascal
|
||||
.o_vs (hdmi_vs),
|
||||
.o_de (hdmi_de),
|
||||
.o_vbl (hdmi_vbl),
|
||||
.o_brd (hdmi_brd),
|
||||
.o_lltune (lltune),
|
||||
.htotal (WIDTH + HFP + HBP + HS),
|
||||
.hsstart (WIDTH + HFP),
|
||||
@@ -1049,34 +1064,43 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c
|
||||
);
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire [23:0] hdmi_data_sl;
|
||||
wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
reg dis;
|
||||
dis <= fb_force_blank;
|
||||
dis <= fb_force_blank & ~LFB_EN;
|
||||
dis_output <= dis;
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
|
||||
scanlines #(1) HDMI_scanlines
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.cmd_wr(shadowmask_wr),
|
||||
.cmd_in(shadowmask_data),
|
||||
|
||||
.scanlines(scanlines),
|
||||
.din(dis_output ? 24'd0 : hdmi_data),
|
||||
.hs_in(hdmi_hs),
|
||||
.vs_in(hdmi_vs),
|
||||
.de_in(hdmi_de),
|
||||
|
||||
.dout(hdmi_data_sl),
|
||||
.hs_out(hdmi_hs_sl),
|
||||
.vs_out(hdmi_vs_sl),
|
||||
.de_out(hdmi_de_sl)
|
||||
.brd_in(hdmi_brd),
|
||||
.enable(~LFB_EN),
|
||||
|
||||
.dout(hdmi_data_mask),
|
||||
.hs_out(hdmi_hs_mask),
|
||||
.vs_out(hdmi_vs_mask),
|
||||
.de_out(hdmi_de_mask)
|
||||
);
|
||||
|
||||
wire [23:0] hdmi_data_osd;
|
||||
@@ -1091,10 +1115,10 @@ osd hdmi_osd
|
||||
.io_din(io_din),
|
||||
|
||||
.clk_video(clk_hdmi),
|
||||
.din(hdmi_data_sl),
|
||||
.hs_in(hdmi_hs_sl),
|
||||
.vs_in(hdmi_vs_sl),
|
||||
.de_in(hdmi_de_sl),
|
||||
.din(hdmi_data_mask),
|
||||
.hs_in(hdmi_hs_mask),
|
||||
.vs_in(hdmi_vs_mask),
|
||||
.de_in(hdmi_de_mask),
|
||||
|
||||
.dout(hdmi_data_osd),
|
||||
.hs_out(hdmi_hs_osd),
|
||||
@@ -1212,7 +1236,7 @@ assign HDMI_TX_D = hdmi_out_d;
|
||||
///////////////////////// VGA output //////////////////////////////////
|
||||
|
||||
wire [23:0] vga_data_sl;
|
||||
wire vga_de_sl, vga_vs_sl, vga_hs_sl;
|
||||
wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl;
|
||||
scanlines #(0) VGA_scanlines
|
||||
(
|
||||
.clk(clk_vid),
|
||||
@@ -1222,11 +1246,13 @@ scanlines #(0) VGA_scanlines
|
||||
.hs_in(hs_fix),
|
||||
.vs_in(vs_fix),
|
||||
.de_in(de_emu),
|
||||
.ce_in(ce_pix),
|
||||
|
||||
.dout(vga_data_sl),
|
||||
.hs_out(vga_hs_sl),
|
||||
.vs_out(vga_vs_sl),
|
||||
.de_out(vga_de_sl)
|
||||
.de_out(vga_de_sl),
|
||||
.ce_out(vga_ce_sl)
|
||||
);
|
||||
|
||||
wire [23:0] vga_data_osd;
|
||||
@@ -1461,13 +1487,13 @@ sync_fix sync_h(clk_vid, hs_emu, hs_fix);
|
||||
wire [6:0] user_out, user_in;
|
||||
|
||||
assign clk_ihdmi= clk_vid;
|
||||
assign ce_hpix = ce_pix;
|
||||
assign hr_out = r_out;
|
||||
assign hg_out = g_out;
|
||||
assign hb_out = b_out;
|
||||
assign hhs_fix = hs_fix;
|
||||
assign hvs_fix = vs_fix;
|
||||
assign hde_emu = de_emu;
|
||||
assign ce_hpix = vga_ce_sl;
|
||||
assign hr_out = vga_data_sl[23:16];
|
||||
assign hg_out = vga_data_sl[15:8];
|
||||
assign hb_out = vga_data_sl[7:0];
|
||||
assign hhs_fix = vga_hs_sl;
|
||||
assign hvs_fix = vga_vs_sl;
|
||||
assign hde_emu = vga_de_sl;
|
||||
|
||||
wire uart_dtr;
|
||||
wire uart_dsr;
|
||||
@@ -1504,11 +1530,15 @@ wire [13:0] fb_stride;
|
||||
assign fb_stride = 0;
|
||||
`endif
|
||||
|
||||
reg [1:0] sl_r;
|
||||
wire [1:0] sl = sl_r;
|
||||
always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines;
|
||||
|
||||
emu emu
|
||||
(
|
||||
.CLK_50M(FPGA_CLK2_50),
|
||||
.RESET(reset),
|
||||
.HPS_BUS({f1, HDMI_TX_VS,
|
||||
.HPS_BUS({fb_en, sl, f1, HDMI_TX_VS,
|
||||
clk_100m, clk_ihdmi,
|
||||
ce_hpix, hde_emu, hhs_fix, hvs_fix,
|
||||
io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
|
||||
|
||||
Reference in New Issue
Block a user