mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-04-19 03:04:19 +00:00
0f51aae7eb
- Added state management for audiomap usage - Added coding dependent sector playback delay - Basic seeking time simulation and constant data rate - Removed debugging option to disable MODE2 filters - Added a lot documentation about expectations of the CDIC to the code - Splitted off all audio playback into seperate file - Added DC bias filter to reduce pops between playbacks - Fixed wrong sample during underflow of FIFO - Added two sample delay for ADPCM Fixes frequent clicks and pops due to latency of ADPCM calculation - Buffer management now equal to CDIC emulation of MAME Uses internal bank switching to avoid ADPCM overwrite Stabilizes intro of "Zelda's Adventure" and "Hotel Mario" SCC68070: DMA support for transfer to CDIC memory Added additional test roms to verify the additions Known issues: - Hotel Mario hangs during score screen - Frog Feast hangs ingame
114 lines
1.9 KiB
NASM
114 lines
1.9 KiB
NASM
section .text
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org $400000
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vector:
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dc.l $1234
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dc.l main
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main:
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move.l #cdicirq,$200
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move #$2000,SR
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move.w #$2480,$303FFC ; IRQ vector
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move.w #$0023,$303C00 ; Command Register = Reset Mode 1
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move.w #$8000,$303FFE ; Data buffer
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move.w #$2480,$303FFC ; Interrupt Vector
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move.w #$0029,$303C00 ; Read Mode 1
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move.l #$0021600,$303C02 ; Time Register
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move.w #$8000,$303FFE ; Start the Read
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move.l #$2000,A3
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move.b #'O',$80002019
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jsr waitforirq
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move.b #'A',$80002019
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move.w $303FF6,d0
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move.w $303FF6,d0
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move.w $303FFE,d0
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; Check CDIC ram like the driver does
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move.w $300002,d0
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move.w $30000a,d0
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move.w $300a02,d0
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move.w $300a0a,d0
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move.b d0,$80004000 ; reset status
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move.l A3,$8000400c
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move.w #$498,$8000400a
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;move.w #$4,$8000400a
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move.b #$92,$80004005
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move.b #$80,$80004007 ; start DMA
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move.w #$8a00,$303FF8 ; DMA Control Register = Start Transmission at a00
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adda.l #$930,a3
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move.b #'B',$80002019
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move.w #$0000,$303FFE ; Data buffer = 0, disable reading
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move.w #800,d0
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jsr wait
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move.w #$0029,$303C00 ; Read Mode 1
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move.l #$0021600,$303C02 ; Time Register
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move.w #$8000,$303FFE ; Start the Read
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jsr waitforirq
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move.b #'A',$80002019
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move.w $303FF6,d0
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move.w $303FF6,d0
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move.w $303FFE,d0
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; Check CDIC ram like the driver does
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move.w $300002,d0
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move.w $30000a,d0
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move.w $300a02,d0
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move.w $300a0a,d0
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move.b d0,$80004000 ; reset status
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move.l A3,$8000400c
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move.w #$498,$8000400a
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;move.w #$4,$8000400a
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move.b #$92,$80004005
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move.b #$80,$80004007 ; start DMA
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move.w #$8a00,$303FF8 ; DMA Control Register = Start Transmission at a00
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adda.l #$930,a3
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move.b #'B',$80002019
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endless:
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bra endless
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wait:
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add #-1,d0
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bne wait
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rts
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waitforirq:
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move #0,d0
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waitforirqloop:
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cmp #0,d0
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beq waitforirqloop
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move.b #'O',$80002019
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rts
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cdicirq:
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move.b #'I',$80002019
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move.w $303FF4,d0 ; clear flags on ABUFD
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move.w $303FF6,d0 ; clear flags on XBUF
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;move.b #$92,$80004005
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move #1,d0
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rte
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