mirror of
https://github.com/MiSTer-devel/CDi_MiSTer.git
synced 2026-06-14 03:04:32 +00:00
04d4eba6dd
Partial revert of 1c41f27f
During combined ICA0 and ICA1 activity, memory access by CPU
was not possible for multiple lines.
309 lines
11 KiB
Systemverilog
309 lines
11 KiB
Systemverilog
`include "bus.svh"
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// ICA Image Control Area
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// Configures during VBLANK
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// DCA Dynamic Control Area
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// Configures during HBLANK
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// Limited to a maximum of 8 writes per line
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//`define DEBUG
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`define dp(statement) `ifdef DEBUG $display``statement `endif
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module ica_dca_ctrl (
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input clk,
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input reset,
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output bit [21:0] address,
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output bit as,
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input [15:0] din,
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input bus_ack,
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//output burst,
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input burstdata_valid,
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input dca_read,
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input hblank,
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input parity, // 1 for odd frame, 0 for even frame
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output [6:0] register_adr,
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output [23:0] register_data,
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output register_write,
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output reload_vsr,
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output [21:0] vsr,
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output bit irq,
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output display_parameters_s disp_params
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);
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parameter bit unit_index = 0;
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localparam bit [21:0] odd_ica_start = 22'h400;
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localparam bit [21:0] even_ica_start = 22'h404;
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bit [21:0] ica_pointer;
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bit [21:0] dca_pointer;
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bit [21:0] next_line_dca_pointer;
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bit [3:0] dca_burst_cnt;
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bit [31:0] instruction;
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bit [4:0] stall_cnt;
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enum bit [3:0] {
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IDLE,
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ICA_READ0,
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ICA_READ1,
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ICA_WAIT_FOR_ACK,
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ICA_EXECUTE,
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ICA_STALL,
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DCA_READ0,
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DCA_READ1,
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DCA_READ2,
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DCA_READ3
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} state;
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`ifdef VERILATOR
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string unit_name;
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initial begin
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$sformat(unit_name, "ICA%d", unit_index);
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end
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`endif
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assign register_adr = instruction[30:24];
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assign register_data = instruction[23:0];
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assign register_write = execute_instruction && instruction[31];
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assign vsr = instruction[21:0];
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assign reload_vsr = (execute_instruction && instruction[31:28] == 5) || (execute_instruction && ica_ended && instruction[31:28] == 4);
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always_ff @(posedge clk) begin
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if (register_write)
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`dp(("%s Write %x %x %b", unit_name, {1'b1, register_adr
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}, register_data, register_data));
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end
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bit ica_ended;
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bit dca_active;
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bit execute_instruction;
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// A high level indicates a DCA access was not aligned on a 64 bit boundary
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// We need to ignore the second instruction of the first and last burst to
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// fix this. Also we need one additional burst
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bit dca_misaligned;
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always_ff @(posedge clk) begin
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irq <= 0;
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disp_params.strobe <= 0;
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execute_instruction <= 0;
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if (reset) begin
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ica_pointer <= parity ? odd_ica_start : even_ica_start;
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as <= 0;
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state <= IDLE;
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ica_ended <= 0;
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dca_burst_cnt <= 0;
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dca_active <= 0;
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dca_misaligned <= 0;
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disp_params.cm <= 0;
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disp_params.mf <= kMosaicFactor2;
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disp_params.ft <= kBitmap;
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instruction <= 0;
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end else begin
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case (state)
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IDLE: begin
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if (!ica_ended) begin
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state <= ICA_READ0;
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address <= ica_pointer;
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// Read one instruction of 4 byte
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ica_pointer <= ica_pointer + 4;
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`dp(("ICA%d Start reading at %x", unit_index, ica_pointer));
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// check for alignment on 32 bit boundary
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assert (ica_pointer[1:0] == 0);
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as <= 1;
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end else if (dca_read) begin
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dca_active <= 1;
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// ICA has ended. Wait for hblanks to
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state <= DCA_READ0;
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as <= 1;
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address <= dca_pointer;
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// check at least for alignment on 32 bit boundary
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assert (dca_pointer[1:0] == 0);
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if (dca_pointer[2]) begin
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// This is bad. The access is not on a 64 bit boundary
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// Only use the first 2 words on the first and last burst
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// Also we need one more additional burst
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dca_pointer <= dca_pointer + 4;
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dca_burst_cnt <= 8;
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dca_misaligned <= 1;
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end else begin
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// We need to read 16 instructions from DCA
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// Always read in bursts of 4. This causes 2 instructions
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// per burst.
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// We need 8 bursts to complete the line
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dca_pointer <= dca_pointer + 8;
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dca_burst_cnt <= 7;
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dca_misaligned <= 0;
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end
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$sformat(unit_name, "DCA%d", unit_index);
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`dp(("DCA%d Start reading at %x", unit_index, dca_pointer));
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next_line_dca_pointer <= dca_pointer + 8 * 8;
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end
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end
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ICA_READ0: begin
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if (burstdata_valid) begin
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instruction[31:16] <= din;
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state <= ICA_READ1;
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end
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end
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ICA_READ1: begin
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if (burstdata_valid) begin
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instruction[15:0] <= din;
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state <= ICA_WAIT_FOR_ACK;
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execute_instruction <= 1;
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end
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end
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ICA_WAIT_FOR_ACK: begin
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if (bus_ack) begin
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as <= 0;
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state <= ICA_EXECUTE;
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end
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end
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ICA_EXECUTE: begin
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state <= ICA_STALL;
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end
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ICA_STALL: begin
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stall_cnt <= stall_cnt + 1;
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if (stall_cnt == 0) state <= IDLE;
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end
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DCA_READ0: begin
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if (burstdata_valid) begin
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instruction[31:16] <= din;
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state <= DCA_READ1;
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end
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end
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DCA_READ1: begin
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if (burstdata_valid) begin
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instruction[15:0] <= din;
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state <= DCA_READ2;
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execute_instruction <= dca_active;
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end
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end
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DCA_READ2: begin
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if (burstdata_valid) begin
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instruction[31:16] <= din;
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state <= DCA_READ3;
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end
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end
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DCA_READ3: begin
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if (burstdata_valid) begin
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instruction[15:0] <= din;
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if (dca_misaligned) begin
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// With DCA not aligned on 64 bit boundary, we must throw away the second word of the first and
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// the last burst
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execute_instruction <= dca_active && dca_burst_cnt != 8 && dca_burst_cnt != 0;
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end else begin
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execute_instruction <= dca_active;
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end
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if (dca_burst_cnt == 8)
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assert (dca_misaligned); // check for the simulation
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end
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if (bus_ack) begin
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if (dca_burst_cnt == 0 || !dca_active) begin
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state <= IDLE;
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dca_pointer <= next_line_dca_pointer;
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dca_active <= 0;
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as <= 0;
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end else begin
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state <= DCA_READ0;
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as <= 1;
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address <= dca_pointer;
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// `dp(("DCA%d Continue reading at %x", unit_index, dca_pointer);
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dca_pointer <= dca_pointer + 8;
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dca_burst_cnt <= dca_burst_cnt - 1;
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end
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end
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end
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default: begin
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end
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endcase
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if (execute_instruction) begin
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// `dp(("%s instruction %x", unit_name, instruction);
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case (instruction[31:28])
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0: begin
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// stop until next field
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ica_ended <= 1;
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`dp(("%s STOP", unit_name));
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dca_active <= 0;
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end
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1: begin
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// no operation
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// `dp(("%s NOP", unit_name));
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end
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2: begin
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// reload dcp
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if (ica_ended) begin
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`dp(("%s NOP (Reload DCP)", unit_name));
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end else begin
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dca_pointer <= instruction[21:0];
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`dp(("%s Reload DCP %x", unit_name, instruction[21:0]));
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end
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end
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3: begin
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// reload dcp and stop
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dca_pointer <= instruction[21:0];
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next_line_dca_pointer <= instruction[21:0];
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dca_active <= 0;
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ica_ended <= 1;
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`dp(("%s Reload DCP and STOP %x", unit_name, instruction[21:0]));
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end
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4: begin
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// reload ica pointer
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ica_pointer <= instruction[21:0];
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if (ica_ended) `dp(("%s Reload VSR %x", unit_name, instruction[21:0]));
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else `dp(("%s Reload ICA %x", unit_name, instruction[21:0]));
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end
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5: begin
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// reload vsr pointer and stop
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`dp(("%s Reload VSR and STOP %x", unit_name, instruction[21:0]));
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ica_ended <= 1;
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dca_active <= 0;
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end
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6: begin
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// interrupt
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`dp(("%s INTERRUPT", unit_name));
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irq <= 1;
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end
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7: begin
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// reload display parameters
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//assert(instruction[27]);
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//assert(!instruction[5]);
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if (instruction[27]) begin
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disp_params.cm <= instruction[4];
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disp_params.mf <= mosaic_factor_e'(instruction[3:2]);
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disp_params.ft <= file_type_e'(instruction[1:0]);
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disp_params.strobe <= 1;
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`dp(("%s RELOAD DISPLAY PARAMETERS %b", unit_name, instruction[4:0]));
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end
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end
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default: begin
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// no command but probably a register write
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end
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endcase
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end
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end
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end
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endmodule
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