MCD212: Improved accuracy of display active bit

- Seems to have no effect at all but is more cycle accurate.
- Also uses less FPGA resources

README.md

@@ -47,10 +47,10 @@ CD images can be stored as CHD or CUE/BIN format.
 
 Core Utilization:
 
-    Logic utilization (in ALMs)  22,527 / 41,910 ( 54 % )
-    Total registers              25524
+    Logic utilization (in ALMs)  22,424 / 41,910 ( 54 % )
+    Total registers              25036
     Total block memory bits      2,331,040 / 5,662,720 ( 41 % )
-    Total DSP Blocks             92 / 112 ( 82 % )
+    Total DSP Blocks             96 / 112 ( 86 % )
 
 Expected synthesis times with Quartus 17.0.2
 

rtl/ica_dca_ctrl.sv

@@ -171,7 +171,7 @@ module ica_dca_ctrl (
                     end
                 end
                 ICA_EXECUTE: begin
-                    state <= ICA_STALL;
+                    state <= IDLE;
                 end
                 ICA_STALL: begin
                     stall_cnt <= stall_cnt + 1;

rtl/mcd212.sv

@@ -215,12 +215,11 @@ module mcd212 (
     end
 `endif
 
-    wire display_active;
-
     always_comb begin
         status_register1 = 0;
+        status_register1.da = !vblank;
+
         // TODO This might not be accurate
-        status_register1.da = display_active;
         status_register1.pa = fake_parity;
     end
 
@@ -494,8 +493,7 @@ module mcd212 (
         .new_line(new_line),
         .new_pixel(new_pixel),
         .new_pixel_lores(new_pixel_lores),
-        .new_pixel_hires(new_pixel_hires),
-        .display_active(display_active)
+        .new_pixel_hires(new_pixel_hires)
     );
 
 

rtl/video_timing.sv

@@ -19,8 +19,7 @@ module video_timing (
     output bit new_line,
     output bit new_pixel,
     output bit new_pixel_hires,
-    output bit new_pixel_lores,
-    output bit display_active
+    output bit new_pixel_lores
 );
 
     localparam bit [12:0] ClksPerCycle = 16;
@@ -142,7 +141,6 @@ module video_timing (
     always_ff @(posedge clk) begin
         hblank <= !(video_x >= h_start && video_x < (h_start + h_active));
         vblank <= !(video_y >= v_start && video_y < (v_start + v_active));
-        display_active <= video_y >= v_start;
     end
 
     assign new_pixel_lores = video_x[1:0] == 1 && !hblank && !vblank;

sw/README.md

@@ -2,10 +2,13 @@
 
 This folder contains the firmware that drives the actual MPEG decoding inside the VMPEG replication.
 Since not much is known about the actual hardware, it is substituted with a hybrid approach of software and hardware.
-This project uses a modified port of the MPEG1 decoding library [pl_mpeg](https://github.com/phoboslab/pl_mpeg), augmented with FPGA based accelerators.
+This project uses a modified port of the MPEG1 decoding library [pl_mpeg](https://github.com/phoboslab/pl_mpeg), augmented with
+FPGA based accelerators.
 It is compiled for a RISC-V target via GCC to be executed on the [VexiiRiscv](https://github.com/SpinalHDL/VexiiRiscv) soft core.
 
-For MPEG1 video decoding, the pl_mpeg library is manually partitioned for running on multiple asymmetric cores. One VexiiRiscv is clocked at about 80 MHz to decode the MPEG bitstream. It creates commands for image manipulation and inserts them into a FIFO to grab by 2 identical worker cores, also running at 80 MHz.
+For MPEG1 video decoding, the pl_mpeg library is manually partitioned for running on multiple asymmetric cores.
+One VexiiRiscv is clocked at about 80 MHz to decode the MPEG bitstream. It creates commands for image manipulation
+and inserts them into a FIFO to grab by 2 identical worker cores, also running at 80 MHz.
 
 For MP2 audio decoding, a single VexiiRiscv at CD-i system frequency of 30 MHz is sufficient.