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106 lines
4.6 KiB
Markdown
106 lines
4.6 KiB
Markdown
# Memory of the CDi
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According to CDi 210 service manual: Two DRAM chips of 256K x 16
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This should indicate TD=0 acxcording to MCD212 datasheet.
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## Map
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Based on MCD212 datasheet and [mame source code](https://github.com/dankan1890/mewui/blob/master/src/mame/drivers/cdi.cpp).
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Also lots of info from [cdifan](https://github.com/cdifan/cdichips)
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0x000000 to 0x03ffff DRAM Bank 0 Lower 256kB -> MiSTer SDRAM 0x000000 to 0x03ffff
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0x040000 to 0x07ffff DRAM Bank 1 Lower 256kB -> MiSTer SDRAM 0x040000 to 0x07ffff
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0x200000 to 0x23ffff DRAM Bank 0 Upper 256kB -> MiSTer SDRAM 0x080000 to 0x0bffff
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0x240000 to 0x27ffff DRAM Bank 1 Upper 256kB -> MiSTer SDRAM 0x0C0000 to 0x0fffff
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According to MCD212 the DRAM goes until 0x3fffff. But this can't be true.
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I assume the ATTEX limits the DRAM to 0x27fffe as these do now follow.
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0x300000 to 0x303ffe CDIC
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0x310000 SLAVE
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0x320000 to 0x323fff NVRAM (according to mame)
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0x400000 to 0x4ffbff ROM but only 512kB so it ends 0x80000 -> MiSTer SDRAM 0x400000 to 0x47FFFF
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0x4ffc00 to 0x4fffdf MCD212 SystemIO (is this even used?)
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0x4fffe0 to 0x4fffff MCD212 according to MAME, channels 1+2 according to datasheet
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0xd00000 to 0xdfffff VMPEG System RAM (1MB) -> MiSTer SDRAM 0x100000 to 0x1fffff
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0xe00000 to 0xe01ffe VMPEG VCD pixel clock selection latch (mirrored a lot)
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0xe03000 to 0xe03024 VMPEG FMA (DSP56k via indirect access)
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0xe04000 to 0xe040f4 VMPEG FMV (MCD251)
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0xe40000 to 0xe5ffff VMPEG ROM (128K vmpega.rom) -> MiSTer SDRAM 0x480000
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0xe60000 to 0xe7ffff VMPEG ROM (mirrored)
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0xe80000 to 0xefffff VMPEG MCD251 Memory for Video decoding (512kB) -> MiSTer SDRAM 0x200000 to 0x27ffff
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0xf00000 to 0xf00068 Dummy player shell which starts a CD-i application (by CD-i Fan)
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## Bus Error
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Some locations are not mapped to memory and will cause a bus error exception on a CDI 210/05
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0x080000 to 0x1fffff
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0x500000 to 0xcfffff
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## CPU Internal
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0x80001001 LIR priority
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0x80002011 UART Mode
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0x80002013 UART Status
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0x80002015 UART Clock Select
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0x80002017 UART Command
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0x80002019 UART Transmit Holding
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0x8000201B UART Receive Holding
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0x80002020 Timer Status
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0x80002021 Timer Control
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0x80002022 Reload Register High
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0x80002023 Reload Register Low
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0x80002024 Timer 0 High
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0x80002025 Timer 0 Low
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0x80002026 Timer 1 High
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0x80002027 Timer 1 Low
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0x80002028 Timer 2 High
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0x80002029 Timer 2 Low
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0x80002045 PICR1
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0x80002047 PICR2
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0x80004000 DMA Channel 0 Status
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0x80004001 DMA Channel 0 Error
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0x80004004 DMA Channel 0 Device Control
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0x80004005 DMA Channel 0 Operation Control
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0x80004006 DMA Channel 0 Sequence Control
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0x80004007 DMA Channel 0 Channel Control
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0x8000400a DMA Channel 0 Memory Transfer Counter High
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0x8000400b DMA Channel 0 Memory Transfer Counter Low
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0x8000400c DMA Channel 0 Memory Address Counter High
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0x8000400d DMA Channel 0 Memory Address Counter
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0x8000400e DMA Channel 0 Memory Address Counter
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0x8000400f DMA Channel 0 Memory Address Counter Low
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0x80004014 DMA Channel 0 Device Address Counter High
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0x80004015 DMA Channel 0 Device Address Counter
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0x80004016 DMA Channel 0 Device Address Counter
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0x80004017 DMA Channel 0 Device Address Counter Low
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0x80004040 DMA Channel 1 Status
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0x80004041 DMA Channel 1 Error
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0x80004044 DMA Channel 1 Device Control
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0x80004045 DMA Channel 1 Operation Control
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0x80004046 DMA Channel 1 Sequence Control
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0x80004047 DMA Channel 1 Channel Control
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0x8000404a DMA Channel 1 Memory Transfer Counter High
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0x8000404b DMA Channel 1 Memory Transfer Counter Low
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0x8000404c DMA Channel 1 Memory Address Counter High
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0x8000404d DMA Channel 1 Memory Address Counter
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0x8000404e DMA Channel 1 Memory Address Counter
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0x8000404f DMA Channel 1 Memory Address Counter Low
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0x80004054 DMA Channel 1 Device Address Counter High
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0x80004055 DMA Channel 1 Device Address Counter
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0x80004056 DMA Channel 1 Device Address Counter
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0x80004057 DMA Channel 1 Device Address Counter Low
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## Auto refresh
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According to the datasheet of the SDRAM it is required to perform 8192 auto refresh cycles within 64ms.
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The CD-i connected to a TV has 64µs per scanline. This is standard for PAL and NTSC. This would indicate
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that 8-9 refresh cycles are required per scanline.
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Source: AllianceMemory_512M_SDRAM_Bdie_AS4C32M16SB_7TXN_6T-1826888.pdf
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