mirror of https://github.com/MiSTer-devel/CDi_MiSTer.git synced 2026-04-19 03:04:19 +00:00

Files

Andre Zeps ef6fcc9824 Removed git submodules

Copy of tg68k added to rtl subfolder

Also some cleanup on the READMEs

2025-06-12 21:41:05 +02:00

Verilator Simulation

Verilator is much faster than ModelSim but is restricted to Verilog/SystemVerilog. VHDL source code must be converted first.

Please use the convert scripts in case the VHDL code was changed. To be safe, a conversion is already part of the repo.

Prerequisites

You need CD images to use with the simulation. Only the .bin files are required. .chd is not supported.

./sim_top.sh