6 Commits

Author	SHA1	Message	Date
Andre Zeps	b9d9678654	moved generated code to verilator folder	2024-09-09 13:34:13 +02:00
Andre Zeps	d05f1fb295	Slave controller features ... - Added servo controller SPI fake communication Behaves as a closed but empty tray - Added pointing device emulation MiSTer joystick data used as input Behaves like a maneuvering device - Added SCI IRQ to 6805 cpu core - Added SPI and SCI to 6805 uC - Fixed spurious 68k chip select for slave - Added documentation about I2C to the Front LCD - Simulated U3090MG no longer causes front panel button presses Lead to spurious IRQs before - Removal of slave memory patches	2024-09-03 11:58:26 +02:00
Andre Zeps	74bff4c5ce	Removed slave rom from FPGA bitstream ... Added ioctl_download for slave rom boot0.rom is expected to be the main cpu rom boot1.rom is expected to be the slave rom	2024-08-18 20:02:33 +02:00
Andre Zeps	738bd44379	Boot fixes and video implementation ... - Attach display file and ICA to SDRAM - Fixed byte order of 8 bit accesses by CPU - Added SDRAM burst mode to fix video timing - Fixed missing reset behavior of some components - Added optional SDRAM zeroing - Added SDRAM refresh during ROM download - Added OS aware syscall parser to simulation - Fixed SCC68070 on-chip interrupt autovector - Fixed SCC68070 Timer0 frequency - Added video pixel data FIFO - Changed SDRAM auto refresh command	2024-08-17 22:32:51 +02:00
Andre Zeps	3cbdbea097	Added more comments to the code	2024-07-10 18:41:12 +02:00
Andre Zeps	b99ab86b09	First public release ... - SCC68070 is booting cdi200.rom - SLAVE is communicating with the CPU - MCD212 only implements memory map - IRQs incomplete - CDIC missing - MiSTer interface missing	2024-07-08 19:22:59 +02:00