T65: minor update for unification.

rtl/t65/T65.vhd

@@ -134,14 +134,16 @@ library IEEE;
 entity T65 is
   port(
     Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+    BCD_en  : in  std_logic := '1';             -- '0' => 2A03/2A07, '1' => others
+
     Res_n   : in  std_logic;
     Enable  : in  std_logic;
     Clk     : in  std_logic;
-    Rdy     : in  std_logic;
-    Abort_n : in  std_logic;
-    IRQ_n   : in  std_logic;
-    NMI_n   : in  std_logic;
-    SO_n    : in  std_logic;
+    Rdy     : in  std_logic := '1';
+    Abort_n : in  std_logic := '1';
+    IRQ_n   : in  std_logic := '1';
+    NMI_n   : in  std_logic := '1';
+    SO_n    : in  std_logic := '1';
     R_W_n   : out std_logic;
     Sync    : out std_logic;
     EF      : out std_logic;
@@ -157,7 +159,7 @@ entity T65 is
     -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
     Regs    : out std_logic_vector(63 downto 0);
     DEBUG   : out T_t65_dbg;
-    NMI_ack : out std_logic
+    NMI_ack : out std_logic
   );
 end T65;
 
@@ -183,6 +185,7 @@ architecture rtl of T65 is
   signal DO_r               : std_logic_vector(7 downto 0);
 
   signal Mode_r             : std_logic_vector(1 downto 0);
+  signal BCD_en_r           : std_logic;
   signal ALU_Op_r           : T_ALU_Op;
   signal Write_Data_r       : T_Write_Data;
   signal Set_Addr_To_r      : T_Set_Addr_To;
@@ -245,8 +248,8 @@ architecture rtl of T65 is
   signal NMI_entered    : std_logic;
 
 begin
-  NMI_ack <= NMIAct;
-
+  NMI_ack <= NMIAct;
+
   -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor 
   really_rdy <= Rdy or not(WRn_i);
   Sync <= '1' when MCycle = "000" else '0';
@@ -309,6 +312,7 @@ begin
   alu : entity work.T65_ALU
     port map(
       Mode => Mode_r,
+      BCD_en => BCD_en_r,
       Op => ALU_Op_r,
       BusA => BusA_r,
       BusB => BusB,
@@ -340,6 +344,7 @@ begin
       DBR <= (others => '0');
 
       Mode_r <= (others => '0');
+      BCD_en_r <= '1';
       ALU_Op_r <= ALU_OP_BIT;
       Write_Data_r <= Write_Data_DL;
       Set_Addr_To_r <= Set_Addr_To_PBR;
@@ -369,6 +374,7 @@ begin
 
           if MCycle  = "000" then
             Mode_r <= Mode;
+            BCD_en_r <= BCD_en;
 
             if IRQCycle = '0' and NMICycle = '0' then
               PC <= PC + 1;

rtl/t65/T65_ALU.vhd

@@ -57,6 +57,7 @@ use work.T65_Pack.all;
 entity T65_ALU is
   port(
     Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+    BCD_en  : in std_logic;
     Op      : in T_ALU_OP;
     BusA    : in std_logic_vector(7 downto 0);
     BusB    : in std_logic_vector(7 downto 0);
@@ -83,7 +84,7 @@ architecture rtl of T65_ALU is
 
 begin
 
-  process (P_In, BusA, BusB)
+  process (P_In, BusA, BusB, BCD_en)
     variable AL : unsigned(6 downto 0);
     variable AH : unsigned(6 downto 0);
     variable C : std_logic;
@@ -102,7 +103,7 @@ begin
       ADC_Z <= '0';
     end if;
 
-    if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+    if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
       AL(6 downto 1) := AL(6 downto 1) + 6;
     end if;
 
@@ -116,7 +117,7 @@ begin
       if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
 -- pragma translate_on
 
-    if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+    if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
       AH(6 downto 1) := AH(6 downto 1) + 6;
     end if;
 
@@ -125,7 +126,7 @@ begin
     ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
   end process;
 
-  process (Op, P_In, BusA, BusB)
+  process (Op, P_In, BusA, BusB, BCD_en)
     variable AL : unsigned(6 downto 0);
     variable AH : unsigned(5 downto 0);
     variable C : std_logic;
@@ -165,7 +166,7 @@ begin
 
     SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
 
-    if P_In(Flag_D) = '1' then
+    if P_In(Flag_D) = '1' and BCD_en = '1' then
       if AL(5) = '1' then
         AL(5 downto 1) := AL(5 downto 1) - 6;
       end if;
@@ -181,7 +182,7 @@ begin
   process (Op, P_In, BusA, BusB,
       ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
       SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
-		SBX_Q)
+      SBX_Q, BCD_en)
     variable Q_t : std_logic_vector(7 downto 0);
     variable Q2_t : std_logic_vector(7 downto 0);
   begin
@@ -226,7 +227,7 @@ begin
         Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
         P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
         Q2_t := Q_t;
-        if P_In(Flag_D)='1' then
+        if P_In(Flag_D)='1' and BCD_en = '1' then
           if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
             Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
           end if;

rtl/t65/T65_Pack.vhd

@@ -177,4 +177,4 @@ package body T65_Pack is
     end case;
   end CycleNext;
 
-end T65_Pack;
+end T65_Pack;