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10 lines
946 B
Plaintext
10 lines
946 B
Plaintext
{ "" "" "" "Ignored filter at sys_top.sdc(18): vip\|output_inst\|vid_clk could not be matched with a net" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored create_generated_clock at sys_top.sdc(17): Argument <targets> is an empty collection" { } { } 0 332049 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Ignored filter at sys_top.sdc(41): VID_CLK could not be matched with a clock" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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