mister-devel/Archie_MiSTer
1
0
Fork 0
mirror of https://github.com/MiSTer-devel/Archie_MiSTer.git synced 2026-04-19 03:04:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update sys.

Browse Source
This commit is contained in:
sorgelig
2019-09-27 15:31:11 +08:00
parent 375efeac24
commit bd1369fc3c
9 changed files with 258 additions and 283 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
sys/hdmi_config.sv
View File

@@ -24,19 +24,21 @@ wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [7:0] LUT_INDEX = 0;
i2c_master #(50_000_000, 20_000) i2c_av
i2c #(50_000_000, 20_000) i2c_av
(
.clk(iCLK),
.rst(~iRST_N),
.CLK(iCLK),
.i2c_scl(I2C_SCL), // I2C CLOCK
.i2c_sda(I2C_SDA), // I2C DATA
.I2C_SCL(I2C_SCL), // I2C CLOCK
.I2C_SDA(I2C_SDA), // I2C DATA
.addr(8'h39), // 0x39 is the Slave Address of the ADV7513 chip
.data_in(init_data[LUT_INDEX]),
.start(mI2C_GO), // START transfer
.ready(mI2C_END), // END transfer
.error(mI2C_ACK) // ACK
.I2C_ADDR('h39), // 0x39 is the Slave Address of the ADV7513 chip!
.I2C_WLEN(1),
.I2C_WDATA1(init_data[LUT_INDEX][15:8]), // SUB_ADDR
.I2C_WDATA2(init_data[LUT_INDEX][7:0]), // DATA
.START(mI2C_GO), // START transfer
.READ(0),
.END(mI2C_END), // END transfer
.ACK(mI2C_ACK) // ACK
);
////////////////////// Config Control ////////////////////////////

224
sys/i2c.v
View File

@@ -1,178 +1,94 @@
module i2c_master
module i2c
(
input clk,
input rst,
input [6:0] addr,
input [15:0] data_in,
input start,
input rw,
input CLK,
output reg error,
output reg [7:0] data_out,
output reg ready,
input START,
input READ,
input [6:0] I2C_ADDR,
input I2C_WLEN, // 0 - one byte, 1 - two bytes
input [7:0] I2C_WDATA1,
input [7:0] I2C_WDATA2,
output [7:0] I2C_RDATA,
output reg END = 1,
output reg ACK = 0,
inout i2c_sda,
output i2c_scl
//I2C bus
output I2C_SCL,
inout I2C_SDA
);
// Clock Setting
parameter CLK_Freq = 50_000_000; // 50 MHz
parameter I2C_Freq = 400_000; // 400 KHz
localparam IDLE = 0;
localparam START = 1;
localparam ADDRESS = 2;
localparam READ_ACK = 3;
localparam WRITE_DATA = 4;
localparam WRITE_DATA2 = 5;
localparam WRITE_ACK = 6;
localparam READ_DATA = 7;
localparam READ_ACK2 = 8;
localparam READ_ACK3 = 9;
localparam STOP = 10;
localparam STOP2 = 11;
localparam I2C_FreqX2 = I2C_Freq*2;
localparam I2C_Rate = CLK_Freq/(I2C_Freq*2);
reg I2C_CLOCK;
reg [31:0] cnt;
wire [31:0] cnt_next = cnt + I2C_FreqX2;
assign i2c_scl = scl_disable | i2c_clk;
assign i2c_sda = ~sda_out ? 1'b0 : 1'bz;
reg i2c_clk;
reg i2c_clk_d;
always@(posedge clk) begin
integer div = 0;
if(div < I2C_Rate) begin
div <= div + 1;
end else begin
div <= 0;
i2c_clk <= ~i2c_clk;
always @(posedge CLK) begin
cnt <= cnt_next;
if(cnt_next >= CLK_Freq) begin
cnt <= cnt_next - CLK_Freq;
I2C_CLOCK <= ~I2C_CLOCK;
end
i2c_clk_d <= i2c_clk;
end
reg sda_out = 1;
reg scl_disable = 0;
assign I2C_SCL = SCLK | I2C_CLOCK;
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
always @(posedge clk, posedge rst) begin
reg [3:0] state;
reg [7:0] saved_addr;
reg [7:0] saved_data1;
reg [7:0] saved_data2;
reg [2:0] counter;
reg old_st;
reg SCLK = 1;
reg [3:0] SDO = 4'b1111;
reg [0:7] rdata;
if(rst) begin
state <= IDLE;
scl_disable <= 1;
sda_out <= 1;
ready <= 0;
end
else begin
if(i2c_clk & ~i2c_clk_d) begin
old_st <= start;
assign I2C_RDATA = rdata;
case(state)
IDLE: begin
ready <= 1;
if (~old_st & start) begin
state <= START;
saved_addr <= {addr, rw};
{saved_data1,saved_data2} <= data_in;
error <= 0;
ready <= 0;
end
end
always @(posedge CLK) begin
reg old_clk;
reg old_st;
reg rd,len;
START: begin
scl_disable <= 0;
counter <= 7;
state <= ADDRESS;
end
reg [5:0] SD_COUNTER = 'b111111;
reg [0:31] SD;
ADDRESS: begin
if (counter == 0) begin
state <= READ_ACK;
end else counter <= counter - 1'd1;
end
old_clk <= I2C_CLOCK;
old_st <= START;
// delay to make sure SDA changed while SCL is stabilized at low
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
SDO[3:1] <= SDO[2:0];
READ_ACK: begin
if (i2c_sda == 0) begin
counter <= 7;
if(saved_addr[0] == 0) state <= WRITE_DATA;
else state <= READ_DATA;
end
else begin
state <= STOP;
error <= 1;
end
end
WRITE_DATA: begin
if(counter == 0) begin
state <= READ_ACK2;
end else counter <= counter - 1'd1;
end
READ_ACK2: begin
if (i2c_sda == 0) begin
state <= WRITE_DATA2;
counter <= 7;
end
else begin
state <= STOP;
error <= 1;
end
end
WRITE_DATA2: begin
if(counter == 0) state <= READ_ACK3;
else counter <= counter - 1'd1;
end
READ_ACK3: begin
if (i2c_sda == 0) state <= STOP;
else begin
state <= STOP;
error <= 1;
end
end
READ_DATA: begin
data_out[counter] <= i2c_sda;
if (counter == 0) state <= WRITE_ACK;
else counter <= counter - 1'd1;
end
WRITE_ACK: begin
state <= STOP;
end
STOP: begin
scl_disable <= 1;
state <= STOP2;
end
STOP2: begin
state <= IDLE;
end
if(~old_st && START) begin
SCLK <= 1;
SDO <= 4'b1111;
ACK <= 0;
END <= 0;
rd <= READ;
len <= I2C_WLEN;
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
SD_COUNTER <= 0;
end else begin
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
SD_COUNTER <= SD_COUNTER + 6'd1;
case(SD_COUNTER)
01: SCLK <= 0;
10: ACK <= ACK | I2C_SDA;
19: if(~rd) begin
ACK <= ACK | I2C_SDA;
if(~len) SD_COUNTER <= 29;
end
20: if(rd) SCLK <= 1;
23: if(rd) END <= 1;
28: if(~rd) ACK <= ACK | I2C_SDA;
29: if(~rd) SCLK <= 1;
32: if(~rd) END <= 1;
endcase
end
if(~i2c_clk & i2c_clk_d) begin
case(state)
START: sda_out <= 0;
ADDRESS: sda_out <= saved_addr[counter];
READ_ACK: sda_out <= 1;
READ_ACK2: sda_out <= 1;
READ_ACK3: sda_out <= 1;
WRITE_DATA: sda_out <= saved_data1[counter];
WRITE_DATA2: sda_out <= saved_data2[counter];
WRITE_ACK: sda_out <= 0;
READ_DATA: sda_out <= 1;
STOP: sda_out <= 0;
STOP2: sda_out <= 1;
endcase
if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
end
end
end

27
sys/mcp23009.sv
View File

@@ -22,21 +22,20 @@ reg rw;
wire [7:0] dout;
reg [15:0] din;
i2c_master #(50_000_000, 500_000) i2c
i2c #(50_000_000, 500_000) i2c
(
.clk(clk),
.rst(0),
.addr('h20),
.data_in(din),
.start(start),
.rw(rw),
.error(error),
.data_out(dout),
.ready(ready),
.i2c_sda(sda),
.i2c_scl(scl)
.CLK(clk),
.START(start),
.READ(rw),
.I2C_ADDR('h20),
.I2C_WLEN(1),
.I2C_WDATA1(din[15:8]),
.I2C_WDATA2(din[7:0]),
.I2C_RDATA(dout),
.END(ready),
.ACK(error),
.I2C_SCL(scl),
.I2C_SDA(sda)
);
always@(posedge clk) begin

41
sys/osd.v
View File

@@ -4,16 +4,20 @@
module osd
(
input clk_sys,
input io_osd,
input io_strobe,
input [15:0] io_din,
input clk_video,
input [23:0] din,
output [23:0] dout,
input de_in,
input vs_in,
input hs_in,
output [23:0] dout,
output reg de_out,
output reg vs_out,
output reg hs_out,
output reg osd_status
);
@@ -212,19 +216,30 @@ end
reg [23:0] rdout;
assign dout = rdout;
reg [23:0] osd_rdout, normal_rdout;
reg osd_mux;
reg de_dly;
always @(posedge clk_video) begin
normal_rdout <= din;
osd_rdout <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0
reg [23:0] ordout1, nrdout1, rdout2, rdout3;
reg de1,de2,de3;
reg osd_mux;
reg vs1,vs2,vs3;
reg hs1,hs2,hs3;
nrdout1 <= din;
ordout1 <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0
osd_mux <= ~osd_de[2];
rdout <= osd_mux ? normal_rdout : osd_rdout;
de_dly <= de_in;
de_out <= de_dly;
rdout2 <= osd_mux ? nrdout1 : ordout1;
rdout3 <= rdout2;
de1 <= de_in; de2 <= de1; de3 <= de2;
hs1 <= hs_in; hs2 <= hs1; hs3 <= hs2;
vs1 <= vs_in; vs2 <= vs1; vs3 <= vs2;
rdout <= rdout3;
de_out <= de3;
hs_out <= hs3;
vs_out <= vs3;
end
endmodule

47
sys/scanlines.v
View File

@@ -1,52 +1,67 @@
module scanlines #(parameter v2=0)
(
input clk,
input clk,
input [1:0] scanlines,
input [23:0] din,
input hs_in,vs_in,
input de_in,
output reg [23:0] dout,
input hs,vs
output reg hs_out,vs_out,
output reg de_out
);
reg [1:0] scanline;
always @(posedge clk) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
old_hs <= hs_in;
old_vs <= vs_in;
if(old_hs && ~hs) begin
if(old_hs && ~hs_in) begin
if(v2) begin
scanline <= scanline + 1'd1;
if (scanline == scanlines) scanline <= 0;
end
else scanline <= scanline ^ scanlines;
end
if(old_vs && ~vs) scanline <= 0;
if(old_vs && ~vs_in) scanline <= 0;
end
wire [7:0] r,g,b;
assign {r,g,b} = din;
reg [23:0] d;
always @(*) begin
case(scanline)
1: // reduce 25% = 1/2 + 1/4
dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
{1'b0, g[7:1]} + {2'b00, g[7:2]},
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
d = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
{1'b0, g[7:1]} + {2'b00, g[7:2]},
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
2: // reduce 50% = 1/2
dout = {{1'b0, r[7:1]},
{1'b0, g[7:1]},
{1'b0, b[7:1]}};
d = {{1'b0, r[7:1]},
{1'b0, g[7:1]},
{1'b0, b[7:1]}};
3: // reduce 75% = 1/4
dout = {{2'b00, r[7:2]},
{2'b00, g[7:2]},
{2'b00, b[7:2]}};
d = {{2'b00, r[7:2]},
{2'b00, g[7:2]},
{2'b00, b[7:2]}};
default: dout = {r,g,b};
default: d = {r,g,b};
endcase
end
always @(posedge clk) begin
reg [23:0] dout1, dout2;
reg de1,de2,vs1,vs2,hs1,hs2;
dout <= dout2; dout2 <= dout1; dout1 <= d;
vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in;
hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in;
de_out <= de2; de2 <= de1; de1 <= de_in;
end
endmodule

1
sys/sys.tcl
View File

@@ -245,6 +245,7 @@ set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"

36
sys/sys_top.sdc
View File

@@ -3,7 +3,7 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period 10.0ns [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
@@ -14,26 +14,24 @@ create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
set_clock_groups -exclusive \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
-group [get_clocks { FPGA_CLK1_50 }] \
-group [get_clocks { FPGA_CLK2_50 }] \
-group [get_clocks { FPGA_CLK3_50 }]
set_output_delay -max -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -max -clock HDMI_CLK 4.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *
# Put constraints on output ports
set_false_path -from * -to [get_ports {LED_*}]
set_false_path -from * -to [get_ports {VGA_*}]
set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
set_false_path -from * -to [get_ports {AUDIO_L}]
set_false_path -from * -to [get_ports {AUDIO_R}]
set_false_path -from * -to [get_keepers {cfg[*]}]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -to {wcalc[*] hcalc[*]}

134
sys/sys_top.v
View File

@@ -102,7 +102,7 @@ module sys_top
output SD_SPI_MOSI,
inout SDCD_SPDIF,
inout IO_SCL,
output IO_SCL,
inout IO_SDA,
////////// ADC //////////////
@@ -441,7 +441,7 @@ always @(posedge FPGA_CLK2_50) begin
end
wire clk_100m;
wire clk_hdmi = ~hdmi_tx_clk; // Internal HDMI clock, inverted in relation to external clock
wire clk_hdmi = ~hdmi_clk_out; // Internal HDMI clock, inverted in relation to external clock
wire clk_audio = FPGA_CLK3_50;
wire clk_pal = FPGA_CLK3_50;
@@ -506,7 +506,9 @@ wire [127:0] vbuf_writedata;
wire [15:0] vbuf_byteenable;
wire vbuf_write;
wire hdmi_vs, hdmi_hs;
wire [23:0] hdmi_data;
wire hdmi_vs, hdmi_hs, hdmi_de;
ascal
#(
.RAMBASE(32'h20000000),
@@ -524,10 +526,10 @@ ascal
.i_r (r_out),
.i_g (g_out),
.i_b (b_out),
.i_hs (hs),
.i_vs (vs),
.i_hs (hs_fix),
.i_vs (vs_fix),
.i_fl (f1),
.i_de (de),
.i_de (de_emu),
.iauto (1),
.himin (0),
.himax (0),
@@ -698,14 +700,14 @@ fbpal fbpal
///////////////////////// HDMI output /////////////////////////////////
wire hdmi_tx_clk;
wire hdmi_clk_out;
pll_hdmi pll_hdmi
(
.refclk(FPGA_CLK1_50),
.rst(reset_req),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.outclk_0(hdmi_tx_clk)
.outclk_0(hdmi_clk_out)
);
//1920x1080@60 PCLK=148.5MHz CEA
@@ -788,23 +790,27 @@ hdmi_config hdmi_config
.ypbpr(ypbpr_en & direct_video)
);
wire [23:0] hdmi_data;
wire [23:0] hdmi_data_sl;
wire hdmi_de;
wire [23:0] hdmi_data_sl;
wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;
scanlines #(1) HDMI_scanlines
(
.clk(clk_hdmi),
.scanlines(scanlines),
.din(hdmi_data),
.hs_in(hdmi_hs),
.vs_in(hdmi_vs),
.de_in(hdmi_de),
.dout(hdmi_data_sl),
.hs(HDMI_TX_HS),
.vs(HDMI_TX_VS)
.hs_out(hdmi_hs_sl),
.vs_out(hdmi_vs_sl),
.de_out(hdmi_de_sl)
);
wire [23:0] hdmi_tx_d;
wire hdmi_tx_de;
wire [23:0] hdmi_data_osd;
wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
osd hdmi_osd
(
.clk_sys(clk_sys),
@@ -815,14 +821,19 @@ osd hdmi_osd
.clk_video(clk_hdmi),
.din(hdmi_data_sl),
.dout(hdmi_tx_d),
.de_in(hdmi_de),
.de_out(hdmi_tx_de),
.hs_in(hdmi_hs_sl),
.vs_in(hdmi_vs_sl),
.de_in(hdmi_de_sl),
.dout(hdmi_data_osd),
.hs_out(hdmi_hs_osd),
.vs_out(hdmi_vs_osd),
.de_out(hdmi_de_osd),
.osd_status(osd_status)
);
reg [23:0] dv_d;
reg [23:0] dv_data;
reg dv_hs, dv_vs, dv_de;
always @(negedge clk_vid) begin
reg [23:0] dv_d1, dv_d2;
@@ -833,58 +844,64 @@ always @(negedge clk_vid) begin
reg [3:0] hss;
if(ce_pix) begin
hss <= (hss << 1) | hs;
hss <= (hss << 1) | vga_hs_osd;
old_hs <= hs;
if(~old_hs && hs) begin
old_vs <= vs;
old_hs <= vga_hs_osd;
if(~old_hs && vga_hs_osd) begin
old_vs <= vga_vs_osd;
if(~&vcnt) vcnt <= vcnt + 1'd1;
if(~old_vs & vs & ~f1) vsz <= vcnt;
if(old_vs & ~vs) vcnt <= 0;
if(~old_vs & vga_vs_osd & ~f1) vsz <= vcnt;
if(old_vs & ~vga_vs_osd) vcnt <= 0;
if(vcnt == 1) vde <= 1;
if(vcnt == vsz - 3) vde <= 0;
end
dv_de1 <= !{hss,hs} && vde;
dv_hs1 <= csync_en ? cs : hs;
dv_vs1 <= vs;
dv_de1 <= !{hss,vga_hs_osd} && vde;
dv_hs1 <= csync_en ? vga_cs_osd : vga_hs_osd;
dv_vs1 <= vga_vs_osd;
end
dv_d1 <= vga_q;
dv_d1 <= vga_data_osd;
dv_d2 <= dv_d1;
dv_de2 <= dv_de1;
dv_hs2 <= dv_hs1;
dv_vs2 <= dv_vs1;
dv_d <= dv_d2;
dv_data<= dv_d2;
dv_de <= dv_de2;
dv_hs <= dv_hs2;
dv_vs <= dv_vs2;
end
assign HDMI_TX_CLK = direct_video ? clk_vid : hdmi_tx_clk;
assign HDMI_TX_HS = direct_video ? dv_hs : hdmi_hs ;
assign HDMI_TX_VS = direct_video ? dv_vs : hdmi_vs ;
assign HDMI_TX_D = direct_video ? dv_d : hdmi_tx_d ;
assign HDMI_TX_DE = direct_video ? dv_de : hdmi_tx_de ;
assign HDMI_TX_CLK = direct_video ? clk_vid : hdmi_clk_out;
assign HDMI_TX_HS = direct_video ? dv_hs : hdmi_hs_osd;
assign HDMI_TX_VS = direct_video ? dv_vs : hdmi_vs_osd;
assign HDMI_TX_DE = direct_video ? dv_de : hdmi_de_osd;
assign HDMI_TX_D = direct_video ? dv_data : hdmi_data_osd;
///////////////////////// VGA output //////////////////////////////////
wire [23:0] vga_data_sl;
wire vga_de_sl, vga_vs_sl, vga_hs_sl;
scanlines #(0) VGA_scanlines
(
.clk(clk_vid),
.scanlines(scanlines),
.din(de ? {r_out, g_out, b_out} : 24'd0),
.din(de_emu ? {r_out, g_out, b_out} : 24'd0),
.hs_in(hs_fix),
.vs_in(vs_fix),
.de_in(de_emu),
.dout(vga_data_sl),
.hs(hs),
.vs(vs)
.hs_out(vga_hs_sl),
.vs_out(vga_vs_sl),
.de_out(vga_de_sl)
);
wire [23:0] vga_q;
wire [23:0] vga_data_osd;
wire vga_vs_osd, vga_hs_osd;
osd vga_osd
(
.clk_sys(clk_sys),
@@ -895,12 +912,17 @@ osd vga_osd
.clk_video(clk_vid),
.din(vga_data_sl),
.dout(vga_q),
.de_in(de)
.hs_in(vga_hs_sl),
.vs_in(vga_vs_sl),
.de_in(vga_de_sl),
.dout(vga_data_osd),
.hs_out(vga_hs_osd),
.vs_out(vga_vs_osd)
);
wire cs;
csync csync_vga(clk_vid, hs, vs, cs);
wire vga_cs_osd;
csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
`ifndef DUAL_SDRAM
wire [23:0] vga_o;
@@ -909,15 +931,15 @@ csync csync_vga(clk_vid, hs, vs, cs);
.ypbpr_full(0),
.ypbpr_en(ypbpr_en),
.dout(vga_o),
.din(vga_scaler ? {24{hdmi_tx_de}} & hdmi_tx_d : vga_q)
.din(vga_scaler ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
);
wire hdmi_cs;
csync csync_hdmi(clk_hdmi, hdmi_hs, hdmi_vs, hdmi_cs);
wire hdmi_cs_osd;
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
wire vs1 = vga_scaler ? hdmi_vs : vs;
wire hs1 = vga_scaler ? hdmi_hs : hs;
wire cs1 = vga_scaler ? hdmi_cs : cs;
wire vs1 = vga_scaler ? hdmi_vs_osd : vga_vs_osd;
wire hs1 = vga_scaler ? hdmi_hs_osd : vga_hs_osd;
wire cs1 = vga_scaler ? hdmi_cs_osd : vga_cs_osd;
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1;
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1;
@@ -1047,7 +1069,7 @@ wire [15:0] audio_ls, audio_rs;
wire audio_s;
wire [1:0] audio_mix;
wire [7:0] r_out, g_out, b_out;
wire vs, hs, de, f1;
wire vs_fix, hs_fix, de_emu, f1;
wire [1:0] scanlines;
wire clk_sys, clk_vid, ce_pix;
@@ -1068,8 +1090,8 @@ wire [1:0] led_disk;
wire [1:0] btn;
wire vs_emu, hs_emu;
sync_fix sync_v(clk_vid, vs_emu, vs);
sync_fix sync_h(clk_vid, hs_emu, hs);
sync_fix sync_v(clk_vid, vs_emu, vs_fix);
sync_fix sync_h(clk_vid, hs_emu, hs_fix);
wire uart_dtr;
wire uart_dsr;
@@ -1083,9 +1105,9 @@ wire [6:0] user_out, user_in;
emu emu
(
.CLK_50M(FPGA_CLK3_50),
.CLK_50M(FPGA_CLK2_50),
.RESET(reset),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de_emu, hs_fix, vs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
@@ -1095,7 +1117,7 @@ emu emu
.VGA_B(b_out),
.VGA_HS(hs_emu),
.VGA_VS(vs_emu),
.VGA_DE(de),
.VGA_DE(de_emu),
.VGA_F1(f1),
.VGA_SL(scanlines),

9
sys/video_cleaner.sv
View File

@@ -23,6 +23,9 @@ module video_cleaner
input HBlank,
input VBlank,
//optional de
input DE_in,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
@@ -33,7 +36,10 @@ module video_cleaner
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out
output reg VBlank_out,
// optional aligned de
output reg DE_out
);
wire hs, vs;
@@ -55,6 +61,7 @@ always @(posedge clk_vid) begin
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
DE_out <= DE_in;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end