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2025-12-09 11:48:48 +08:00
2025-12-09 11:48:48 +08:00
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2021-03-25 17:20:34 +01:00
2024-05-25 10:08:07 -04:00
2021-03-25 17:20:34 +01:00
2021-03-25 17:20:34 +01:00
2025-12-09 11:48:48 +08:00
2021-03-16 12:14:03 +01:00
2021-03-25 17:20:34 +01:00
2021-03-16 12:14:03 +01:00
2021-03-25 17:20:34 +01:00
2021-06-15 05:54:18 -04:00

U.S. Championship V'ball

This is the emulation of V'Ball from Technos Japan ported to MiSTerFPGA by Pierre Cornier (Pierco). The core uses SDRAM for background tiles & DDRAM for PCM data, loaded automagically from mra.

The default joystick mapping is:

Name Button
Coin A R2
Coin B L2
Jump B
Action A
Start Start

Games provided

  • U.S. Championship V'ball (US)
  • U.S. Championship V'ball (Bootleg of US set)

DIP-Switches

  • Difficulty
  • Single Player Game Time
  • Start Buttons (4-player)
  • Rotate Players 1 & 4
  • Player Mode (2/4)
  • Coin A (coins/credits)
  • Coin B (coins/credits)
  • Flip Screen
  • Demo Sounds

I would like to thank Alan Steremberg, ElectronAsh, David Shadoff & Chockichoc for their help and support.

Description
This is a port of V'Ball for MiSTer FPGA
Readme GPL-2.0 11 MiB
Languages
Verilog 63.3%
VHDL 23.2%
SystemVerilog 11.7%
Tcl 1.7%