working

rtl/snd/fm.vhd

@@ -42,6 +42,7 @@ entity fm is
   port (
     reset : in std_logic;
     clk   : in std_logic;
+    cen   : in std_logic;
 
     addr : in std_logic;
     din  : in std_logic_vector(7 downto 0);
@@ -80,7 +81,7 @@ begin
   port map (
     rst => reset,
     clk => clk,
-    cen => '1',
+    cen => cen,
 
     din  => din,
     dout => dout,

rtl/snd/snd.vhd

@@ -56,6 +56,7 @@ entity snd is
     -- clock signals
     clk     : in std_logic;
     cen_4   : in std_logic;
+    cen_50  : in std_logic;
     cen_384 : in std_logic;
 
     -- memory map
@@ -158,6 +159,7 @@ begin
   port map (
     reset  => reset,
     clk    => clk,
+    cen    => cen_4,
     irq_n  => cpu_int_n,
     cs     => fm_cs,
     addr   => cpu_addr(0),

rtl/tecmo.vhd

@@ -54,6 +54,7 @@ entity tecmo is
     clk     : in std_logic;
     cen_6   : buffer std_logic; -- 6MHz
     cen_4   : buffer std_logic; -- 4MHz
+    cen_50  : buffer std_logic; -- 50KHz
     cen_384 : buffer std_logic; -- 384KHz
 
     -- debug mode
@@ -230,6 +231,11 @@ begin
   generic map (DIVISOR => natural(CLK_FREQ/4.0))
   port map (clk => clk, cen => cen_4);
 
+  -- generate a 50KHz clock enable signal
+  clock_divider_50 : entity work.clock_divider
+  generic map (DIVISOR => natural(CLK_FREQ/0.5))
+  port map (clk => clk, cen => cen_50);
+
   -- generate a 384KHz clock enable signal
   clock_divider_384 : entity work.clock_divider
   generic map (DIVISOR => natural(CLK_FREQ/0.384))
@@ -409,6 +415,7 @@ begin
     -- clock signals
     clk     => clk,
     cen_4   => cen_4,
+    cen_50  => cen_50,
     cen_384 => cen_384,
 
     -- configuration