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Merge pull request #3 from alanswx/master

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new sys, new release
This commit is contained in:
MiSTer-X
2021-01-18 09:13:58 +09:00
committed by GitHub
parent a8a5707fa2 9db93eb3fd
commit 177a635e99
67 changed files with 7826 additions and 6227 deletions
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120
Arcade-SolomonsKey.qsf
View File

@@ -1,61 +1,61 @@
# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name SEED 1
#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1"
#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1"
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER OFF
# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
set_global_assignment -name SEED 1
set_global_assignment -name VERILOG_MACRO "ARCADE_SYS=1"
set_global_assignment -name VERILOG_MACRO "USE_FB=1"
#set_global_assignment -name VERILOG_MACRO "USE_SDRAM=1"
#set_global_assignment -name VERILOG_MACRO "USE_DDRAM=1"
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

175
Arcade-SolomonsKey.sv
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@@ -4,6 +4,7 @@
// Original implimentation and port to MiSTer by MiSTer-X 2019
//============================================================================
module emu
(
//Master input clock
@@ -17,11 +18,15 @@ module emu
inout [45:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output VGA_CLK,
output CLK_VIDEO,
//Multiple resolutions are supported using different VGA_CE rates.
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output VGA_CE,
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [11:0] VIDEO_ARX,
output [11:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
@@ -29,26 +34,36 @@ module emu
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
//Base video clock. Usually equals to CLK_SYS.
output HDMI_CLK,
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
//Multiple resolutions are supported using different HDMI_CE rates.
//Must be based on CLK_VIDEO
output HDMI_CE,
`ifdef USE_FB
// Use framebuffer from DDRAM (USE_FB=1 in qsf)
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of 16 bytes.
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE, // = ~(VBlank | HBlank)
output [1:0] HDMI_SL, // scanlines fx
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] HDMI_ARX,
output [7:0] HDMI_ARY,
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
output LED_USER, // 1 - ON, 0 - OFF.
@@ -58,10 +73,25 @@ module emu
output [1:0] LED_POWER,
output [1:0] LED_DISK,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
`ifdef USE_DDRAM
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
`endif
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
@@ -72,20 +102,22 @@ module emu
);
assign VGA_F1 = 0;
assign VGA_SCALER= 0;
assign USER_OUT = '1;
assign LED_USER = ioctl_download;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
assign HDMI_ARY = status[1] ? 8'd9 : 8'd3;
wire [1:0] ar = status[2:1];
assign VIDEO_ARX = (!ar) ? ( 8'd4) : (ar - 1'd1);
assign VIDEO_ARY = (!ar) ? ( 8'd3) : 12'd0;
`include "build_id.v"
localparam CONF_STR = {
"A.SolmnsKey;;",
"F,rom;", // allow loading of alternate ROMs
"-;",
"H0O1,Aspect Ratio,Original,Wide;",
"H0O12,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
"-;",
"O89,Difficulty,Normal,Middle,Easy,Hard;",
@@ -149,7 +181,6 @@ wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [10:0] ps2_key;
wire [15:0] joystk1, joystk2;
wire [21:0] gamma_bus;
@@ -176,82 +207,28 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.ioctl_dout(ioctl_dout),
.joystick_0(joystk1),
.joystick_1(joystk2),
.ps2_key(ps2_key)
.joystick_1(joystk2)
);
wire pressed = ps2_key[9];
wire [8:0] code = ps2_key[8:0];
always @(posedge clk_sys) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
casex(code)
'hX75: btn_up <= pressed; // up
'hX72: btn_down <= pressed; // down
'hX6B: btn_left <= pressed; // left
'hX74: btn_right <= pressed; // right
'h029: btn_trig1 <= pressed; // space
'h014: btn_trig2 <= pressed; // ctrl
'h005: btn_one_player <= pressed; // F1
'h006: btn_two_players <= pressed; // F2
wire m_up2 = joystk2[3];
wire m_down2 = joystk2[2];
wire m_left2 = joystk2[1];
wire m_right2 = joystk2[0];
wire m_trig21 = joystk2[4];
wire m_trig22 = joystk2[5];
// JPAC/IPAC/MAME Style Codes
'h016: btn_start_1 <= pressed; // 1
'h01E: btn_start_2 <= pressed; // 2
'h02E: btn_coin_1 <= pressed; // 5
'h036: btn_coin_2 <= pressed; // 6
'h02D: btn_up_2 <= pressed; // R
'h02B: btn_down_2 <= pressed; // F
'h023: btn_left_2 <= pressed; // D
'h034: btn_right_2 <= pressed; // G
'h01C: btn_trig1_2 <= pressed; // A
'h01B: btn_trig2_2 <= pressed; // S
endcase
end
end
wire m_start1 = joystk1[6] | joystk2[6];
wire m_start2 = joystk1[7] | joystk2[7];
reg btn_up = 0;
reg btn_down = 0;
reg btn_right = 0;
reg btn_left = 0;
reg btn_trig1 = 0;
reg btn_trig2 = 0;
reg btn_one_player = 0;
reg btn_two_players = 0;
wire m_up1 = joystk1[3] | (bCabinet ? 1'b0 : m_up2);
wire m_down1 = joystk1[2] | (bCabinet ? 1'b0 : m_down2);
wire m_left1 = joystk1[1] | (bCabinet ? 1'b0 : m_left2);
wire m_right1 = joystk1[0] | (bCabinet ? 1'b0 : m_right2);
wire m_trig11 = joystk1[4] | (bCabinet ? 1'b0 : m_trig21);
wire m_trig12 = joystk1[5] | (bCabinet ? 1'b0 : m_trig22);
reg btn_start_1 = 0;
reg btn_start_2 = 0;
reg btn_coin_1 = 0;
reg btn_coin_2 = 0;
reg btn_up_2 = 0;
reg btn_down_2 = 0;
reg btn_left_2 = 0;
reg btn_right_2 = 0;
reg btn_trig1_2 = 0;
reg btn_trig2_2 = 0;
wire m_up2 = btn_up_2 | joystk2[3];
wire m_down2 = btn_down_2 | joystk2[2];
wire m_left2 = btn_left_2 | joystk2[1];
wire m_right2 = btn_right_2 | joystk2[0];
wire m_trig21 = btn_trig1_2 | joystk2[4];
wire m_trig22 = btn_trig2_2 | joystk2[5];
wire m_start1 = btn_one_player | joystk1[6] | joystk2[6] | btn_start_1;
wire m_start2 = btn_two_players | joystk1[7] | joystk2[7] | btn_start_2;
wire m_up1 = btn_up | joystk1[3] | (bCabinet ? 1'b0 : m_up2);
wire m_down1 = btn_down | joystk1[2] | (bCabinet ? 1'b0 : m_down2);
wire m_left1 = btn_left | joystk1[1] | (bCabinet ? 1'b0 : m_left2);
wire m_right1 = btn_right | joystk1[0] | (bCabinet ? 1'b0 : m_right2);
wire m_trig11 = btn_trig1 | joystk1[4] | (bCabinet ? 1'b0 : m_trig21);
wire m_trig12 = btn_trig2 | joystk1[5] | (bCabinet ? 1'b0 : m_trig22);
wire m_coin1 = btn_one_player | btn_coin_1 | joystk1[8];
wire m_coin2 = btn_two_players| btn_coin_2 | joystk2[8];
wire m_coin1 = joystk1[8];
wire m_coin2 = joystk2[8];
///////////////////////////////////////////////////
@@ -268,7 +245,7 @@ always @(posedge clk_hdmi) begin
ce_pix <= old_clk & ~ce_vid;
end
arcade_fx #(256,12) arcade_video
arcade_video #(256,12) arcade_video
(
.*,

34
files.qip
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@@ -1,18 +1,18 @@
set_global_assignment -name VHDL_FILE src/CPU/T80s.vhd
set_global_assignment -name VHDL_FILE src/CPU/T80_Reg.vhd
set_global_assignment -name VHDL_FILE src/CPU/T80_Pack.vhd
set_global_assignment -name VHDL_FILE src/CPU/T80_MCode.vhd
set_global_assignment -name VHDL_FILE src/CPU/T80_ALU.vhd
set_global_assignment -name VHDL_FILE src/CPU/T80.vhd
set_global_assignment -name VERILOG_FILE src/z80ip.v
set_global_assignment -name VHDL_FILE src/YM2149_linmix_sep.vhd
set_global_assignment -name VERILOG_FILE src/SOLOMON_VIDEO.v
set_global_assignment -name VERILOG_FILE src/SOLOMON_SOUND.v
set_global_assignment -name VERILOG_FILE src/SOLOMON_ROMS.v
set_global_assignment -name VERILOG_FILE src/SOLOMON_MAIN.v
set_global_assignment -name VERILOG_FILE src/SOLOMON.v
set_global_assignment -name VERILOG_FILE src/mems.v
set_global_assignment -name VERILOG_FILE src/DPRAM1024_7.v
set_global_assignment -name QIP_FILE src/DPRAM1024_7.qip
set_global_assignment -name VERILOG_FILE src/abusdriver.v
set_global_assignment -name VHDL_FILE rtl/CPU/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/CPU/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/CPU/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/CPU/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/CPU/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/CPU/T80.vhd
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VERILOG_FILE rtl/SOLOMON_VIDEO.v
set_global_assignment -name VERILOG_FILE rtl/SOLOMON_SOUND.v
set_global_assignment -name VERILOG_FILE rtl/SOLOMON_ROMS.v
set_global_assignment -name VERILOG_FILE rtl/SOLOMON_MAIN.v
set_global_assignment -name VERILOG_FILE rtl/SOLOMON.v
set_global_assignment -name VERILOG_FILE rtl/mems.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_7.v
set_global_assignment -name QIP_FILE rtl/DPRAM1024_7.qip
set_global_assignment -name VERILOG_FILE rtl/abusdriver.v
set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-SolomonsKey.sv"

BIN
releases/Arcade-SolomonsKey_20210116.rbf Normal file
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Binary file not shown.

1
releases/Solomon no Kagi (Japan).mra
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@@ -8,6 +8,7 @@
<category>Adventure</category>
<category>Platform</category>
<rbf>solomonskey</rbf>
<buttons names="Trig1,Trig2,Start 1P,Start 2P,Coin" default="A,B,Start,Select,R"/>
<rom index="0" zip="solomon.zip|solomonj.zip" md5="2e540133603058d3949c9a3403e942c6">
<part crc="80fa2be3" name="slmn_02.bin"/>
<part crc="236106b4" name="slmn_03.bin"/>

2
releases/Solomon's Key.mra
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@@ -8,6 +8,8 @@
<category>Adventure</category>
<category>Platform</category>
<rbf>solomonskey</rbf>
<buttons names="Block,Magic,Start 1P,Start 2P,Coin" default="A,B,Start,Select,R"/>
<rom index="0" zip="solomon.zip" md5="75ac218ad31ae027184c2d0185ea969f">
<part crc="80fa2be3" name="2.5lm"/>
<part crc="236106b4" name="3.6lm"/>

0
src/CPU/T80.vhd → rtl/CPU/T80.vhd
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0
src/CPU/T80_ALU.vhd → rtl/CPU/T80_ALU.vhd
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0
src/CPU/T80_MCode.vhd → rtl/CPU/T80_MCode.vhd
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0
src/CPU/T80_Pack.vhd → rtl/CPU/T80_Pack.vhd
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0
src/CPU/T80_Reg.vhd → rtl/CPU/T80_Reg.vhd
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0
src/CPU/T80s.vhd → rtl/CPU/T80s.vhd
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0
src/DPRAM1024_7.qip → rtl/DPRAM1024_7.qip
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0
src/DPRAM1024_7.v → rtl/DPRAM1024_7.v
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0
src/SOLOMON.v → rtl/SOLOMON.v
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0
src/SOLOMON_MAIN.v → rtl/SOLOMON_MAIN.v
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0
src/SOLOMON_ROMS.v → rtl/SOLOMON_ROMS.v
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0
src/SOLOMON_SOUND.v → rtl/SOLOMON_SOUND.v
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0
src/SOLOMON_VIDEO.v → rtl/SOLOMON_VIDEO.v
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0
src/YM2149_linmix_sep.vhd → rtl/YM2149_linmix_sep.vhd
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0
src/abusdriver.v → rtl/abusdriver.v
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0
src/mems.v → rtl/mems.v
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13
rtl/pll.13.qip Normal file
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@@ -0,0 +1,13 @@
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"

0
sys/pll.qip → rtl/pll.qip
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0
sys/pll.v → rtl/pll.v
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0
sys/pll/pll_0002.qip → rtl/pll/pll_0002.qip
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0
sys/pll/pll_0002.v → rtl/pll/pll_0002.v
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0
sys/pll/pll_0002_q13.qip → rtl/pll/pll_0002_q13.qip
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0
src/z80ip.v → rtl/z80ip.v
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174
sys/alsa.sv
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@@ -1,7 +1,7 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019 Sorgelig
// (c)2019,2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
@@ -20,113 +20,137 @@
//============================================================================
module alsa
#(
parameter CLK_RATE = 24576000
)
(
input reset,
output reg en_out,
input en_in,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input clk,
output reg [31:3] ram_address,
input [63:0] ram_data,
output reg ram_req = 0,
input ram_ready,
input spi_ss,
input spi_sck,
input spi_mosi,
output spi_miso,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg spi_new = 0;
reg [127:0] spi_data;
reg [60:0] buf_info;
reg [6:0] spicnt = 0;
always @(posedge spi_sck, posedge spi_ss) begin
reg [7:0] mosi;
reg [6:0] spicnt = 0;
reg [95:0] spi_data;
if(spi_ss) spicnt <= 0;
else begin
mosi <= {mosi[6:0],spi_mosi};
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
spicnt <= spicnt + 1'd1;
if(&spicnt[2:0]) begin
spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
spi_new <= &spicnt;
end
end
end
reg [31:0] buf_addr;
reg [31:0] buf_len;
reg [31:0] buf_wptr = 0;
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
always @(posedge ram_clk) begin
reg n1,n2,n3;
reg [127:0] data1,data2;
reg [31:0] spi_out = 0;
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
n1 <= spi_new;
n2 <= n1;
n3 <= n2;
data1 <= spi_data;
reg [31:3] buf_addr;
reg [18:3] buf_len;
reg [18:3] buf_wptr = 0;
always @(posedge clk) begin
reg [60:0] data1,data2;
data1 <= buf_info;
data2 <= data1;
if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
end
reg [31:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg got_first = 0;
reg ready = 0;
reg ud = 0;
reg [31:0] readdata;
reg [2:0] hurryup = 0;
reg [18:3] buf_rptr = 0;
if(~ram_waitrequest) ram_read <= 0;
if(ram_readdatavalid && ram_burstcount) begin
ram_burstcount <= 0;
ready <= 1;
readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
end
always @(posedge clk) begin
reg [18:3] len = 0;
reg [1:0] ready = 0;
reg [63:0] readdata;
reg got_first = 0;
reg [7:0] ce_cnt = 0;
reg [1:0] state = 0;
if(reset) {ready, got_first, ram_burstcount} <= 0;
else
if(buf_rptr[31:2] != buf_wptr[31:2]) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else
if(!ram_burstcount && ~ram_waitrequest && ~ready && en_out == en_in) begin
ram_address <= buf_addr[31:3] + buf_rptr[31:3];
ud <= buf_rptr[2];
ram_burstcount <= 1;
ram_read <= 1;
buf_rptr <= buf_rptr + 4;
end
if(reset) begin
ready <= 0;
ce_cnt <= 0;
state <= 0;
got_first <= 0;
len <= 0;
end
else begin
if(ready & ce_48k) begin
{pcm_r,pcm_l} <= readdata;
ready <= 0;
//ramp up
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
//ramp down
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
if(!len[18:10]) hurryup <= 0;
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
case(state)
0: if(!ce_sample) begin
if(ready) begin
if(ce_cnt) begin
{readdata[31:0],pcm_r,pcm_l} <= readdata;
ready <= ready - 1'd1;
ce_cnt <= ce_cnt - 1'd1;
end
end
else if(buf_rptr != buf_wptr) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else begin
ram_address <= buf_addr + buf_rptr;
ram_req <= ~ram_req;
buf_rptr <= buf_rptr + 1'd1;
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
state <= 1;
end
end
else begin
len <= 0;
ce_cnt <= 0;
hurryup <= 0;
end
end
1: if(ram_ready) begin
ready <= 2;
readdata <= ram_data;
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
state <= 0;
end
endcase
end
if(ce_48k) en_out <= ~en_out;
end
reg ce_48k;
always @(posedge ram_clk) begin
reg [15:0] acc = 0;
reg ce_sample;
always @(posedge clk) begin
reg [31:0] acc = 0;
ce_48k <= 0;
acc <= acc + 16'd48;
if(acc >= 50000) begin
acc <= acc - 16'd50000;
ce_48k <= 1;
ce_sample <= 0;
acc <= acc + 48000 + {hurryup,6'd0};
if(acc >= CLK_RATE) begin
acc <= acc - CLK_RATE;
ce_sample <= 1;
end
end

808
sys/arcade_video.v
View File

@@ -1,506 +1,302 @@
//============================================================================
//
// Copyright (C) 2017-2019 Sorgelig
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
module arcade_rotate_fx #(parameter WIDTH=320, HEIGHT=240, DW=8, CCW=0, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output VGA_CLK,
output VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output HDMI_CLK,
output HDMI_CE,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE,
output [1:0] HDMI_SL,
input [2:0] fx,
input forced_scandoubler,
input no_rotate,
input direct_video,
inout [21:0] gamma_bus
);
wire [7:0] R,G,B;
wire CE,HS,VS,HBL,VBL;
wire [DW-1:0] RGB_fix;
wire VGA_HBL, VGA_VBL;
arcade_vga #(DW) vga
(
.clk_video(clk_video),
.ce_pix(ce_pix),
.RGB_in(RGB_in),
.HBlank(HBlank),
.VBlank(VBlank),
.HSync(HSync),
.VSync(VSync),
.RGB_out(RGB_fix),
.VGA_CLK(VGA_CLK),
.VGA_CE(CE),
.VGA_R(R),
.VGA_G(G),
.VGA_B(B),
.VGA_HS(HS),
.VGA_VS(VS),
.VGA_HBL(HBL),
.VGA_VBL(VBL)
);
wire [DW-1:0] RGB_out;
wire rhs,rvs,rhblank,rvblank;
screen_rotate #(WIDTH,HEIGHT,DW,4,CCW) rotator
(
.clk(VGA_CLK),
.ce(CE),
.video_in(RGB_fix),
.hblank(HBL),
.vblank(VBL),
.ce_out(CE | (~scandoubler & ~gamma_bus[19])),
.video_out(RGB_out),
.hsync(rhs),
.vsync(rvs),
.hblank_out(rhblank),
.vblank_out(rvblank)
);
wire [3:0] Rr,Gr,Br;
generate
if(DW == 6) begin
assign Rr = {RGB_out[5:4],RGB_out[5:4]};
assign Gr = {RGB_out[3:2],RGB_out[3:2]};
assign Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 8) begin
assign Rr = {RGB_out[7:5],RGB_out[7]};
assign Gr = {RGB_out[4:2],RGB_out[4]};
assign Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 9) begin
assign Rr = {RGB_out[8:6],RGB_out[8]};
assign Gr = {RGB_out[5:3],RGB_out[5]};
assign Br = {RGB_out[2:0],RGB_out[2]};
end
else begin
assign Rr = RGB_out[11:8];
assign Gr = RGB_out[7:4];
assign Br = RGB_out[3:0];
end
endgenerate
reg norot;
always @(posedge VGA_CLK) norot <= no_rotate | direct_video;
assign HDMI_CLK = VGA_CLK;
assign HDMI_SL = (no_rotate & ~direct_video) ? 2'd0 : sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(WIDTH+4, 1, GAMMA) video_mixer
(
.clk_vid(HDMI_CLK),
.ce_pix(CE | (~scandoubler & ~gamma_bus[19] & ~direct_video)),
.ce_pix_out(HDMI_CE),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R(norot ? R[7:4] : Rr),
.G(norot ? G[7:4] : Gr),
.B(norot ? B[7:4] : Br),
.HSync (norot ? HS : rhs),
.VSync (norot ? VS : rvs),
.HBlank(norot ? HBL : rhblank),
.VBlank(norot ? VBL : rvblank),
.VGA_R(HDMI_R),
.VGA_G(HDMI_G),
.VGA_B(HDMI_B),
.VGA_VS(HDMI_VS),
.VGA_HS(HDMI_HS),
.VGA_DE(HDMI_DE)
);
assign VGA_CE = direct_video ? HDMI_CE : CE;
assign VGA_R = direct_video ? HDMI_R : R;
assign VGA_G = direct_video ? HDMI_G : G;
assign VGA_B = direct_video ? HDMI_B : B;
assign VGA_HS = direct_video ? HDMI_HS : HS;
assign VGA_VS = direct_video ? HDMI_VS : VS;
assign VGA_DE = direct_video ? HDMI_DE : ~(HBL | VBL);
endmodule
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
module arcade_fx #(parameter WIDTH=320, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output VGA_CLK,
output VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output HDMI_CLK,
output HDMI_CE,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE,
output [1:0] HDMI_SL,
input [2:0] fx,
input forced_scandoubler,
inout [21:0] gamma_bus
);
wire [7:0] R,G,B;
wire CE,HS,VS,HBL,VBL;
wire VGA_HBL, VGA_VBL;
arcade_vga #(DW) vga
(
.clk_video(clk_video),
.ce_pix(ce_pix),
.RGB_in(RGB_in),
.HBlank(HBlank),
.VBlank(VBlank),
.HSync(HSync),
.VSync(VSync),
.VGA_CLK(VGA_CLK),
.VGA_CE(CE),
.VGA_R(R),
.VGA_G(G),
.VGA_B(B),
.VGA_HS(HS),
.VGA_VS(VS),
.VGA_HBL(HBL),
.VGA_VBL(VBL)
);
assign HDMI_CLK = VGA_CLK;
assign HDMI_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(WIDTH+4, 1, GAMMA) video_mixer
(
.clk_vid(HDMI_CLK),
.ce_pix(CE),
.ce_pix_out(HDMI_CE),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R(R[7:4]),
.G(G[7:4]),
.B(B[7:4]),
.HSync(HS),
.VSync(VS),
.HBlank(HBL),
.VBlank(VBL),
.VGA_R(HDMI_R),
.VGA_G(HDMI_G),
.VGA_B(HDMI_B),
.VGA_VS(HDMI_VS),
.VGA_HS(HDMI_HS),
.VGA_DE(HDMI_DE)
);
assign VGA_CE = HDMI_CE;
assign VGA_R = HDMI_R;
assign VGA_G = HDMI_G;
assign VGA_B = HDMI_B;
assign VGA_HS = HDMI_HS;
assign VGA_VS = HDMI_VS;
assign VGA_DE = HDMI_DE;
endmodule
//////////////////////////////////////////////////////////
module arcade_vga #(parameter DW)
(
input clk_video,
input ce_pix,
input [DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output[DW-1:0] RGB_out,
output VGA_CLK,
output reg VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output reg VGA_HS,
output reg VGA_VS,
output reg VGA_HBL,
output reg VGA_VBL
);
assign VGA_CLK = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(VGA_CLK, HSync, hs_fix);
sync_fix sync_h(VGA_CLK, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
always @(posedge VGA_CLK) begin
reg old_ce;
old_ce <= ce_pix;
VGA_CE <= 0;
if(~old_ce & ce_pix) begin
VGA_CE <= 1;
VGA_HS <= hs_fix;
if(~VGA_HS & hs_fix) VGA_VS <= vs_fix;
RGB_fix <= RGB_in;
VGA_HBL <= HBlank;
if(VGA_HBL & ~HBlank) VGA_VBL <= VBlank;
end
end
assign RGB_out = RGB_fix;
generate
if(DW == 6) begin
assign VGA_R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign VGA_G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign VGA_R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign VGA_G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign VGA_R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign VGA_G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign VGA_B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else begin
assign VGA_R = {RGB_fix[11:8],RGB_fix[11:8]};
assign VGA_G = {RGB_fix[7:4],RGB_fix[7:4]};
assign VGA_B = {RGB_fix[3:0],RGB_fix[3:0]};
end
endgenerate
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2017-2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
//
// Output timings are incompatible with any TV/VGA mode.
// The output is supposed to be send to scaler input.
//
module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4, CCW=0)
(
input clk,
input ce,
input [DEPTH-1:0] video_in,
input hblank,
input vblank,
input ce_out,
output [DEPTH-1:0] video_out,
output reg hsync,
output reg vsync,
output reg hblank_out,
output reg vblank_out
);
localparam bufsize = WIDTH*HEIGHT;
localparam memsize = bufsize*2;
localparam aw = $clog2(memsize); // resolutions up to ~ 512x256
reg [aw-1:0] addr_in, addr_out;
reg we_in;
reg buff = 0;
(* ramstyle="no_rw_check" *) reg [DEPTH-1:0] ram[memsize];
always @ (posedge clk) if (en_we) ram[addr_in] <= video_in;
always @ (posedge clk) out <= ram[addr_out];
reg [DEPTH-1:0] out;
reg [DEPTH-1:0] vout;
assign video_out = vout;
wire en_we = ce & ~blank & en_x & en_y;
wire en_x = (xpos<WIDTH);
wire en_y = (ypos<HEIGHT);
integer xpos, ypos;
wire blank = hblank | vblank;
always @(posedge clk) begin
reg old_blank, old_vblank;
reg [aw-1:0] addr_row;
if(en_we) begin
addr_in <= CCW ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
xpos <= xpos + 1;
end
old_blank <= blank;
old_vblank <= vblank;
if(~old_blank & blank) begin
xpos <= 0;
ypos <= ypos + 1;
addr_in <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
addr_row <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
end
if(~old_vblank & vblank) begin
if(buff) begin
addr_in <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
addr_row <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
end else begin
addr_in <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
addr_row <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
end
buff <= ~buff;
ypos <= 0;
xpos <= 0;
end
end
always @(posedge clk) begin
reg old_buff;
reg hs;
reg ced;
integer vbcnt;
integer xposo, yposo, xposd, yposd;
ced <= 0;
if(ce_out) begin
ced <= 1;
xposd <= xposo;
yposd <= yposo;
if(xposo == (HEIGHT + 8)) hsync <= 1;
if(xposo == (HEIGHT + 10)) hsync <= 0;
if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
end
xposo <= xposo + 1;
if(xposo > (HEIGHT + 16)) begin
xposo <= 0;
if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
vblank_out <= 1;
vbcnt <= vbcnt + 1;
if(vbcnt == 10 ) vsync <= 1;
if(vbcnt == 12) vsync <= 0;
end
else yposo <= yposo + 1;
old_buff <= buff;
if(old_buff != buff) begin
addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
yposo <= 0;
vsync <= 0;
vbcnt <= 0;
vblank_out <= 0;
end
end
end
if(ced) begin
if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
vout <= 0;
end else begin
vout <= out;
end
if(xposd == 0) hblank_out <= 0;
if(xposd == HEIGHT) hblank_out <= 1;
end
end
endmodule
//============================================================================
//
// Copyright (C) 2017-2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
// 24 : 8R 8G 8B
module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output CLK_VIDEO,
output CE_PIXEL,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output [1:0] VGA_SL,
input [2:0] fx,
input forced_scandoubler,
inout [21:0] gamma_bus
);
assign CLK_VIDEO = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(CLK_VIDEO, HSync, hs_fix);
sync_fix sync_h(CLK_VIDEO, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
reg CE,HS,VS,HBL,VBL;
always @(posedge CLK_VIDEO) begin
reg old_ce;
old_ce <= ce_pix;
CE <= 0;
if(~old_ce & ce_pix) begin
CE <= 1;
HS <= hs_fix;
if(~HS & hs_fix) VS <= vs_fix;
RGB_fix <= RGB_in;
HBL <= HBlank;
if(HBL & ~HBlank) VBL <= VBlank;
end
end
wire [7:0] R,G,B;
generate
if(DW == 6) begin
assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else if(DW == 12) begin
assign R = {RGB_fix[11:8],RGB_fix[11:8]};
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else begin // 24
assign R = RGB_fix[23:16];
assign G = RGB_fix[15:8];
assign B = RGB_fix[7:0];
end
endgenerate
assign VGA_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
(
.clk_vid(CLK_VIDEO),
.ce_pix(CE),
.ce_pix_out(CE_PIXEL),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R((DW!=24) ? R[7:4] : R),
.G((DW!=24) ? G[7:4] : G),
.B((DW!=24) ? B[7:4] : B),
.HSync (HS),
.VSync (VS),
.HBlank(HBL),
.VBlank(VBL),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.VGA_DE(VGA_DE)
);
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module screen_rotate
(
input CLK_VIDEO,
input CE_PIXEL,
input [7:0] VGA_R,
input [7:0] VGA_G,
input [7:0] VGA_B,
input VGA_HS,
input VGA_VS,
input VGA_DE,
input rotate_ccw,
input no_rotate,
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
output DDRAM_RD
);
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
assign DDRAM_CLK = CLK_VIDEO;
assign DDRAM_BURSTCNT = 1;
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F;
assign DDRAM_DIN = {ram_data,ram_data};
assign DDRAM_WE = ram_wr;
assign DDRAM_RD = 0;
assign FB_EN = fb_en[2];
assign FB_FORMAT = 5'b00110;
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
assign FB_WIDTH = vsz;
assign FB_HEIGHT = hsz;
assign FB_STRIDE = stride;
function [1:0] buf_next;
input [1:0] a,b;
begin
buf_next = 1;
if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2;
if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0;
end
endfunction
reg [1:0] i_fb,o_fb;
always @(posedge CLK_VIDEO) begin
reg old_vbl,old_vs;
old_vbl <= FB_VBL;
old_vs <= VGA_VS;
if(FB_LL) begin
if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]};
if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]};
end
else begin
if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb);
if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb);
end
end
initial begin
fb_en = 0;
end
reg [2:0] fb_en = 0;
reg [11:0] hsz = 320, vsz = 240;
reg [11:0] bwidth;
reg [22:0] bufsize;
always @(posedge CLK_VIDEO) begin
reg [11:0] hcnt = 0, vcnt = 0;
reg old_vs, old_de;
if(CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
hcnt <= hcnt + 1'd1;
if(~old_de & VGA_DE) begin
hcnt <= 1;
vcnt <= vcnt + 1'd1;
end
if(old_de & ~VGA_DE) hsz <= hcnt;
if(~old_vs & VGA_VS) begin
vsz <= vcnt;
bwidth <= vcnt + 2'd3;
vcnt <= 0;
fb_en <= {fb_en[1:0], ~no_rotate};
end
if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
end
end
wire [13:0] stride = {bwidth[11:2], 4'd0};
reg [22:0] ram_addr, next_addr;
reg [31:0] ram_data;
reg ram_wr;
always @(posedge CLK_VIDEO) begin
reg [13:0] hcnt = 0;
reg old_vs, old_de;
ram_wr <= 0;
if(CE_PIXEL) begin
old_vs <= VGA_VS;
old_de <= VGA_DE;
if(~old_vs & VGA_VS) begin
next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
end
if(VGA_DE) begin
ram_wr <= 1;
ram_data <= {VGA_B,VGA_G,VGA_R};
ram_addr <= next_addr;
next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
end
if(old_de & ~VGA_DE) begin
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
end
end
end
endmodule

375
sys/ascal.vhd
View File

@@ -1,14 +1,14 @@
--------------------------------------------------------------------------------
-- AVALON SCALER
--------------------------------------------------------------------------------
-- TEMLIB 10/2018
-- TEMLIB 2018 - 2020
--------------------------------------------------------------------------------
-- This code can be freely distributed and used for any purpose, but, if you
-- find any bug, or want to suggest an enhancement, you ought to send a mail
-- to info@temlib.org.
--------------------------------------------------------------------------------
-- Features :
-- Features
-- - Arbitrary output video format
-- - Autodetect input image size or fixed window
-- - Progressive and interlaced input
@@ -30,7 +30,7 @@
-- below 1x) them.
--------------------------------------------
-- 5 clock domains :
-- 5 clock domains
-- i_xxx : Input video
-- o_xxx : Output video
-- avl_xxx : Avalon memory bus
@@ -54,10 +54,10 @@
-- 1 : Pixel format
-- 0 : 16 bits/pixel, RGB : RRRRRGGGGGGBBBBB
-- 1 : 24 bits/pixel, RGB
-- 2 : 32 bits/pixels RGB0
-- 2 : 32 bits/pixel, RGB0
-- 3:2 : Header size : Offset to start of picture (= N_BURST). 12 bits
-- 5:4 : Attributes. TBD
-- 5:4 : Attributes
-- b0 ; Interlaced
-- b1 : Field number
-- b2 : Horizontal downscaled
@@ -83,7 +83,7 @@ USE ieee.numeric_std.ALL;
-- 100 : Polyphase
-- 101 : TBD
-- 110 : TBD
-- 111 : TEST
-- 111 : TBD
-- MODE[3]
-- 0 : Direct. Single framebuffer.
@@ -98,7 +98,8 @@ USE ieee.numeric_std.ALL;
-- Must be a power of two
-- INTER : True=Autodetect interlaced video False=Force progressive scan
-- HEADER : True=Add image properties header
-- PALETTE : Enable palette for framebuffer -8bpp mode
-- PALETTE : Enable palette for framebuffer 8bpp mode
-- PALETTE2 : Enable palette for framebuffer 8bpp mode supplied by core
-- DOWNSCALE : True=Support downscaling False=Downscaling disabled
-- BYTESWAP : Little/Big endian byte swap
-- FRAC : Fractional bits, subpixel resolution
@@ -120,6 +121,7 @@ ENTITY ascal IS
DOWNSCALE : boolean := true;
BYTESWAP : boolean := true;
PALETTE : boolean := true;
PALETTE2 : boolean := true;
FRAC : natural RANGE 4 TO 6 :=4;
OHRES : natural RANGE 1 TO 4096 :=2048;
IHRES : natural RANGE 1 TO 2048 :=2048;
@@ -148,6 +150,7 @@ ENTITY ascal IS
o_hs : OUT std_logic; -- H sync
o_vs : OUT std_logic; -- V sync
o_de : OUT std_logic; -- Display Enable
o_vbl : OUT std_logic; -- V blank
o_ce : IN std_logic; -- Clock Enable
o_clk : IN std_logic; -- Output clock
@@ -161,13 +164,22 @@ ENTITY ascal IS
o_fb_vsize : IN natural RANGE 0 TO 4095 :=0;
o_fb_format : IN unsigned(5 DOWNTO 0) :="000100";
o_fb_base : IN unsigned(31 DOWNTO 0) :=x"0000_0000";
o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0');
-- Framebuffer palette in 8bpp mode
pal_clk : IN std_logic :='0';
pal_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B
pal_dr : OUT unsigned(23 DOWNTO 0) :=x"000000";
pal_a : IN unsigned(7 DOWNTO 0) :=x"00"; -- Colour index
pal_wr : IN std_logic :='0';
pal1_clk : IN std_logic :='0';
pal1_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0
pal1_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000";
pal1_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2
pal1_wr : IN std_logic :='0';
pal_n : IN std_logic :='0';
pal2_clk : IN std_logic :='0';
pal2_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B
pal2_dr : OUT unsigned(23 DOWNTO 0) :=x"000000";
pal2_a : IN unsigned(7 DOWNTO 0) :="00000000"; -- Colour index
pal2_wr : IN std_logic :='0';
------------------------------------
-- Low lag PLL tuning
@@ -175,11 +187,15 @@ ENTITY ascal IS
------------------------------------
-- Input video parameters
iauto : IN std_logic; -- 1=Autodetect image size 0=Choose window
himin : IN natural RANGE 0 TO 4095; -- MIN < MAX, MIN >=0, MAX < DISP
himax : IN natural RANGE 0 TO 4095;
vimin : IN natural RANGE 0 TO 4095;
vimax : IN natural RANGE 0 TO 4095;
iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window
himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP
himax : IN natural RANGE 0 TO 4095 :=0;
vimin : IN natural RANGE 0 TO 4095 :=0;
vimax : IN natural RANGE 0 TO 4095 :=0;
-- Detected input image size
i_hdmax : OUT natural RANGE 0 TO 4095;
i_vdmax : OUT natural RANGE 0 TO 4095;
-- Output video parameters
run : IN std_logic :='1'; -- 1=Enable output image. 0=No image
@@ -187,7 +203,7 @@ ENTITY ascal IS
mode : IN unsigned(4 DOWNTO 0);
-- SYNC |_________________________/"""""""""\_______|
-- DE |""""""""""""""""""\________________________|
-- RGB | <#IMAGE#> ^HDISP |
-- RGB | <#IMAGE#> ^HDISP |
-- ^HMIN ^HMAX ^HSSTART ^HSEND ^HTOTAL
htotal : IN natural RANGE 0 TO 4095;
hsstart : IN natural RANGE 0 TO 4095;
@@ -283,11 +299,12 @@ ARCHITECTURE rtl OF ascal IS
SUBTYPE uint12 IS natural RANGE 0 TO 4095;
SUBTYPE uint13 IS natural RANGE 0 TO 8191;
TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0);
TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0);
TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12;
----------------------------------------------------------
-- Input image
SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
@@ -386,8 +403,14 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
SIGNAL o_format : unsigned(5 DOWNTO 0);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
SIGNAL pal_mem : arr_uv24(0 TO 255);
ATTRIBUTE ramstyle of pal_mem : signal is "no_rw_check";
SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0);
SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0);
SIGNAL pal_idx: unsigned(7 DOWNTO 0);
SIGNAL pal_idx_lsb: std_logic;
SIGNAL pal1_mem : arr_uv48(0 TO 127);
SIGNAL pal2_mem : arr_uv24(0 TO 255);
ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check";
ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check";
SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
SIGNAL o_hsize,o_vsize : uint12;
@@ -397,14 +420,18 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic;
SIGNAL o_bufup0,o_bufup1,o_inter : std_logic;
SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2;
TYPE type_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD);
SIGNAL o_state : type_o_state;
SIGNAL o_copy,o_readack,o_readack_sync,o_readack_sync2 : std_logic;
TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD);
SIGNAL o_state : enum_o_state;
TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY);
SIGNAL o_copy : enum_o_copy;
SIGNAL o_pshift : natural RANGE 0 TO 15;
SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic;
SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic;
SIGNAL o_copyv : unsigned(0 TO 8);
SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address
SIGNAL o_adrs_pre : natural RANGE 0 TO 32*4096-1;
SIGNAL o_adrsa,o_rline : std_logic;
SIGNAL o_adrs_pre : natural RANGE 0 TO 2**23-1;
SIGNAL o_stride : unsigned(13 DOWNTO 0);
SIGNAL o_adrsa,o_adrsb,o_rline : std_logic;
SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1;
SIGNAL o_adturn : std_logic;
SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0);
@@ -422,12 +449,12 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix;
SIGNAL o_wr : unsigned(3 DOWNTO 0);
SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12;
SIGNAL o_ihsize,o_ivsize : uint12;
SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12;
SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767;
SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0);
SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
SIGNAL o_hsv,o_vsv,o_dev,o_pev : unsigned(0 TO 5);
SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 5);
SIGNAL o_hsp,o_vss : std_logic;
SIGNAL o_read,o_read_pre : std_logic;
SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2;
@@ -435,11 +462,13 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_fload : natural RANGE 0 TO 3;
SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO
SIGNAL o_dshi : natural RANGE 0 TO 3;
SIGNAL o_first,o_last,o_last1,o_last2,o_last3 : std_logic;
SIGNAL o_lastt1,o_lastt2,o_lastt3 : std_logic;
SIGNAL o_first,o_last,o_last1,o_last2 : std_logic;
SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic;
SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0);
SIGNAL o_hdown,o_vdown : std_logic;
SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2);
TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15;
SIGNAL o_off : arr_uint4(0 TO 2);
SIGNAL o_bibu : std_logic :='0';
SIGNAL o_dcptv : arr_uint12(1 TO 8);
SIGNAL o_dcpt : uint12;
@@ -593,7 +622,7 @@ ARCHITECTURE rtl OF ascal IS
(N_DW=64 AND ((acpt MOD 2)=0));
END CASE;
END FUNCTION;
FUNCTION shift_opix (shift : unsigned(0 TO N_DW+15);
format : unsigned(5 DOWNTO 0)) RETURN type_pix IS
BEGIN
@@ -615,6 +644,19 @@ ARCHITECTURE rtl OF ascal IS
END CASE;
END FUNCTION;
FUNCTION pixoffset(adrs : unsigned(31 DOWNTO 0);
format : unsigned (5 DOWNTO 0)) RETURN natural IS
BEGIN
CASE format(2 DOWNTO 0) IS
WHEN "011" => -- 8bbp
RETURN to_integer(adrs(NB_LA-1 DOWNTO 0));
WHEN "100" => -- 16bpp 565
RETURN to_integer(adrs(NB_LA-1 DOWNTO 1));
WHEN OTHERS => -- 32bpp
RETURN to_integer(adrs(NB_LA-1 DOWNTO 2));
END CASE;
END FUNCTION;
FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS
VARIABLE e : unsigned(N_DW-1 DOWNTO 0);
BEGIN
@@ -1068,9 +1110,16 @@ BEGIN
i_hmin<=himin; -- <ASYNC>
i_hmax<=himax; -- <ASYNC>
i_vmin<=vimin; -- <ASYNC>
i_vmax<=vimax; -- <ASYNC>
IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
i_vmax<=vimax; -- <ASYNC>
END IF;
END IF;
IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
i_vdmax<=i_vimax;
END IF;
i_hdmax<=i_himax;
IF i_format="00" OR i_format="11" THEN -- 16bpp
i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST;
ELSIF i_format="01" THEN -- 24bpp
@@ -1446,6 +1495,7 @@ BEGIN
-----------------------------------------------------------------------------
-- AVALON interface
Avaloir:PROCESS(avl_clk,avl_reset_na) IS
VARIABLE adr_v : unsigned(31 DOWNTO 0);
BEGIN
IF avl_reset_na='0' THEN
avl_state<=sIDLE;
@@ -1526,7 +1576,6 @@ BEGIN
avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
END IF;
ELSIF avl_read_sr='1' THEN
avl_state<=sREAD;
avl_read_clr<='1';
@@ -1543,14 +1592,12 @@ BEGIN
WHEN sREAD =>
IF avl_rline='0' THEN
avl_address<=std_logic_vector(
avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
avl_o_offset0(N_AW+NB_LA-1 DOWNTO NB_LA));
adr_v:=avl_radrs + avl_o_offset0;
ELSE
avl_address<=std_logic_vector(
avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
avl_o_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
END IF;
adr_v:=avl_radrs + avl_o_offset1;
END IF;
avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA));
avl_read_i<='1';
IF avl_read_i='1' AND avl_waitrequest='0' THEN
avl_state<=sIDLE;
@@ -1645,9 +1692,10 @@ BEGIN
VARIABLE hpix_v : type_pix;
VARIABLE hcarry_v,vcarry_v : boolean;
VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1;
VARIABLE off_v : natural RANGE 0 TO 15;
BEGIN
IF o_reset_na='0' THEN
o_copy<='0';
o_copy<=sWAIT;
o_state<=sDISP;
o_read_pre<='0';
o_readlev<=0;
@@ -1709,12 +1757,21 @@ BEGIN
o_ihsize<=o_fb_hsize;
o_ivsize<=o_fb_vsize;
o_format<=o_fb_format;
o_hdown<='0';
o_vdown<='0';
END IF;
o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2);
o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1);
o_hburst <= o_ihsize_temp2 / N_BURST;
IF o_fb_ena='1' AND o_fb_stride /= 0 THEN
o_stride<=o_fb_stride;
ELSE
o_stride<=to_unsigned(o_ihsize_temp2,14);
o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0');
END IF;
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
o_obuf0<=buf_next(o_obuf0,o_ibuf0);
o_bufup0<='0';
@@ -1775,13 +1832,15 @@ BEGIN
o_vpe<=to_std_logic(o_vcpt_pre<o_vmax AND o_vcpt_pre>=o_vmin);
o_divstart<='0';
o_adrsa<='0';
o_adrsb<=o_adrsa;
o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192;
o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192;
--Alternate phase
--o_vacc_ini<=o_ivsize;
--o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192;
CASE o_state IS
--------------------------------------------------
WHEN sDISP =>
@@ -1803,13 +1862,13 @@ BEGIN
vcarry_v:=true;
END IF;
o_divstart<='1';
IF o_vcpt_pre2=o_vmin THEN --pe='0' THEN
IF o_vcpt_pre2=o_vmin THEN
o_vacc <=o_vacc_ini;
o_vacc_next<=o_vacc_ini + 2*o_ivsize;
o_vacpt<=x"001";
vcarry_v:=false;
END IF;
IF vcarry_v THEN
o_vacpt<=o_vacpt+1;
END IF;
@@ -1822,7 +1881,7 @@ BEGIN
WHEN sREAD =>
-- Read a block
IF o_readlev<2 THEN
IF o_readlev<2 AND o_adrsb='1' THEN
lev_inc_v:='1';
o_read_pre<=NOT o_read_pre;
o_state <=sWAITREAD;
@@ -1831,6 +1890,10 @@ BEGIN
prim_v:=to_std_logic(o_hbcpt=0);
last_v:=to_std_logic(o_hbcpt=o_hburst-1);
bib_v :=o_bibu;
off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format);
IF o_fb_ena='0' THEN
off_v:=0;
END IF;
o_adrsa<='1';
WHEN sWAITREAD =>
@@ -1851,18 +1914,18 @@ BEGIN
END CASE;
o_read<=o_read_pre AND o_run;
o_adrs_pre<=to_integer(o_vacpt) * o_hburst;
o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video
o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride);
IF o_adrsa='1' THEN
IF o_fload=2 THEN
o_adrs<=to_unsigned(o_hbcpt * N_BURST,32);
o_alt<="1111";
ELSIF o_fload=1 THEN
o_adrs<=to_unsigned((o_hburst + o_hbcpt) * N_BURST,32);
o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride;
o_alt<="0100";
ELSE
o_adrs<=to_unsigned((o_adrs_pre + o_hbcpt) * N_BURST,32);
o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32);
o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1);
END IF;
END IF;
@@ -1870,86 +1933,104 @@ BEGIN
------------------------------------------------------
-- Copy from buffered memory to pixel lines
o_sh<='0';
IF o_copy='0' THEN
o_copyv(0)<='0';
IF o_copylev>0 AND o_copyv(0)='0' THEN
o_copy<='1';
o_altx<=o_alt;
END IF;
o_adturn<='0';
IF o_primv(0)='1' THEN
-- First memcopy of a horizontal line, carriage return !
o_hacc <=o_hacc_ini;
o_hacc_next<=o_hacc_ini + 2*o_ihsize;
o_hacpt <=x"000";
o_dcpt<=0;
o_dshi<=2;
o_acpt<=0;
o_first<='1';
o_last<='0';
END IF;
IF o_bibv(0)='0' THEN
o_ad<=0;
ELSE
o_ad<=BLEN;
END IF;
ELSE
-- dshi : Force shift first two or three pixels of each line
IF o_dshi=0 THEN
dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
IF dif_v>=4*OHRES THEN
o_hacc<=o_hacc_next;
o_hacc_next<=o_hacc_next + 2*o_ihsize;
hcarry_v:=false;
ELSE
o_hacc<=dif_v;
o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
hcarry_v:=true;
CASE o_copy IS
WHEN sWAIT =>
o_copyv(0)<='0';
IF o_copylev>0 AND o_copyv(0)='0' THEN
o_copy<=sCOPY;
IF o_off(0)>0 AND o_primv(0)='1' THEN
o_copy<=sSHIFT;
END IF;
o_altx<=o_alt;
END IF;
o_dcpt<=(o_dcpt+1) MOD 4096;
ELSE
o_dshi<=o_dshi-1;
hcarry_v:=false;
END IF;
IF o_dshi<=1 THEN
o_copyv(0)<='1';
END IF;
IF hcarry_v THEN
o_adturn<='0';
o_pshift<=o_off(0) -1;
IF o_primv(0)='1' THEN
-- First memcopy of a horizontal line, carriage return !
o_ihsizem<=o_ihsize + o_off(0) - 2;
o_hacc <=o_hacc_ini;
o_hacc_next<=o_hacc_ini + 2*o_ihsize;
o_hacpt <=x"000";
o_dcpt<=0;
o_dshi<=2;
o_acpt<=0;
o_first<='1';
o_last<='0';
END IF;
IF o_bibv(0)='0' THEN
o_ad<=0;
ELSE
o_ad<=BLEN;
END IF;
WHEN sSHIFT =>
o_hacpt<=o_hacpt+1;
o_last<=to_std_logic(o_hacpt>=o_ihsize-2);
END IF;
IF hcarry_v OR o_dshi>0 THEN
o_sh<='1';
o_acpt<=(o_acpt+1) MOD 16;
-- Shift two more pixels to the right before ending line.
o_last1<=o_last;
o_last2<=o_last1;
IF shift_onext(o_acpt,o_format) THEN
o_ad<=(o_ad+1) MOD (2*BLEN);
END IF;
IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND
(((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN
o_copy<='0';
lev_dec_v:='1';
o_pshift<=o_pshift-1;
IF o_pshift=0 THEN
o_copy<=sCOPY;
END IF;
IF o_ad MOD BLEN=4 THEN
o_adturn<='1';
WHEN sCOPY =>
-- dshi : Force shift first two or three pixels of each line
IF o_dshi=0 THEN
dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
IF dif_v>=4*OHRES THEN
o_hacc<=o_hacc_next;
o_hacc_next<=o_hacc_next + 2*o_ihsize;
hcarry_v:=false;
ELSE
o_hacc<=dif_v;
o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
hcarry_v:=true;
END IF;
o_dcpt<=(o_dcpt+1) MOD 4096;
ELSE
o_dshi<=o_dshi-1;
hcarry_v:=false;
END IF;
END IF;
END IF;
IF o_dshi<=1 THEN
o_copyv(0)<='1';
END IF;
IF hcarry_v THEN
o_hacpt<=o_hacpt+1;
o_last <=to_std_logic(o_hacpt>=o_ihsizem);
END IF;
IF hcarry_v OR o_dshi>0 THEN
o_sh<='1';
o_acpt<=(o_acpt+1) MOD 16;
-- Shift two more pixels to the right before ending line.
o_last1<=o_last;
o_last2<=o_last1;
IF shift_onext(o_acpt,o_format) THEN
o_ad<=(o_ad+1) MOD (2*BLEN);
END IF;
IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND
(((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN
o_copy<=sWAIT;
lev_dec_v:='1';
END IF;
IF o_ad MOD BLEN=4 THEN
o_adturn<='1';
END IF;
END IF;
END CASE;
o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3;
o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2;
o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3;
o_lastt1<=o_last; o_lastt2<=o_lastt1; o_lastt3<=o_lastt2;
o_lastt1<=o_last; o_lastt2<=o_lastt1;
o_lastt3<=o_lastt2; o_lastt4<=o_lastt3;
------------------------------------------------------
IF o_sh3='1' THEN
@@ -1979,7 +2060,7 @@ BEGIN
o_hpix2<=hpix_v;
o_first<='0';
END IF;
IF o_lastt3='1' THEN
IF o_lastt4='1' THEN
-- Right edge. Keep last pixel.
o_hpix0<=o_hpix0;
END IF;
@@ -2007,6 +2088,7 @@ BEGIN
o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line
o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line
o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select
o_off (0 TO 1)<=o_off (1 TO 2); -- Start offset
END IF;
IF lev_inc_v='1' THEN
@@ -2014,15 +2096,18 @@ BEGIN
o_primv(0)<=prim_v;
o_lastv(0)<=last_v;
o_bibv (0)<=bib_v;
o_off (0)<=off_v;
ELSIF (o_readlev=1 AND lev_dec_v='0') OR
(o_readlev=2 AND lev_dec_v='1') THEN
o_primv(1)<=prim_v;
o_lastv(1)<=last_v;
o_bibv (1)<=bib_v;
o_off (1)<=off_v;
END IF;
o_primv(2)<=prim_v;
o_lastv(2)<=last_v;
o_bibv (2)<=bib_v;
o_off (2)<=off_v;
END IF;
------------------------------------------------------
@@ -2036,21 +2121,40 @@ BEGIN
o_v_poly_dr<=o_v_poly(o_v_poly_a) WHEN rising_edge(o_clk);
-- Framebuffer palette
GenPal:IF PALETTE GENERATE
Tempera:PROCESS(pal_clk) IS
GenPal1:IF PALETTE GENERATE
Tempera1:PROCESS(pal1_clk) IS
BEGIN
IF rising_edge(pal_clk) THEN
IF pal_wr='1' THEN
pal_mem(to_integer(pal_a))<=pal_dw;
IF rising_edge(pal1_clk) THEN
IF pal1_wr='1' THEN
pal1_mem(to_integer(pal1_a))<=pal1_dw;
END IF;
pal_dr<=pal_mem(to_integer(pal_a));
pal1_dr<=pal1_mem(to_integer(pal1_a));
END IF;
END PROCESS;
o_fb_pal_dr<=
pal_mem(to_integer(shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7)))
WHEN rising_edge(o_clk);
END GENERATE GenPal;
pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7);
pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk);
o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk);
END GENERATE GenPal1;
GenPal2:IF PALETTE and PALETTE2 GENERATE
Tempera2:PROCESS(pal2_clk) IS
BEGIN
IF rising_edge(pal2_clk) THEN
IF pal2_wr='1' THEN
pal2_mem(to_integer(pal2_a))<=pal2_dw;
END IF;
pal2_dr<=pal2_mem(to_integer(pal2_a));
END IF;
END PROCESS;
o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk);
o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
END GENERATE GenPal2;
GenPal1not2:IF PALETTE and not PALETTE2 GENERATE
o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
END GENERATE GenPal1not2;
GenNoPal:IF NOT PALETTE GENERATE
o_fb_pal_dr<=x"000000";
@@ -2148,7 +2252,7 @@ BEGIN
o_copyv(1 TO 8)<=o_copyv(0 TO 7);
o_dcptv(1)<=o_dcpt;
IF o_dcptv(1)>o_hsize THEN
IF o_dcptv(1)>=o_hsize THEN
o_copyv(2)<='0';
END IF;
o_dcptv(2)<=o_dcptv(1) MOD OHRES;
@@ -2279,6 +2383,7 @@ BEGIN
o_vcpt<=o_vcpt_pre;
END IF;
o_end(0)<=to_std_logic(o_vcpt>=o_vdisp);
o_dev(0)<=to_std_logic(o_hcpt<o_hdisp AND o_vcpt<o_vdisp);
o_pev(0)<=to_std_logic(o_hcpt>=o_hmin AND o_hcpt<=o_hmax AND
o_vcpt>=o_vmin AND o_vcpt<=o_vmax);
@@ -2286,18 +2391,20 @@ BEGIN
o_vsv(0)<=to_std_logic((o_vcpt=o_vsstart AND o_hcpt>=o_hsstart) OR
(o_vcpt>o_vsstart AND o_vcpt<o_vsend) OR
(o_vcpt=o_vsend AND o_hcpt<o_hsstart));
o_vss<=to_std_logic(o_vcpt_pre2>=o_vmin AND o_vcpt_pre2<=o_vmax);
o_hsv(1 TO 5)<=o_hsv(0 TO 4);
o_vsv(1 TO 5)<=o_vsv(0 TO 4);
o_dev(1 TO 5)<=o_dev(0 TO 4);
o_pev(1 TO 5)<=o_pev(0 TO 4);
o_end(1 TO 5)<=o_end(0 TO 4);
IF o_run='0' THEN
o_hsv(2)<='0';
o_vsv(2)<='0';
o_dev(2)<='0';
o_pev(2)<='0';
o_end(2)<='0';
END IF;
END IF;
@@ -2314,7 +2421,7 @@ BEGIN
IF o_ce='1' THEN
-- CYCLE 1 -----------------------------------------
-- Read mem
o_radl<=(o_hcpt-o_hmin+OHRES) MOD OHRES;
o_radl<=(o_hcpt - o_hmin + OHRES) MOD OHRES;
-- CYCLE 2 -----------------------------------------
-- Lines reordering
@@ -2397,6 +2504,7 @@ BEGIN
o_hs<=o_hsv(5);
o_vs<=o_vsv(5);
o_de<=o_dev(5);
o_vbl<=o_end(5);
o_r<=x"00";
o_g<=x"00";
o_b<=x"00";
@@ -2451,4 +2559,3 @@ BEGIN
----------------------------------------------------------------------------
END ARCHITECTURE rtl;

247
sys/audio_out.v
View File

@@ -1,7 +1,7 @@
module audio_out
#(
parameter CLK_RATE = 50000000
parameter CLK_RATE = 24576000
)
(
input reset,
@@ -10,8 +10,24 @@ module audio_out
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [15:0] left_in,
input [15:0] right_in,
input [31:0] flt_rate,
input [39:0] cx,
input [7:0] cx0,
input [7:0] cx1,
input [7:0] cx2,
input [23:0] cy0,
input [23:0] cy1,
input [23:0] cy2,
input [4:0] att,
input [1:0] mix,
input is_signed,
input [15:0] core_l,
input [15:0] core_r,
input [15:0] alsa_l,
input [15:0] alsa_r,
// I2S
output i2s_bclk,
@@ -38,11 +54,11 @@ reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce <= 0;
mclk_ce = 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce <= 1;
mclk_ce = 1;
end
end
@@ -56,19 +72,6 @@ always @(posedge clk) begin
end
end
reg lpf_ce;
always @(posedge clk) begin
integer div;
lpf_ce <= 0;
if(mclk_ce) begin
div <= div + 1;
if(div == FILTER_DIV) begin
div <= 0;
lpf_ce <= 1;
end
end
end
i2s i2s
(
.reset(reset),
@@ -111,47 +114,183 @@ sigma_delta_dac #(15) sd_r
.DACout(dac_r)
);
wire [15:0] al, ar;
lpf_aud lpf_l
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(left_in),
.ODATA(al)
);
reg sample_ce;
always @(posedge clk) begin
reg [8:0] div = 0;
reg [1:0] add = 0;
lpf_aud lpf_r
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(right_in),
.ODATA(ar)
);
div <= div + add;
if(!div) begin
div <= 2'd1 << sample_rate;
add <= 2'd1 << sample_rate;
end
endmodule
module lpf_aud
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
sample_ce <= !div;
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
reg flt_ce;
always @(posedge clk) begin
reg [31:0] cnt = 0;
flt_ce = 0;
cnt = cnt + {flt_rate[30:0],1'b0};
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
flt_ce = 1;
end
end
reg [15:0] cl,cr;
always @(posedge clk) begin
reg [15:0] cl1,cl2;
reg [15:0] cr1,cr2;
cl1 <= core_l; cl2 <= cl1;
if(cl2 == cl1) cl <= cl2;
cr1 <= core_r; cr2 <= cr1;
if(cr2 == cr1) cr <= cr2;
end
reg a_en1 = 0, a_en2 = 0;
always @(posedge clk, posedge reset) begin
reg [1:0] dly1 = 0;
reg [14:0] dly2 = 0;
if(reset) begin
dly1 <= 0;
dly2 <= 0;
a_en1 <= 0;
a_en2 <= 0;
end
else begin
if(flt_ce) begin
if(~&dly1) dly1 <= dly1 + 1'd1;
else a_en1 <= 1;
end
if(sample_ce) begin
if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1;
else a_en2 <= 1;
end
end
end
wire [15:0] acl, acr;
IIR_filter #(.use_params(0)) IIR_filter
(
.clk(clk),
.reset(reset),
.ce(flt_ce & a_en1),
.sample_ce(sample_ce),
.cx(cx),
.cx0(cx0),
.cx1(cx1),
.cx2(cx2),
.cy0(cy0),
.cy1(cy1),
.cy2(cy2),
.input_l({~is_signed ^ cl[15], cl[14:0]}),
.input_r({~is_signed ^ cr[15], cr[14:0]}),
.output_l(acl),
.output_r(acr)
);
wire [15:0] adl;
DC_blocker dcb_l
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acl),
.dout(adl)
);
wire [15:0] adr;
DC_blocker dcb_r
(
.clk(clk),
.ce(sample_ce),
.sample_rate(sample_rate),
.mute(~a_en2),
.din(acr),
.dout(adr)
);
wire [15:0] al, audio_l_pre;
aud_mix_top audmix_l
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adl),
.pre_in(audio_r_pre),
.linux_audio(alsa_l),
.pre_out(audio_l_pre),
.out(al)
);
wire [15:0] ar, audio_r_pre;
aud_mix_top audmix_r
(
.clk(clk),
.ce(sample_ce),
.att(att),
.mix(mix),
.core_audio(adr),
.pre_in(audio_l_pre),
.linux_audio(alsa_r),
.pre_out(audio_r_pre),
.out(ar)
);
endmodule
module aud_mix_top
(
input clk,
input ce,
input [4:0] att,
input [1:0] mix,
input [15:0] core_audio,
input [15:0] linux_audio,
input [15:0] pre_in,
output reg [15:0] pre_out = 0,
output reg [15:0] out = 0
);
reg signed [16:0] a1, a2, a3, a4;
always @(posedge clk) if (ce) begin
a1 <= {core_audio[15],core_audio};
a2 <= a1 + {linux_audio[15],linux_audio};
pre_out <= a2[16:1];
case(mix)
0: a3 <= a2;
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
endcase
if(att[4]) a4 <= 0;
else a4 <= a3 >>> att[3:0];
//clamping
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
end
endmodule

146
sys/build_id.tcl
View File

@@ -1,73 +1,73 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file
# Sorgelig - 17/2/2018
proc generateCDF {revision device outpath} {
set outputFileName "jtag.cdf"
set outputFile [open $outputFileName "w"]
puts $outputFile "JedecChain;"
puts $outputFile " FileRevision(JESD32A);"
puts $outputFile " DefaultMfr(6E);"
puts $outputFile ""
puts $outputFile " P ActionCode(Ign)"
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
puts $outputFile " P ActionCode(Cfg)"
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
puts $outputFile "ChainEnd;"
puts $outputFile ""
puts $outputFile "AlteraBegin;"
puts $outputFile " ChainType(JTAG);"
puts $outputFile "AlteraEnd;"
}
set project_name [lindex $quartus(args) 1]
set revision [lindex $quartus(args) 2]
if {[project_exists $project_name]} {
if {[string equal "" $revision]} {
project_open $project_name -revision [get_current_revision $project_name]
} else {
project_open $project_name -revision $revision
}
} else {
post_message -type error "Project $project_name does not exist"
exit
}
set device [get_global_assignment -name DEVICE]
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
if [is_project_open] {
project_close
}
generateBuildID_Verilog
generateCDF $revision $device $outpath
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file
# Sorgelig - 17/2/2018
proc generateCDF {revision device outpath} {
set outputFileName "jtag.cdf"
set outputFile [open $outputFileName "w"]
puts $outputFile "JedecChain;"
puts $outputFile " FileRevision(JESD32A);"
puts $outputFile " DefaultMfr(6E);"
puts $outputFile ""
puts $outputFile " P ActionCode(Ign)"
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
puts $outputFile " P ActionCode(Cfg)"
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
puts $outputFile "ChainEnd;"
puts $outputFile ""
puts $outputFile "AlteraBegin;"
puts $outputFile " ChainType(JTAG);"
puts $outputFile "AlteraEnd;"
}
set project_name [lindex $quartus(args) 1]
set revision [lindex $quartus(args) 2]
if {[project_exists $project_name]} {
if {[string equal "" $revision]} {
project_open $project_name -revision [get_current_revision $project_name]
} else {
project_open $project_name -revision $revision
}
} else {
post_message -type error "Project $project_name does not exist"
exit
}
set device [get_global_assignment -name DEVICE]
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
if [is_project_open] {
project_close
}
generateBuildID_Verilog
generateCDF $revision $device $outpath

108
sys/ddr_svc.sv Normal file
View File

@@ -0,0 +1,108 @@
//
// Copyright (c) 2020 Alexey Melnikov
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// 16-bit version
module ddr_svc
(
input clk,
input ram_waitrequest,
output [7:0] ram_burstcnt,
output [28:0] ram_addr,
input [63:0] ram_readdata,
input ram_read_ready,
output reg ram_read,
output [63:0] ram_writedata,
output [7:0] ram_byteenable,
output reg ram_write,
output [7:0] ram_bcnt,
input [31:3] ch0_addr,
input [7:0] ch0_burst,
output [63:0] ch0_data,
input ch0_req,
output ch0_ready,
input [31:3] ch1_addr,
input [7:0] ch1_burst,
output [63:0] ch1_data,
input ch1_req,
output ch1_ready
);
assign ram_burstcnt = ram_burst;
assign ram_byteenable = 8'hFF;
assign ram_addr = ram_address;
assign ram_writedata = 0;
assign ch0_data = ram_q[0];
assign ch1_data = ram_q[1];
assign ch0_ready = ready[0];
assign ch1_ready = ready[1];
reg [7:0] ram_burst;
reg [63:0] ram_q[2];
reg [31:3] ram_address;
reg [1:0] ack = 0;
reg [1:0] ready;
reg state = 0;
reg ch = 0;
always @(posedge clk) begin
ready <= 0;
if(!ram_waitrequest) begin
ram_read <= 0;
ram_write <= 0;
case(state)
0: if(ch0_req != ack[0]) begin
ack[0] <= ch0_req;
ram_address <= ch0_addr;
ram_burst <= ch0_burst;
ram_read <= 1;
ch <= 0;
ram_bcnt <= 8'hFF;
state <= 1;
end
else if(ch1_req != ack[1]) begin
ack[1] <= ch1_req;
ram_address <= ch1_addr;
ram_burst <= ch1_burst;
ram_read <= 1;
ch <= 1;
ram_bcnt <= 8'hFF;
state <= 1;
end
1: begin
if(ram_read_ready) begin
ram_bcnt <= ram_bcnt + 1'd1;
ram_q[ch] <= ram_readdata;
ready[ch] <= 1;
if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
end
end
endcase
end
end
endmodule

86
sys/fbpal.sv
View File

@@ -1,86 +0,0 @@
//============================================================================
//
// Framebuffer Palette support for MiSTer
// (c)2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module fbpal
(
input reset,
input en_in,
output reg en_out,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input [31:0] fb_address,
input pal_en,
output reg [7:0] pal_a,
output reg [23:0] pal_d,
output reg pal_wr
);
reg [31:0] base_addr;
always @(posedge ram_clk) base_addr <= fb_address - 4096;
reg [6:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg [23:0] odd_d;
if(~pal_a[0] & pal_wr) {pal_a[0], pal_d} <= {1'b1, odd_d};
else pal_wr <= 0;
if(~ram_waitrequest) ram_read <= 0;
if(pal_en & ~reset) begin
if(ram_burstcount) begin
if(ram_readdatavalid) begin
ram_burstcount <= 0;
odd_d <= ram_readdata[55:32];
pal_d <= ram_readdata[23:0];
pal_a <= {buf_rptr, 1'b0};
pal_wr <= 1;
en_out <= en_in;
buf_rptr <= buf_rptr + 1'd1;
end
end
else begin
if(~ram_waitrequest && en_out != en_in) begin
ram_address <= base_addr[31:3] + buf_rptr;
ram_burstcount <= 1;
ram_read <= 1;
end
end
end
else begin
en_out <= en_in;
buf_rptr <= 0;
ram_burstcount <= 0;
end
end
endmodule

44
sys/hdmi_config.sv
View File

@@ -111,32 +111,32 @@ wire [15:0] init_data[82] =
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
{8'h18, ypbpr ? 8'h88 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
{8'h19, ypbpr ? 8'h2E : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
{8'h1A, ypbpr ? 8'h18 : 8'h00}, // CSC Channel A.
{8'h1B, ypbpr ? 8'h93 : 8'h00},
{8'h1C, ypbpr ? 8'h1F : 8'h00},
{8'h1D, ypbpr ? 8'h3F : 8'h00},
{8'h1E, ypbpr ? 8'h08 : 8'h01},
{8'h1F, 8'h00},
{8'h18, ypbpr ? 8'h86 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
{8'h19, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
{8'h1A, ypbpr ? 8'h1A : 8'h00}, // CSC Channel A.
{8'h1B, ypbpr ? 8'h3F : 8'h00},
{8'h1C, ypbpr ? 8'h1E : 8'h00},
{8'h1D, ypbpr ? 8'hE2 : 8'h00},
{8'h1E, ypbpr ? 8'h07 : 8'h01},
{8'h1F, ypbpr ? 8'hE7 : 8'h00},
{8'h20, ypbpr ? 8'h03 : 8'h00}, // CSC Channel B.
{8'h21, ypbpr ? 8'h67 : 8'h00},
{8'h22, ypbpr ? 8'h0B : limited[0] ? 8'h0D : 8'h0E},
{8'h23, ypbpr ? 8'h71 : limited[0] ? 8'hBC : 8'hFE},
{8'h20, ypbpr ? 8'h04 : 8'h00}, // CSC Channel B.
{8'h21, ypbpr ? 8'h1C : 8'h00},
{8'h22, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
{8'h23, ypbpr ? 8'h11 : limited[0] ? 8'hBC : 8'hFE},
{8'h24, ypbpr ? 8'h01 : 8'h00},
{8'h25, ypbpr ? 8'h28 : 8'h00},
{8'h26, ypbpr ? 8'h00 : 8'h01},
{8'h25, ypbpr ? 8'h91 : 8'h00},
{8'h26, ypbpr ? 8'h01 : 8'h01},
{8'h27, 8'h00},
{8'h28, ypbpr ? 8'h1E : 8'h00}, // CSC Channel C.
{8'h29, ypbpr ? 8'h21 : 8'h00},
{8'h2A, ypbpr ? 8'h19 : 8'h00},
{8'h2B, ypbpr ? 8'hB2 : 8'h00},
{8'h2C, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
{8'h2D, ypbpr ? 8'h2D : limited[0] ? 8'hBC : 8'hFE},
{8'h2E, ypbpr ? 8'h08 : 8'h01},
{8'h2F, 8'h00},
{8'h28, ypbpr ? 8'h1D : 8'h00}, // CSC Channel C.
{8'h29, ypbpr ? 8'hAE : 8'h00},
{8'h2A, ypbpr ? 8'h1B : 8'h00},
{8'h2B, ypbpr ? 8'h73 : 8'h00},
{8'h2C, ypbpr ? 8'h06 : limited[0] ? 8'h0D : 8'h0E},
{8'h2D, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE},
{8'h2E, ypbpr ? 8'h07 : 8'h01},
{8'h2F, ypbpr ? 8'hE7 : 8'h00},
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.

520
sys/hps_io.v
View File

@@ -2,7 +2,7 @@
// hps_io.v
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017-2019 Alexey Melnikov
// Copyright (c) 2017-2020 Alexey Melnikov
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@@ -18,14 +18,11 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
// altera message_off 10665
//
// Use buffer to access SD card. It's time-critical part.
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = CLK_SYS/(PS2DIV*2)
//
// WIDE=1 for 16 bit file I/O
// VDNUM 1-4
module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
@@ -36,12 +33,15 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// buttons up to 32
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [31:0] joystick_5,
// analog -127..+127, Y: [15:8], X: [7:0]
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
@@ -49,6 +49,22 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [15:0] joystick_analog_4,
output reg [15:0] joystick_analog_5,
// paddle 0..255
output reg [7:0] paddle_0,
output reg [7:0] paddle_1,
output reg [7:0] paddle_2,
output reg [7:0] paddle_3,
output reg [7:0] paddle_4,
output reg [7:0] paddle_5,
// spinner [7:0] -128..+127, [8] - toggle with every update
output reg [8:0] spinner_0,
output reg [8:0] spinner_1,
output reg [8:0] spinner_2,
output reg [8:0] spinner_3,
output reg [8:0] spinner_4,
output reg [8:0] spinner_5,
output [1:0] buttons,
output forced_scandoubler,
output direct_video,
@@ -58,6 +74,9 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
input status_set,
input [15:0] status_menumask,
input info_req,
input [7:0] info,
//toggle to force notify of video mode change
input new_vmode,
@@ -86,10 +105,13 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg [15:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr,
output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2
output reg [DW:0] ioctl_dout,
output reg ioctl_upload = 0, // signal indicating an active upload
input [DW:0] ioctl_din,
output reg ioctl_rd,
output reg [31:0] ioctl_file_ext,
input ioctl_wait,
@@ -104,11 +126,8 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [32:0] TIMESTAMP,
// UART flags
input [15:0] uart_mode,
// CD interface
input [48:0] cd_in,
output reg [48:0] cd_out,
output reg [7:0] uart_mode,
output reg [31:0] uart_speed,
// ps2 keyboard emulation
output ps2_kbd_clk_out,
@@ -133,24 +152,32 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [24:0] ps2_mouse = 0,
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
inout [21:0] gamma_bus
inout [21:0] gamma_bus,
// for core-specific extensions
inout [35:0] EXT_BUS
);
assign EXT_BUS[31:16] = HPS_BUS[31:16];
assign EXT_BUS[35:33] = HPS_BUS[35:33];
localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1;
localparam DW = (WIDE) ? 15 : 7;
localparam AW = (WIDE) ? 7 : 8;
localparam VD = VDNUM-1;
wire io_wait = ioctl_wait;
wire io_enable= |HPS_BUS[35:34];
wire io_strobe= HPS_BUS[33];
wire io_enable= HPS_BUS[34];
wire fp_enable= HPS_BUS[35];
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
wire [15:0] io_din = HPS_BUS[31:16];
reg [15:0] io_dout;
assign HPS_BUS[37] = io_wait;
assign HPS_BUS[37] = ioctl_wait;
assign HPS_BUS[36] = clk_sys;
assign HPS_BUS[32] = io_wide;
assign HPS_BUS[15:0] = io_dout;
assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : fp_enable ? fp_dout : io_dout;
reg [15:0] cfg;
assign buttons = cfg[1:0];
@@ -184,6 +211,7 @@ video_calc video_calc
(
.clk_100(HPS_BUS[43]),
.clk_vid(HPS_BUS[42]),
.clk_sys(clk_sys),
.ce_pix(HPS_BUS[41]),
.de(HPS_BUS[40]),
.hs(HPS_BUS[39]),
@@ -208,18 +236,21 @@ reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
reg [9:0] byte_cnt;
reg [MAX_W:0] byte_cnt;
always@(posedge clk_sys) begin
always@(posedge clk_sys) begin : uio_block
reg [15:0] cmd;
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg [3:0] stick_idx;
reg [3:0] pdsp_idx;
reg ps2skip = 0;
reg [3:0] stflg = 0;
reg [63:0] status_req;
reg old_status_set = 0;
reg [7:0] cd_req = 0;
reg old_cd = 0;
reg old_info = 0;
reg [7:0] info_n = 0;
reg [15:0] tmp1;
reg [7:0] tmp2;
old_status_set <= status_set;
if(~old_status_set & status_set) begin
@@ -227,9 +258,9 @@ always@(posedge clk_sys) begin
status_req <= status_in;
end
old_cd <= cd_in[48];
if(old_cd ^ cd_in[48]) cd_req <= cd_req + 1'd1;
old_info <= info_req;
if(~old_info & info_req) info_n <= info;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
@@ -248,62 +279,62 @@ always@(posedge clk_sys) begin
end
if(cmd == 'h22) RTC[64] <= ~RTC[64];
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
if(cmd == 'h35) cd_out[48] <= ~cd_out[48];
cmd <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
io_dout <= 0;
ps2skip <= 0;
end else begin
if(io_strobe) begin
img_mounted <= 0;
end
else if(io_strobe) begin
io_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
io_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
if(byte_cnt == 0) begin
cmd <= io_din;
if(byte_cnt == 0) begin
cmd <= io_din;
case(io_din)
'h19: sd_ack_conf <= 1;
'h17,
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
'h2F: io_dout <= 1;
'h32: io_dout <= gamma_bus[21];
'h34: io_dout <= cd_req;
endcase
case(io_din)
'h19: sd_ack_conf <= 1;
'h17,
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
'h2F: io_dout <= 1;
'h32: io_dout <= gamma_bus[21];
'h36: begin io_dout <= info_n; info_n <= 0; end
'h39: io_dout <= 1;
endcase
sd_buff_addr <= 0;
img_mounted <= 0;
if(io_din == 5) ps2_key_raw <= 0;
end else begin
sd_buff_addr <= 0;
if(io_din == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din;
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
case(cmd)
// buttons and switches
'h01: cfg <= io_din;
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
// store incoming ps2 mouse bytes
'h04: begin
// store incoming ps2 mouse bytes
'h04: begin
if(PS2DIV) begin
mouse_data <= io_din[7:0];
mouse_we <= 1;
end
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) begin
case(byte_cnt)
if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: ps2_mouse[7:0] <= io_din[7:0];
2: ps2_mouse[15:8] <= io_din[7:0];
3: ps2_mouse[23:16] <= io_din[7:0];
endcase
case(byte_cnt)
case(byte_cnt[1:0])
1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
2: ps2_mouse_ext[11:8] <= io_din[11:8];
3: ps2_mouse_ext[15:12]<= io_din[11:8];
@@ -311,8 +342,8 @@ always@(posedge clk_sys) begin
end
end
// store incoming ps2 keyboard bytes
'h05: begin
// store incoming ps2 keyboard bytes
'h05: begin
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
if(PS2DIV) begin
@@ -321,130 +352,143 @@ always@(posedge clk_sys) begin
end
end
// reading config string, returning a byte from string
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading config string, returning a byte from string
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading sd card status
'h16: case(byte_cnt)
// reading sd card status
'h16: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
4: io_dout <= sd_req_type;
endcase
end
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
'h19,
// send sector IO -> FPGA
// flag that download begins
'h17: begin
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
'h19,
// send sector IO -> FPGA
// flag that download begins
'h17: begin
sd_buff_dout <= io_din[DW:0];
b_wr <= 1;
end
// reading sd card write data
'h18: begin
// reading sd card write data
'h18: begin
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
io_dout <= sd_buff_din;
end
// joystick analog
'h1a: case(byte_cnt)
1: stick_idx <= io_din[2:0]; // first byte is joystick index
// joystick analog
'h1a: if(!byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
2: case(stick_idx)
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
2: joystick_analog_2 <= io_din;
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
2: joystick_analog_2 <= io_din;
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
15: case(pdsp_idx)
0: paddle_0 <= io_din[7:0];
1: paddle_1 <= io_din[7:0];
2: paddle_2 <= io_din[7:0];
3: paddle_3 <= io_din[7:0];
4: paddle_4 <= io_din[7:0];
5: paddle_5 <= io_din[7:0];
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
endcase
endcase
endcase
end
// notify image selection
'h1c: begin
// notify image selection
'h1c: begin
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
img_readonly <= io_din[7];
end
// send image info
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
// send image info
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
// status, 64bit version
'h1e: case(byte_cnt)
// status, 64bit version
'h1e: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: status[15:00] <= io_din;
2: status[31:16] <= io_din;
3: status[47:32] <= io_din;
4: status[63:48] <= io_din;
endcase
end
// reading keyboard LED status
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
// reading keyboard LED status
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
// reading ps2 keyboard/mouse control
'h21: if(PS2DIV) begin
if(byte_cnt == 1) begin
io_dout <= kbd_data_host;
kbd_rd <= 1;
end
else
if(byte_cnt == 2) begin
io_dout <= mouse_data_host;
mouse_rd <= 1;
end
// reading ps2 keyboard/mouse control
'h21: if(PS2DIV) begin
if(byte_cnt == 1) begin
io_dout <= kbd_data_host;
kbd_rd <= 1;
end
else
if(byte_cnt == 2) begin
io_dout <= mouse_data_host;
mouse_rd <= 1;
end
end
//RTC
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//RTC
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: if(!byte_cnt[9:4]) io_dout <= vc_dout;
//Video res.
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//UART flags
'h28: io_dout <= uart_mode;
//status set
'h29: case(byte_cnt)
//status set
'h29: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= status_req[15:00];
2: io_dout <= status_req[31:16];
3: io_dout <= status_req[47:32];
4: io_dout <= status_req[63:48];
endcase
//menu mask
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
//sdram size set
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
end
// Gamma
'h32: gamma_en <= io_din[0];
'h33: begin
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
end
//menu mask
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
//sdram size set
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
//CD get
'h34: case(byte_cnt)
1: io_dout <= cd_in[15:0];
2: io_dout <= cd_in[31:16];
3: io_dout <= cd_in[47:32];
// Gamma
'h32: gamma_en <= io_din[0];
'h33: begin
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
end
// UART
'h3b: if(!byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: tmp2 <= io_din[7:0];
2: tmp1 <= io_din;
3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2};
endcase
//CD set
'h35: case(byte_cnt)
1: cd_out[15:0] <= io_din;
2: cd_out[31:16] <= io_din;
3: cd_out[47:32] <= io_din;
endcase
endcase
end
end
endcase
end
end
end
@@ -454,7 +498,7 @@ end
generate
if(PS2DIV) begin
reg clk_ps2;
always @(negedge clk_sys) begin
always @(posedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
@@ -519,22 +563,24 @@ endgenerate
/////////////////////////////// DOWNLOADING ///////////////////////////////
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
localparam UIO_FILE_INFO = 8'h56;
localparam FIO_FILE_TX = 8'h53;
localparam FIO_FILE_TX_DAT = 8'h54;
localparam FIO_FILE_INDEX = 8'h55;
localparam FIO_FILE_INFO = 8'h56;
always@(posedge clk_sys) begin
reg [15:0] fp_dout;
always@(posedge clk_sys) begin : fio_block
reg [15:0] cmd;
reg [2:0] cnt;
reg has_cmd;
reg [26:0] addr;
reg wr;
ioctl_rd <= 0;
ioctl_wr <= wr;
wr <= 0;
if(~io_enable) has_cmd <= 0;
if(~fp_enable) has_cmd <= 0;
else begin
if(io_strobe) begin
@@ -545,7 +591,7 @@ always@(posedge clk_sys) begin
end else begin
case(cmd)
UIO_FILE_INFO:
FIO_FILE_INFO:
if(~cnt[1]) begin
case(cnt)
0: ioctl_file_ext[31:16] <= io_din;
@@ -554,29 +600,54 @@ always@(posedge clk_sys) begin
cnt <= cnt + 1'd1;
end
UIO_FILE_INDEX:
FIO_FILE_INDEX:
begin
ioctl_index <= io_din[7:0];
ioctl_index <= io_din[15:0];
end
UIO_FILE_TX:
FIO_FILE_TX:
begin
if(io_din[7:0]) begin
addr <= 0;
ioctl_download <= 1;
end else begin
ioctl_addr <= addr;
ioctl_download <= 0;
end
cnt <= cnt + 1'd1;
case(cnt)
0: if(io_din[7:0] == 8'hAA) begin
ioctl_addr <= 0;
ioctl_upload <= 1;
ioctl_rd <= 1;
end
else if(io_din[7:0]) begin
addr <= 0;
ioctl_download <= 1;
end
else begin
if(ioctl_download) ioctl_addr <= addr;
ioctl_download <= 0;
ioctl_upload <= 0;
end
1: begin
ioctl_addr[15:0] <= io_din;
addr[15:0] <= io_din;
end
2: begin
ioctl_addr[26:16] <= io_din[10:0];
addr[26:16] <= io_din[10:0];
end
endcase
end
UIO_FILE_TX_DAT:
begin
FIO_FILE_TX_DAT:
if(ioctl_download) begin
ioctl_addr <= addr;
ioctl_dout <= io_din[DW:0];
wr <= 1;
addr <= addr + (WIDE ? 2'd2 : 2'd1);
end
else begin
ioctl_addr <= ioctl_addr + (WIDE ? 2'd2 : 2'd1);
fp_dout <= ioctl_din;
ioctl_rd <= 1;
end
endcase
end
end
@@ -633,7 +704,7 @@ always@(posedge clk_sys) begin
tx_empty <= ((wptr == rptr) && (tx_state == 0));
if(we) begin
if(we && !has_data) begin
fifo[wptr] <= wdata;
wptr <= wptr + 1'd1;
end
@@ -673,6 +744,8 @@ always@(posedge clk_sys) begin
ps2_dat_out <= 1;
has_data <= 1;
rx_state <= 0;
rptr <= 0;
wptr <= 0;
end
endcase
end else begin
@@ -733,6 +806,8 @@ module video_calc
(
input clk_100,
input clk_vid,
input clk_sys,
input ce_pix,
input de,
input hs,
@@ -745,22 +820,22 @@ module video_calc
output reg [15:0] dout
);
always @(*) begin
always @(posedge clk_sys) begin
case(par_num)
1: dout = {|vid_int, vid_nres};
2: dout = vid_hcnt[15:0];
3: dout = vid_hcnt[31:16];
4: dout = vid_vcnt[15:0];
5: dout = vid_vcnt[31:16];
6: dout = vid_htime[15:0];
7: dout = vid_htime[31:16];
8: dout = vid_vtime[15:0];
9: dout = vid_vtime[31:16];
10: dout = vid_pix[15:0];
11: dout = vid_pix[31:16];
12: dout = vid_vtime_hdmi[15:0];
13: dout = vid_vtime_hdmi[31:16];
default dout = 0;
1: dout <= {|vid_int, vid_nres};
2: dout <= vid_hcnt[15:0];
3: dout <= vid_hcnt[31:16];
4: dout <= vid_vcnt[15:0];
5: dout <= vid_vcnt[31:16];
6: dout <= vid_htime[15:0];
7: dout <= vid_htime[31:16];
8: dout <= vid_vtime[15:0];
9: dout <= vid_vtime[31:16];
10: dout <= vid_pix[15:0];
11: dout <= vid_pix[31:16];
12: dout <= vid_vtime_hdmi[15:0];
13: dout <= vid_vtime_hdmi[31:16];
default dout <= 0;
endcase
end
@@ -861,92 +936,3 @@ always @(posedge clk_100) begin
end
endmodule
//
// Phase shift helper module for better 64MB/128MB modules support.
//
// Copyright (c) 2019 Alexey Melnikov
//
module phase_shift #(parameter M32MB=0, M64MB=0, M128MB=0)
(
input reset,
input clk,
input pll_locked,
output reg phase_en,
output reg updn,
input phase_done,
input [15:0] sdram_sz,
output reg ready
);
localparam ph32 = ($signed(M32MB ) >= 0) ? M32MB : (0 - M32MB);
localparam ph64 = ($signed(M64MB ) >= 0) ? M64MB : (0 - M64MB);
localparam ph128 = ($signed(M128MB) >= 0) ? M128MB : (0 - M128MB);
localparam up32 = ($signed(M32MB ) >= 0) ? 1'b1 : 1'b0;
localparam up64 = ($signed(M64MB ) >= 0) ? 1'b1 : 1'b0;
localparam up128 = ($signed(M128MB) >= 0) ? 1'b1 : 1'b0;
always @(posedge clk, posedge reset) begin
reg [2:0] state = 0;
reg [7:0] cnt;
reg [8:0] ph;
if(reset) begin
state <= 0;
ready <= 0;
end
else begin
case(state)
0: begin
ready <= 0;
if(pll_locked) state <= state + 1'd1;
end
1: if(sdram_sz[15]) begin
cnt <= 0;
if(sdram_sz[14]) ph <= sdram_sz[8:0];
else begin
case(sdram_sz[1:0])
0: ph <= 0;
1: ph <= {up32[0],ph32[7:0]};
2: ph <= {up64[0],ph64[7:0]};
3: ph <= {up128[0],ph128[7:0]};
endcase
end
state <= state + 1'd1;
end
2: if(ph[7:0]) begin
ph[7:0] <= ph[7:0] - 1'd1;
updn <= ph[8];
state <= state + 1'd1;
end
else begin
state <= 6;
end
3: begin
phase_en <= 1;
state <= state + 1'd1;
end
4: if(~phase_done) begin
phase_en <= 0;
state <= state + 1'd1;
end
5: if(phase_done) begin
cnt <= cnt + 1'd1;
if(cnt == ph[7:0]) state <= state + 1'd1;
else state <= 3;
end
6: begin
ready <= 1;
if(!sdram_sz[15]) state <= 0;
end
endcase
end
end
endmodule

192
sys/i2c.v
View File

@@ -1,96 +1,96 @@
module i2c
(
input CLK,
input START,
input READ,
input [6:0] I2C_ADDR,
input I2C_WLEN, // 0 - one byte, 1 - two bytes
input [7:0] I2C_WDATA1,
input [7:0] I2C_WDATA2,
output [7:0] I2C_RDATA,
output reg END = 1,
output reg ACK = 0,
//I2C bus
output I2C_SCL,
inout I2C_SDA
);
// Clock Setting
parameter CLK_Freq = 50_000_000; // 50 MHz
parameter I2C_Freq = 400_000; // 400 KHz
localparam I2C_FreqX2 = I2C_Freq*2;
reg I2C_CLOCK;
reg [31:0] cnt;
wire [31:0] cnt_next = cnt + I2C_FreqX2;
always @(posedge CLK) begin
cnt <= cnt_next;
if(cnt_next >= CLK_Freq) begin
cnt <= cnt_next - CLK_Freq;
I2C_CLOCK <= ~I2C_CLOCK;
end
end
assign I2C_SCL = SCLK | I2C_CLOCK;
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
reg SCLK = 1;
reg [3:0] SDO = 4'b1111;
reg [0:7] rdata;
assign I2C_RDATA = rdata;
always @(posedge CLK) begin
reg old_clk;
reg old_st;
reg rd,len;
reg [5:0] SD_COUNTER = 'b111111;
reg [0:31] SD;
old_clk <= I2C_CLOCK;
old_st <= START;
// delay to make sure SDA changed while SCL is stabilized at low
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
SDO[3:1] <= SDO[2:0];
if(~old_st && START) begin
SCLK <= 1;
SDO <= 4'b1111;
ACK <= 0;
END <= 0;
rd <= READ;
len <= I2C_WLEN;
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
SD_COUNTER <= 0;
end else begin
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
SD_COUNTER <= SD_COUNTER + 6'd1;
case(SD_COUNTER)
01: SCLK <= 0;
10: ACK <= ACK | I2C_SDA;
19: if(~rd) begin
ACK <= ACK | I2C_SDA;
if(~len) SD_COUNTER <= 29;
end
20: if(rd) SCLK <= 1;
23: if(rd) END <= 1;
28: if(~rd) ACK <= ACK | I2C_SDA;
29: if(~rd) SCLK <= 1;
32: if(~rd) END <= 1;
endcase
if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
end
end
end
endmodule
module i2c
(
input CLK,
input START,
input READ,
input [6:0] I2C_ADDR,
input I2C_WLEN, // 0 - one byte, 1 - two bytes
input [7:0] I2C_WDATA1,
input [7:0] I2C_WDATA2,
output [7:0] I2C_RDATA,
output reg END = 1,
output reg ACK = 0,
//I2C bus
output I2C_SCL,
inout I2C_SDA
);
// Clock Setting
parameter CLK_Freq = 50_000_000; // 50 MHz
parameter I2C_Freq = 400_000; // 400 KHz
localparam I2C_FreqX2 = I2C_Freq*2;
reg I2C_CLOCK;
reg [31:0] cnt;
wire [31:0] cnt_next = cnt + I2C_FreqX2;
always @(posedge CLK) begin
cnt <= cnt_next;
if(cnt_next >= CLK_Freq) begin
cnt <= cnt_next - CLK_Freq;
I2C_CLOCK <= ~I2C_CLOCK;
end
end
assign I2C_SCL = SCLK | I2C_CLOCK;
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
reg SCLK = 1;
reg [3:0] SDO = 4'b1111;
reg [0:7] rdata;
assign I2C_RDATA = rdata;
always @(posedge CLK) begin
reg old_clk;
reg old_st;
reg rd,len;
reg [5:0] SD_COUNTER = 'b111111;
reg [0:31] SD;
old_clk <= I2C_CLOCK;
old_st <= START;
// delay to make sure SDA changed while SCL is stabilized at low
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
SDO[3:1] <= SDO[2:0];
if(~old_st && START) begin
SCLK <= 1;
SDO <= 4'b1111;
ACK <= 0;
END <= 0;
rd <= READ;
len <= I2C_WLEN;
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
SD_COUNTER <= 0;
end else begin
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
SD_COUNTER <= SD_COUNTER + 6'd1;
case(SD_COUNTER)
01: SCLK <= 0;
10: ACK <= ACK | I2C_SDA;
19: if(~rd) begin
ACK <= ACK | I2C_SDA;
if(~len) SD_COUNTER <= 29;
end
20: if(rd) SCLK <= 1;
23: if(rd) END <= 1;
28: if(~rd) ACK <= ACK | I2C_SDA;
29: if(~rd) SCLK <= 1;
32: if(~rd) END <= 1;
endcase
if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
end
end
end
endmodule

213
sys/iir_filter.v Normal file
View File

@@ -0,0 +1,213 @@
// 3-tap IIR filter for 2 channels.
// Copyright (C) 2020 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0)
//
module IIR_filter
#(
parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables.
parameter stereo = 1, // 0 for mono (input_l)
parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9)
parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7
parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7
parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7
parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9)
parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9)
parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9)
)
(
input clk,
input reset,
input ce, // must be double of calculated rate for stereo!
input sample_ce, // desired output sample rate
input [39:0] cx,
input [7:0] cx0,
input [7:0] cx1,
input [7:0] cx2,
input [23:0] cy0,
input [23:0] cy1,
input [23:0] cy2,
input [15:0] input_l, input_r, // signed samples
output [15:0] output_l, output_r // signed samples
);
localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000;
localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000;
localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000;
localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000;
wire [39:0] vcoeff = use_params ? pcoeff_x : cx;
wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0;
wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1;
wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2;
wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff);
wire [39:0] x = inp_mul[59:20];
wire [39:0] y = x + tap0;
wire [39:0] tap0;
iir_filter_tap iir_tap_0
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x0[7:0] : cx0),
.cy(vcoeff_y0),
.x(x),
.y(y),
.z(tap1),
.tap(tap0)
);
wire [39:0] tap1;
iir_filter_tap iir_tap_1
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x1[7:0] : cx1),
.cy(vcoeff_y1),
.x(x),
.y(y),
.z(tap2),
.tap(tap1)
);
wire [39:0] tap2;
iir_filter_tap iir_tap_2
(
.clk(clk),
.reset(reset),
.ce(ce),
.ch(ch),
.cx(use_params ? coeff_x2[7:0] : cx2),
.cy(vcoeff_y2),
.x(x),
.y(y),
.z(0),
.tap(tap2)
);
wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20];
reg ch = 0;
reg [15:0] out_l, out_r, out_m;
reg [15:0] inp, inp_m;
always @(posedge clk) if (ce) begin
if(!stereo) begin
ch <= 0;
inp <= input_l;
out_l <= y_clamp;
out_r <= y_clamp;
end
else begin
ch <= ~ch;
if(ch) begin
out_m <= y_clamp;
inp <= inp_m;
end
else begin
out_l <= out_m;
out_r <= y_clamp;
inp <= input_l;
inp_m <= input_r;
end
end
end
reg [31:0] out;
always @(posedge clk) if (sample_ce) out <= {out_l, out_r};
assign {output_l, output_r} = out;
endmodule
module iir_filter_tap
(
input clk,
input reset,
input ce,
input ch,
input [7:0] cx,
input [23:0] cy,
input [39:0] x,
input [39:0] y,
input [39:0] z,
output [39:0] tap
);
wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy);
function [39:0] x_mul;
input [39:0] x;
begin
x_mul = 0;
if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]};
if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]};
if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]};
if(cx[7]) x_mul = ~x_mul; //cheap NEG
end
endfunction
(* ramstyle = "logic" *) reg [39:0] intreg[2];
always @(posedge clk, posedge reset) begin
if(reset) {intreg[0],intreg[1]} <= 80'd0;
else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z;
end
assign tap = intreg[ch];
endmodule
// simplified IIR 1-tap.
module DC_blocker
(
input clk,
input ce, // 48/96 KHz
input mute,
input sample_rate,
input [15:0] din,
output [15:0] dout
);
wire [39:0] x = {din[15], din, 23'd0};
wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]});
wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]});
wire [39:0] y0 = x0 - x1 + y1;
reg [39:0] x1, y;
always @(posedge clk) if(ce) begin
x1 <= x0;
y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0;
end
assign dout = mute ? 16'd0 : y[38:23];
endmodule

279
sys/mt32pi.sv Normal file
View File

@@ -0,0 +1,279 @@
//
// Communication module to MT32-pi (external MIDI emulator on RPi)
// (C) 2020 Sorgelig, Kitrinx
//
// https://github.com/dwhinham/mt32-pi
//
module mt32pi
(
input CLK_AUDIO,
input CLK_VIDEO,
input CE_PIXEL,
input VGA_VS,
input VGA_DE,
input [6:0] USER_IN,
output [6:0] USER_OUT,
input reset,
input midi_tx,
output midi_rx,
output reg [15:0] mt32_i2s_r,
output reg [15:0] mt32_i2s_l,
output reg mt32_available,
input mt32_mode_req,
input [1:0] mt32_rom_req,
input [7:0] mt32_sf_req,
output reg [7:0] mt32_mode,
output reg [7:0] mt32_rom,
output reg [7:0] mt32_sf,
output reg mt32_newmode,
output reg mt32_lcd_en,
output reg mt32_lcd_pix,
output reg mt32_lcd_update
);
//
// Pin | USB Name | Signal
// ----+----------+--------------
// 0 | D+ | I/O I2C_SDA
// 1 | D- | O TX (midi out)
// 2 | TX- | I I2S_WS (1 == right)
// 3 | GND_d | I I2C_SCL
// 4 | RX+ | I I2S_BCLK
// 5 | RX- | I I2S_DAT
// 6 | TX+ | - none
//
assign USER_OUT[0] = sda_out;
assign USER_OUT[1] = midi_tx;
assign USER_OUT[6:2] = '1;
//
// crossed/straight cable selection
//
generate
genvar i;
for(i = 0; i<2; i++) begin : clk_rate
wire clk_in = i ? USER_IN[6] : USER_IN[4];
reg [4:0] cnt;
always @(posedge CLK_AUDIO) begin : clkr
reg clk_sr, clk, old_clk;
reg [4:0] cnt_tmp;
clk_sr <= clk_in;
if (clk_sr == clk_in) clk <= clk_sr;
if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1;
else cnt <= '1;
old_clk <= clk;
if(~old_clk & clk) begin
cnt <= cnt_tmp;
cnt_tmp <= 0;
end
end
end
reg crossed;
always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt);
endgenerate
wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5];
wire i2s_data = crossed ? USER_IN[5] : USER_IN[2];
wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6];
assign midi_rx = crossed ? USER_IN[6] : USER_IN[4];
//
// i2s receiver
//
always @(posedge CLK_AUDIO) begin : i2s_proc
reg [15:0] i2s_buf = 0;
reg [4:0] i2s_cnt = 0;
reg clk_sr;
reg i2s_clk = 0;
reg old_clk, old_ws;
reg i2s_next = 0;
// Debounce clock
clk_sr <= i2s_bclk;
if (clk_sr == i2s_bclk) i2s_clk <= clk_sr;
// Latch data and ws on rising edge
old_clk <= i2s_clk;
if (i2s_clk && ~old_clk) begin
if (~i2s_cnt[4]) begin
i2s_cnt <= i2s_cnt + 1'd1;
i2s_buf[~i2s_cnt[3:0]] <= i2s_data;
end
// Word Select will change 1 clock before the new word starts
old_ws <= i2s_ws;
if (old_ws != i2s_ws) i2s_next <= 1;
end
if (i2s_next) begin
i2s_next <= 0;
i2s_cnt <= 0;
i2s_buf <= 0;
if (i2s_ws) mt32_i2s_l <= i2s_buf;
else mt32_i2s_r <= i2s_buf;
end
if (reset) begin
i2s_buf <= 0;
mt32_i2s_l <= 0;
mt32_i2s_r <= 0;
end
end
//
// i2c slave
//
reg sda_out;
reg [7:0] lcd_data[1024];
reg lcd_sz;
reg reset_r = 0;
wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1;
wire [7:0] rom_req = {6'd0, mt32_rom_req};
always @(posedge CLK_AUDIO) begin : i2c_slave
reg sda_sr, scl_sr;
reg old_sda, old_scl;
reg sda, scl;
reg [7:0] tmp;
reg [3:0] cnt = 0;
reg [10:0] bcnt = 0;
reg ack;
reg i2c_rw;
reg disp, dispdata;
reg [2:0] div;
div <= div + 1'd1;
if(!div) begin
sda_sr <= USER_IN[0];
if(sda_sr == USER_IN[0]) sda <= sda_sr;
old_sda <= sda;
scl_sr <= USER_IN[3];
if(scl_sr == USER_IN[3]) scl <= scl_sr;
old_scl <= scl;
//start
if(old_scl & scl & old_sda & ~sda) begin
cnt <= 9;
bcnt <= 0;
ack <= 0;
i2c_rw <= 0;
disp <= 0;
dispdata <= 0;
end
//stop
if(old_scl & scl & ~old_sda & sda) begin
cnt <= 0;
if(dispdata) begin
lcd_sz <= ~bcnt[9];
mt32_lcd_update <= ~mt32_lcd_update;
end
end
//data latch
if(~old_scl && scl && cnt) begin
tmp <= {tmp[6:0], sda};
cnt <= cnt - 1'd1;
end
if(!cnt) sda_out <= 1;
//data set
if(old_scl && ~scl) begin
sda_out <= 1;
if(cnt == 1) begin
if(!bcnt) begin
if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin
disp <= (tmp[7:1] == 'h3c);
sda_out <= 0;
mt32_available <= 1;
ack <= 1;
i2c_rw <= tmp[0];
bcnt <= bcnt + 1'd1;
cnt <= 10;
end
else begin
// wrong address, stop
cnt <= 0;
end
end
else if(ack) begin
if(~i2c_rw) begin
if(disp) begin
if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01);
else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp;
end
else begin
if(bcnt == 1) mt32_mode <= tmp;
if(bcnt == 2) mt32_rom <= tmp;
if(bcnt == 3) mt32_sf <= tmp;
if(bcnt == 3) mt32_newmode <= ~mt32_newmode;
end
end
if(~&bcnt) bcnt <= bcnt + 1'd1;
sda_out <= 0;
cnt <= 10;
end
end
else if(i2c_rw && ack && cnt && ~disp) begin
if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2];
if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2];
if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2];
if(bcnt == 3) reset_r <= 0;
end
end
end
if(reset) begin
reset_r <= 1;
mt32_available <= 0;
end
end
always @(posedge CLK_VIDEO) begin
reg old_de, old_vs;
reg [7:0] hcnt;
reg [6:0] vcnt;
reg [7:0] sh;
if(CE_PIXEL) begin
old_de <= VGA_DE;
old_vs <= VGA_VS;
if(~&hcnt) hcnt <= hcnt + 1'd1;
sh <= (sh << 1) | (~old_de & VGA_DE);
if(sh[7]) hcnt <= 0;
if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1;
if(~old_vs & VGA_VS) vcnt <= 0;
mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]);
mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]];
end
end
endmodule

64
sys/osd.v
View File

@@ -38,7 +38,7 @@ reg osd_enable;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infox;
reg [21:0] infoy;
reg [21:0] osd_h;
reg [21:0] osd_t;
@@ -123,31 +123,39 @@ end
reg [2:0] osd_de;
reg osd_pixel;
reg [21:0] v_cnt;
reg v_cnt_half, v_cnt_single, v_cnt_double, v_cnt_triple;
reg [21:0] v_osd_start_h, v_osd_start_s, v_osd_start_d, v_osd_start_t, v_osd_start_q;
reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
// pipeline the comparisons a bit
always @(posedge clk_video) if(ce_pix) begin
v_cnt_half <= v_cnt < osd_t;
v_cnt_single <= v_cnt < 320;
v_cnt_double <= v_cnt < 640;
v_cnt_triple <= v_cnt < 960;
v_cnt_h <= v_cnt < osd_t;
v_cnt_1 <= v_cnt < 320;
v_cnt_2 <= v_cnt < 640;
v_cnt_3 <= v_cnt < 960;
v_cnt_4 <= v_cnt < 1280;
v_osd_start_h <= ((v_cnt-(osd_h_hdr>>1))>>1);
v_osd_start_s <= ((v_cnt-osd_h_hdr)>>1);
v_osd_start_d <= ((v_cnt-(osd_h_hdr<<1))>>1);
v_osd_start_t <= ((v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1);
v_osd_start_q <= ((v_cnt-(osd_h_hdr<<2))>>1);
v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
v_info_start_h <= rot[0] ? infox : infoy;
v_info_start_1 <= rot[0] ? infox : infoy;
v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
end
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [2:0] osd_div;
reg [2:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] dsp_width;
@@ -199,26 +207,30 @@ always @(posedge clk_video) begin
if(~osd_enable) osd_en <= 0;
half <= 0;
if(v_cnt_half) begin
if(v_cnt_h) begin
multiscan <= 0;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_h;
v_osd_start <= info ? v_info_start_h : v_osd_start_h;
half <= 1;
end
else if(v_cnt_single | (rot[0] & v_cnt_double)) begin
else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
multiscan <= 0;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_s;
v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
end
else if(rot[0] ? v_cnt_triple : v_cnt_double) begin
else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
multiscan <= 1;
v_osd_start <= info ? (rot[0] ? (infox<<1) : (infoy<<1)) : v_osd_start_d;
v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
end
else if(v_cnt_triple | rot[0]) begin
else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
multiscan <= 2;
v_osd_start <= info ? (rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1))) : v_osd_start_t;
v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
end
else if(rot[0] | v_cnt_4) begin
multiscan <= 3;
v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
end
else begin
multiscan <= 3;
v_osd_start <= info ? (rot[0] ? (infox<<2) : (infoy<<2)) : v_osd_start_q;
multiscan <= 4;
v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
end
end
end

10
sys/pll.13.qip
View File

@@ -4,9 +4,13 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"

17
sys/pll_audio.13.qip Normal file
View File

@@ -0,0 +1,17 @@
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"

337
sys/pll_audio.qip Normal file
View File

@@ -0,0 +1,337 @@
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlv"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUyODMyMTE2Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTc=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw5LDgsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE3Ljc5MiBNSHosMTUyODMyMTE2Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"]
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"

252
sys/pll_audio.v Normal file
View File

@@ -0,0 +1,252 @@
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll_audio.v
// Generated using ACDS version 17.0 602
`timescale 1 ps / 1 ps
module pll_audio (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
pll_audio_0002 pll_audio_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2020 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="24.576" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll_audio.vo
// RELATED_FILES: pll_audio.v, pll_audio_0002.v

4
sys/pll_audio/pll_audio_0002.qip Normal file
View File

@@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"

87
sys/pll_audio/pll_audio_0002.v Normal file
View File

@@ -0,0 +1,87 @@
`timescale 1ns/10ps
module pll_audio_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("24.576000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule

172
sys/pll_cfg.v
View File

@@ -1,86 +1,86 @@
// megafunction wizard: %Altera PLL Reconfig v17.0%
// GENERATION: XML
// pll_cfg.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_cfg #(
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter reconf_width = 64,
parameter WAIT_FOR_LOCK = 1
) (
input wire mgmt_clk, // mgmt_clk.clk
input wire mgmt_reset, // mgmt_reset.reset
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
input wire mgmt_read, // .read
input wire mgmt_write, // .write
output wire [31:0] mgmt_readdata, // .readdata
input wire [5:0] mgmt_address, // .address
input wire [31:0] mgmt_writedata, // .writedata
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
.reconf_width (reconf_width),
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
) pll_cfg_inst (
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
.mgmt_read (mgmt_read), // .read
.mgmt_write (mgmt_write), // .write
.mgmt_readdata (mgmt_readdata), // .readdata
.mgmt_address (mgmt_address), // .address
.mgmt_writedata (mgmt_writedata), // .writedata
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.mgmt_byteenable (4'b0000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : pll_cfg.vo
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
// megafunction wizard: %Altera PLL Reconfig v17.0%
// GENERATION: XML
// pll_cfg.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_cfg #(
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter reconf_width = 64,
parameter WAIT_FOR_LOCK = 1
) (
input wire mgmt_clk, // mgmt_clk.clk
input wire mgmt_reset, // mgmt_reset.reset
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
input wire mgmt_read, // .read
input wire mgmt_write, // .write
output wire [31:0] mgmt_readdata, // .readdata
input wire [5:0] mgmt_address, // .address
input wire [31:0] mgmt_writedata, // .writedata
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
.reconf_width (reconf_width),
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
) pll_cfg_inst (
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
.mgmt_read (mgmt_read), // .read
.mgmt_write (mgmt_write), // .write
.mgmt_readdata (mgmt_readdata), // .readdata
.mgmt_address (mgmt_address), // .address
.mgmt_writedata (mgmt_writedata), // .writedata
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.mgmt_byteenable (4'b0000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : pll_cfg.vo
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v

4342
sys/pll_cfg/altera_pll_reconfig_core.v
View File

File diff suppressed because it is too large Load Diff

830
sys/pll_cfg/altera_pll_reconfig_top.v
View File

@@ -11,418 +11,418 @@
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = "",
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter WAIT_FOR_LOCK = 1
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
//conditional input
input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
);
localparam NM28_START_REG = 6'b000010;
localparam NM20_START_REG = 9'b000000000;
localparam NM20_MIFSTART_ADDR = 9'b000010000;
localparam MIF_STATE_DONE = 2'b00;
localparam MIF_STATE_START = 2'b01;
localparam MIF_STATE_BUSY = 2'b10;
wire mgmt_byteenable_write;
assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
mgmt_write;
generate
if (device_family == "Arria 10")
begin:nm20_reconfig
if(ENABLE_MIF == 1)
begin:mif_reconfig_20nm // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
//wire mif_user_start; // start signal provided by user to start mif
//reg user_start;
reg [1:0] mif_curstate;
reg [1:0] mif_nextstate;
wire mif_start; //start signal to mif reader
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
//mif base addr is initially specified by the user
assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
//MIF statemachine
always @(posedge mgmt_clk)
begin
if(mgmt_reset)
mif_curstate <= MIF_STATE_DONE;
else
mif_curstate <= mif_nextstate;
end
always @(*)
begin
case (mif_curstate)
MIF_STATE_DONE:
begin
if(mif_start)
mif_nextstate <= MIF_STATE_START;
else
mif_nextstate <= MIF_STATE_DONE;
end
MIF_STATE_START:
begin
mif_nextstate <= MIF_STATE_BUSY;
end
MIF_STATE_BUSY:
begin
if(mif_busy)
mif_nextstate <= MIF_STATE_BUSY;
else
mif_nextstate <= MIF_STATE_DONE;
end
endcase
end
//Mif muxes
always @(*)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
//user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
end
end
twentynm_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) twentynm_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_waitrequest(reconfig_mgmt_waitrequest),
//.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(mif_start),
//outputs
.mif_busy(mif_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_address(reconfig_mgmt_addr),
.mgmt_writedata(reconfig_mgmt_writedata),
// Outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end // End generate reconfig with MIF
else
begin:reconfig_core_20nm
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_address(mgmt_address),
.mgmt_writedata(mgmt_writedata),
// Outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end
end // 20nm reconfig
else
begin:NM28_reconfig
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
end // End 28nm Reconfig
endgenerate
endmodule
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = "",
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter WAIT_FOR_LOCK = 1
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
//conditional input
input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
);
localparam NM28_START_REG = 6'b000010;
localparam NM20_START_REG = 9'b000000000;
localparam NM20_MIFSTART_ADDR = 9'b000010000;
localparam MIF_STATE_DONE = 2'b00;
localparam MIF_STATE_START = 2'b01;
localparam MIF_STATE_BUSY = 2'b10;
wire mgmt_byteenable_write;
assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
mgmt_write;
generate
if (device_family == "Arria 10")
begin:nm20_reconfig
if(ENABLE_MIF == 1)
begin:mif_reconfig_20nm // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
//wire mif_user_start; // start signal provided by user to start mif
//reg user_start;
reg [1:0] mif_curstate;
reg [1:0] mif_nextstate;
wire mif_start; //start signal to mif reader
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
//mif base addr is initially specified by the user
assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
//MIF statemachine
always @(posedge mgmt_clk)
begin
if(mgmt_reset)
mif_curstate <= MIF_STATE_DONE;
else
mif_curstate <= mif_nextstate;
end
always @(*)
begin
case (mif_curstate)
MIF_STATE_DONE:
begin
if(mif_start)
mif_nextstate <= MIF_STATE_START;
else
mif_nextstate <= MIF_STATE_DONE;
end
MIF_STATE_START:
begin
mif_nextstate <= MIF_STATE_BUSY;
end
MIF_STATE_BUSY:
begin
if(mif_busy)
mif_nextstate <= MIF_STATE_BUSY;
else
mif_nextstate <= MIF_STATE_DONE;
end
endcase
end
//Mif muxes
always @(*)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
//user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
end
end
twentynm_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) twentynm_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_waitrequest(reconfig_mgmt_waitrequest),
//.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(mif_start),
//outputs
.mif_busy(mif_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_address(reconfig_mgmt_addr),
.mgmt_writedata(reconfig_mgmt_writedata),
// Outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end // End generate reconfig with MIF
else
begin:reconfig_core_20nm
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_address(mgmt_address),
.mgmt_writedata(mgmt_writedata),
// Outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end
end // 20nm reconfig
else
begin:NM28_reconfig
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
end // End 28nm Reconfig
endgenerate
endmodule

6
sys/pll_hdmi.13.qip
View File

@@ -6,7 +6,11 @@ set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"

512
sys/pll_hdmi.v
View File

@@ -1,256 +1,256 @@
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll_hdmi.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_hdmi (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
pll_hdmi_0002 pll_hdmi_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="148.5" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="65.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="27.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="true" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll_hdmi.vo
// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll_hdmi.v
// Generated using ACDS version 17.0 598
`timescale 1 ps / 1 ps
module pll_hdmi (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
);
pll_hdmi_0002 pll_hdmi_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="148.5" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="65.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="27.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="true" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll_hdmi.vo
// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v

482
sys/pll_hdmi/pll_hdmi_0002.v
View File

@@ -1,241 +1,241 @@
`timescale 1ns/10ps
module pll_hdmi_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(32),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("148.500000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("Cyclone V"),
.pll_subtype("Reconfigurable"),
.m_cnt_hi_div(4),
.m_cnt_lo_div(4),
.n_cnt_hi_div(256),
.n_cnt_lo_div(256),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("true"),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_odd_div_duty_en("false"),
.c_cnt_hi_div0(2),
.c_cnt_lo_div0(1),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("true"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("true"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(2),
.pll_cp_current(20),
.pll_bwctrl(4000),
.pll_output_clk_frequency("445.499999 MHz"),
.pll_fractional_division("3908420153"),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("true")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
);
endmodule
`timescale 1ns/10ps
module pll_hdmi_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(32),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("148.500000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("Cyclone V"),
.pll_subtype("Reconfigurable"),
.m_cnt_hi_div(4),
.m_cnt_lo_div(4),
.n_cnt_hi_div(256),
.n_cnt_lo_div(256),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("true"),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_odd_div_duty_en("false"),
.c_cnt_hi_div0(2),
.c_cnt_lo_div0(1),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("true"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("true"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(2),
.pll_cp_current(20),
.pll_bwctrl(4000),
.pll_output_clk_frequency("445.499999 MHz"),
.pll_fractional_division("3908420153"),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("true")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
);
endmodule

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip
View File

@@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

1
sys/pll_q13.qip
View File

@@ -1,5 +1,6 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]

3
sys/pll_q17.qip
View File

@@ -1,3 +1,4 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]

1073
sys/sd_card.v → sys/sd_card.sv
View File

File diff suppressed because it is too large Load Diff

19
sys/spdif.v
View File

@@ -67,6 +67,8 @@ reg spdif_out_q;
reg [5:0] parity_count_q;
reg channel_status_bit;
//-----------------------------------------------------------------
// Subframe Counter
//-----------------------------------------------------------------
@@ -142,7 +144,7 @@ assign subframe_w[28] = 1'b0; // Valid
assign subframe_w[29] = 1'b0;
// Timeslots 30 = Channel status bit
assign subframe_w[30] = 1'b0;
assign subframe_w[30] = channel_status_bit ; //was constant 1'b0 enabling copy-bit;
// Timeslots 31 = Even Parity bit (31:4)
assign subframe_w[31] = 1'b0;
@@ -150,9 +152,9 @@ assign subframe_w[31] = 1'b0;
//-----------------------------------------------------------------
// Preamble
//-----------------------------------------------------------------
localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;
localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block
localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data
localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block
reg [7:0] preamble_r;
@@ -168,6 +170,15 @@ begin
// Left Channel (but not start of block)?
else
preamble_r = PREAMBLE_X; // X(M)
if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted
channel_status_bit = 1'b1;
else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media
channel_status_bit = 1'b1;
else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r)
channel_status_bit = 1'b1;
else
channel_status_bit = 1'b0; // everything else defaults to 0
end
always @ (posedge rst_i or posedge clk_i )

6
sys/sys.qip
View File

@@ -3,7 +3,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fbpal.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
@@ -18,10 +17,13 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) a
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]

453
sys/sys.tcl
View File

@@ -1,227 +1,226 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# I2C LEDS/BUTTONS
#============================================================
set_location_assignment PIN_U14 -to IO_SCL
set_location_assignment PIN_AG9 -to IO_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S*
#============================================================
# USER PORT
#============================================================
set_location_assignment PIN_AF17 -to USER_IO[6]
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
#============================================================
# SDIO_CD or SPDIF_OUT
#============================================================
set_location_assignment PIN_AH7 -to SDCD_SPDIF
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# SPI SD
#============================================================
set_location_assignment PIN_AE15 -to SD_SPI_CS
set_location_assignment PIN_AH8 -to SD_SPI_MISO
set_location_assignment PIN_AG8 -to SD_SPI_CLK
set_location_assignment PIN_U13 -to SD_SPI_MOSI
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# I2C LEDS/BUTTONS
#============================================================
set_location_assignment PIN_U14 -to IO_SCL
set_location_assignment PIN_AG9 -to IO_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S*
#============================================================
# USER PORT
#============================================================
set_location_assignment PIN_AF17 -to USER_IO[6]
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
#============================================================
# SDIO_CD or SPDIF_OUT
#============================================================
set_location_assignment PIN_AH7 -to SDCD_SPDIF
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# SPI SD
#============================================================
set_location_assignment PIN_AE15 -to SD_SPI_CS
set_location_assignment PIN_AH8 -to SD_SPI_MISO
set_location_assignment PIN_AG8 -to SD_SPI_CLK
set_location_assignment PIN_U13 -to SD_SPI_MOSI
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip

142
sys/sys_analog.tcl
View File

@@ -1,71 +1,71 @@
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# I/O #1
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# I/O #1
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*

100
sys/sys_dual_sdram.tcl
View File

@@ -1,50 +1,50 @@
#============================================================
# Secondary SDRAM
#============================================================
set_location_assignment PIN_Y15 -to SDRAM2_DQ[0]
set_location_assignment PIN_AC24 -to SDRAM2_DQ[1]
set_location_assignment PIN_AA15 -to SDRAM2_DQ[2]
set_location_assignment PIN_AD26 -to SDRAM2_DQ[3]
set_location_assignment PIN_AG28 -to SDRAM2_DQ[4]
set_location_assignment PIN_AF28 -to SDRAM2_DQ[5]
set_location_assignment PIN_AE25 -to SDRAM2_DQ[6]
set_location_assignment PIN_AF27 -to SDRAM2_DQ[7]
set_location_assignment PIN_AG26 -to SDRAM2_DQ[14]
set_location_assignment PIN_AH27 -to SDRAM2_DQ[15]
set_location_assignment PIN_AG25 -to SDRAM2_DQ[13]
set_location_assignment PIN_AH26 -to SDRAM2_DQ[12]
set_location_assignment PIN_AH24 -to SDRAM2_DQ[11]
set_location_assignment PIN_AF25 -to SDRAM2_DQ[10]
set_location_assignment PIN_AG23 -to SDRAM2_DQ[9]
set_location_assignment PIN_AF23 -to SDRAM2_DQ[8]
set_location_assignment PIN_AG24 -to SDRAM2_A[12]
set_location_assignment PIN_AH22 -to SDRAM2_CLK
set_location_assignment PIN_AH21 -to SDRAM2_A[9]
set_location_assignment PIN_AG21 -to SDRAM2_A[11]
set_location_assignment PIN_AH23 -to SDRAM2_A[7]
set_location_assignment PIN_AA20 -to SDRAM2_A[8]
set_location_assignment PIN_AF22 -to SDRAM2_A[5]
set_location_assignment PIN_AE22 -to SDRAM2_A[6]
set_location_assignment PIN_AG20 -to SDRAM2_nWE
set_location_assignment PIN_AF21 -to SDRAM2_A[4]
set_location_assignment PIN_AG19 -to SDRAM2_nCAS
set_location_assignment PIN_AH19 -to SDRAM2_nRAS
set_location_assignment PIN_AG18 -to SDRAM2_nCS
set_location_assignment PIN_AH18 -to SDRAM2_BA[0]
set_location_assignment PIN_AF18 -to SDRAM2_BA[1]
set_location_assignment PIN_AF20 -to SDRAM2_A[10]
set_location_assignment PIN_AG15 -to SDRAM2_A[0]
set_location_assignment PIN_AE20 -to SDRAM2_A[1]
set_location_assignment PIN_AE19 -to SDRAM2_A[2]
set_location_assignment PIN_AE17 -to SDRAM2_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"
#============================================================
# Secondary SDRAM
#============================================================
set_location_assignment PIN_Y15 -to SDRAM2_DQ[0]
set_location_assignment PIN_AC24 -to SDRAM2_DQ[1]
set_location_assignment PIN_AA15 -to SDRAM2_DQ[2]
set_location_assignment PIN_AD26 -to SDRAM2_DQ[3]
set_location_assignment PIN_AG28 -to SDRAM2_DQ[4]
set_location_assignment PIN_AF28 -to SDRAM2_DQ[5]
set_location_assignment PIN_AE25 -to SDRAM2_DQ[6]
set_location_assignment PIN_AF27 -to SDRAM2_DQ[7]
set_location_assignment PIN_AG26 -to SDRAM2_DQ[14]
set_location_assignment PIN_AH27 -to SDRAM2_DQ[15]
set_location_assignment PIN_AG25 -to SDRAM2_DQ[13]
set_location_assignment PIN_AH26 -to SDRAM2_DQ[12]
set_location_assignment PIN_AH24 -to SDRAM2_DQ[11]
set_location_assignment PIN_AF25 -to SDRAM2_DQ[10]
set_location_assignment PIN_AG23 -to SDRAM2_DQ[9]
set_location_assignment PIN_AF23 -to SDRAM2_DQ[8]
set_location_assignment PIN_AG24 -to SDRAM2_A[12]
set_location_assignment PIN_AH22 -to SDRAM2_CLK
set_location_assignment PIN_AH21 -to SDRAM2_A[9]
set_location_assignment PIN_AG21 -to SDRAM2_A[11]
set_location_assignment PIN_AH23 -to SDRAM2_A[7]
set_location_assignment PIN_AA20 -to SDRAM2_A[8]
set_location_assignment PIN_AF22 -to SDRAM2_A[5]
set_location_assignment PIN_AE22 -to SDRAM2_A[6]
set_location_assignment PIN_AG20 -to SDRAM2_nWE
set_location_assignment PIN_AF21 -to SDRAM2_A[4]
set_location_assignment PIN_AG19 -to SDRAM2_nCAS
set_location_assignment PIN_AH19 -to SDRAM2_nRAS
set_location_assignment PIN_AG18 -to SDRAM2_nCS
set_location_assignment PIN_AH18 -to SDRAM2_BA[0]
set_location_assignment PIN_AF18 -to SDRAM2_BA[1]
set_location_assignment PIN_AF20 -to SDRAM2_A[10]
set_location_assignment PIN_AG15 -to SDRAM2_A[0]
set_location_assignment PIN_AE20 -to SDRAM2_A[1]
set_location_assignment PIN_AE19 -to SDRAM2_A[2]
set_location_assignment PIN_AE17 -to SDRAM2_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"

108
sys/sys_top.sdc
View File

@@ -1,48 +1,60 @@
# Specify root clocks
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
set_clock_groups -exclusive \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 }] \
-group [get_clocks { FPGA_CLK2_50 }] \
-group [get_clocks { FPGA_CLK3_50 }]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
set_false_path -to {*_osd|v_cnt*}
set_false_path -to {*_osd|v_osd_start*}
set_false_path -to {*_osd|h_osd_start*}
set_false_path -from {*_osd|v_osd_start*}
set_false_path -from {*_osd|h_osd_start*}
set_false_path -from {*_osd|rot*}
set_false_path -from {*_osd|dsp_width*}
set_false_path -to {*_osd|half}
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
# Specify root clocks
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
set_clock_groups -exclusive \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \
-group [get_clocks { spi_sck}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 }] \
-group [get_clocks { FPGA_CLK2_50 }] \
-group [get_clocks { FPGA_CLK3_50 }]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
set_false_path -to [get_ports {VGA_*}]
set_false_path -to [get_ports {AUDIO_SPDIF}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {width[*] height[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
set_false_path -to {*_osd|v_cnt*}
set_false_path -to {*_osd|v_osd_start*}
set_false_path -to {*_osd|v_info_start*}
set_false_path -to {*_osd|h_osd_start*}
set_false_path -from {*_osd|v_osd_start*}
set_false_path -from {*_osd|v_info_start*}
set_false_path -from {*_osd|h_osd_start*}
set_false_path -from {*_osd|rot*}
set_false_path -from {*_osd|dsp_width*}
set_false_path -to {*_osd|half}
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {aflt_* acx* acy* areset*}
set_false_path -from {ascal|o_ihsize*}
set_false_path -from {ascal|o_ivsize*}
set_false_path -from {ascal|o_format*}
set_false_path -from {ascal|o_hdown}
set_false_path -from {ascal|o_vdown}

831
sys/sys_top.v
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198
sys/video_cleaner.sv
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@@ -1,99 +1,99 @@
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
//optional de
input DE_in,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out,
// optional aligned de
output reg DE_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_HS <= hs;
if(~VGA_HS & hs) VGA_VS <= vs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
DE_out <= DE_in;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
//optional de
input DE_in,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out,
// optional aligned de
output reg DE_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_HS <= hs;
if(~VGA_HS & hs) VGA_VS <= vs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
DE_out <= DE_in;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

463
sys/video_mixer.sv
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@@ -1,225 +1,238 @@
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
//
// altera message_off 10720
// altera message_off 12161
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter GAMMA = 0
)
(
// video clock
// it should be multiple by (ce_pix*4).
input clk_vid,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
inout [21:0] gamma_bus,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
generate
if(GAMMA && HALF_DEPTH) begin
wire [7:0] R_in = mono ? {G,R} : {R,R};
wire [7:0] G_in = mono ? {G,R} : {G,G};
wire [7:0] B_in = mono ? {G,R} : {B,B};
end else begin
wire [DWIDTH:0] R_in = R;
wire [DWIDTH:0] G_in = G;
wire [DWIDTH:0] B_in = B;
end
endgenerate
wire hs_g, vs_g;
wire hb_g, vb_g;
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
generate
if(GAMMA) begin
assign gamma_bus[21] = 1;
gamma_corr gamma(
.clk_sys(gamma_bus[20]),
.clk_vid(clk_vid),
.ce_pix(ce_pix),
.gamma_en(gamma_bus[19]),
.gamma_wr(gamma_bus[18]),
.gamma_wr_addr(gamma_bus[17:8]),
.gamma_value(gamma_bus[7:0]),
.HSync(HSync),
.VSync(VSync),
.HBlank(HBlank),
.VBlank(VBlank),
.RGB_in({R_in,G_in,B_in}),
.HSync_out(hs_g),
.VSync_out(vs_g),
.HBlank_out(hb_g),
.VBlank_out(vb_g),
.RGB_out({R_gamma,G_gamma,B_gamma})
);
end else begin
assign gamma_bus[21] = 0;
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
end
endgenerate
wire [DWIDTH_SD:0] R_sd;
wire [DWIDTH_SD:0] G_sd;
wire [DWIDTH_SD:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
(
.*,
.hs_in(hs_g),
.vs_in(vs_g),
.hb_in(hb_g),
.vb_in(vb_g),
.r_in(R_gamma),
.g_in(G_gamma),
.b_in(B_gamma),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
generate
if(!GAMMA && HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : hs_g);
wire vs = (scandoubler ? vs_sd : vs_g);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_vid) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~hb_g;
wire vde = scandoubler ? ~vb_sd : ~vb_g;
always @(posedge clk_vid) begin
reg old_hde;
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
VGA_R <= {1'b0, r[7:1]};
VGA_G <= {1'b0, g[7:1]};
VGA_B <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
VGA_R <= {2'b00, r[7:2]};
VGA_G <= {2'b00, g[7:2]};
VGA_B <= {2'b00, b[7:2]};
end
default: begin
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
end
endcase
VGA_VS <= vs;
VGA_HS <= hs;
old_hde <= hde;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
end
endmodule
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
//
// altera message_off 10720
// altera message_off 12161
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter GAMMA = 0
)
(
// video clock
// it should be multiple by (ce_pix*4).
input clk_vid,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
inout [21:0] gamma_bus,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
generate
if(GAMMA && HALF_DEPTH) begin
wire [7:0] R_in = mono ? {G,R} : {R,R};
wire [7:0] G_in = mono ? {G,R} : {G,G};
wire [7:0] B_in = mono ? {G,R} : {B,B};
end else begin
wire [DWIDTH:0] R_in = R;
wire [DWIDTH:0] G_in = G;
wire [DWIDTH:0] B_in = B;
end
endgenerate
wire hs_g, vs_g;
wire hb_g, vb_g;
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
generate
if(GAMMA) begin
assign gamma_bus[21] = 1;
gamma_corr gamma(
.clk_sys(gamma_bus[20]),
.clk_vid(clk_vid),
.ce_pix(ce_pix),
.gamma_en(gamma_bus[19]),
.gamma_wr(gamma_bus[18]),
.gamma_wr_addr(gamma_bus[17:8]),
.gamma_value(gamma_bus[7:0]),
.HSync(HSync),
.VSync(VSync),
.HBlank(HBlank),
.VBlank(VBlank),
.RGB_in({R_in,G_in,B_in}),
.HSync_out(hs_g),
.VSync_out(vs_g),
.HBlank_out(hb_g),
.VBlank_out(vb_g),
.RGB_out({R_gamma,G_gamma,B_gamma})
);
end else begin
assign gamma_bus[21] = 0;
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
end
endgenerate
wire [DWIDTH_SD:0] R_sd;
wire [DWIDTH_SD:0] G_sd;
wire [DWIDTH_SD:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
(
.*,
.hs_in(hs_g),
.vs_in(vs_g),
.hb_in(hb_g),
.vb_in(vb_g),
.r_in(R_gamma),
.g_in(G_gamma),
.b_in(B_gamma),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
generate
if(!GAMMA && HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : hs_g);
wire vs = (scandoubler ? vs_sd : vs_g);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_vid) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~hb_g;
wire vde = scandoubler ? ~vb_sd : ~vb_g;
reg [7:0] v_r,v_g,v_b;
reg v_vs,v_hs,v_de;
always @(posedge clk_vid) begin
reg old_hde;
if(ce_pix_out) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
v_r <= {1'b0, r[7:1]};
v_g <= {1'b0, g[7:1]};
v_b <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
v_r <= {2'b00, r[7:2]};
v_g <= {2'b00, g[7:2]};
v_b <= {2'b00, b[7:2]};
end
default: begin
v_r <= r;
v_g <= g;
v_b <= b;
end
endcase
v_vs <= vs;
v_hs <= hs;
old_hde <= hde;
if(~old_hde && hde) v_de <= vde;
if(old_hde && ~hde) v_de <= 0;
end
end
always @(posedge clk_vid) if(ce_pix_out) begin
VGA_R <= v_r;
VGA_G <= v_g;
VGA_B <= v_b;
VGA_HS <= v_hs;
VGA_VS <= v_vs;
VGA_DE <= v_de;
end
endmodule