misteraddons 5020187e7d P2 Joy as optional right stroke for Water Match (#42)
* Second Joystick as right stroke in Water Match

* Guard secondary joystick option for non-twinstick games
2026-02-16 13:26:47 +08:00
2021-06-18 06:52:14 +08:00
2024-06-02 22:28:39 -06:00
2019-12-16 23:19:47 +09:00
2020-05-31 03:00:44 +09:00
2019-12-16 18:58:06 +09:00
2019-12-16 18:58:06 +09:00

Arcade: SEGA System 1 for MiSTer

by MiSTer-X

Specifications

  • T80/T80s - Version : 0242
  • Z80 compatible microprocessor core - Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  • 2020/01/08 Impl. Trigger 3 (for SEGA Ninja)

Supported Games

Currently implemented:

  • 4-D Warriors
  • Block Gal
  • Bullfight
  • Flicky
  • I'm Sorry
  • Mister Viking
  • My Hero
  • Pitfall II
  • Rafflesia
  • Regulus
  • Sega Ninja
  • Spatter
  • Star Jacker
  • Swat
  • TeddyBoy Blues
  • Up'n Down
  • Water Match
  • Wonder Boy

Sega System 1 games currently not yet implemented:

  • Choplifter
  • Gardia
  • Noboranka / Zippy Bug

High score save/load

  • To save your scores use the 'Save Settings' option in the OSD
  • All games supported except Water Match and Wonder Boy

ROM Files Instructions

ROMs are not included! In order to use this arcade core, you will need to provide the correct ROM file yourself.

Find this zip file somewhere. You need to find the file exactly as required. Check the .mra file in a text editor for more information.
Do not rename other zip files even if they also represent the same game - they are not compatible!
The name of zip is taken from M.A.M.E. project, so you can get more info about hashes and contained files there.

How to install:

  1. Update MiSTer binary to v200106 or later
  2. copy releases/*.mra to /media/fat/_Arcade
  3. copy releases/*.rbf to /media/fat/_Arcade/cores
  4. copy ROM zip files to /media/fat/_Arcade/mame

Be sure to use the MRA file in "releases" of this repository.
It does not guarantee the operation when using other MRA files.

Description
Sega System 1 for MiSTer
Readme GPL-3.0 15 MiB
Languages
Verilog 45.7%
VHDL 33.3%
SystemVerilog 18.1%
Tcl 2.8%