mirror of
https://github.com/MiSTer-devel/Arcade-RallyX_MiSTer.git
synced 2026-04-19 03:03:09 +00:00
466 lines
11 KiB
Systemverilog
466 lines
11 KiB
Systemverilog
// Arcade: New Rally-X
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//
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// Original implimentation and port to MiSTer by MiSTer-X 2019
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [48:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
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output [12:0] VIDEO_ARX,
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output [12:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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output VGA_DISABLE, // analog out is off
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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output HDMI_BOB_DEINT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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`ifdef MISTER_FB_PALETTE
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`ifdef MISTER_DUAL_SDRAM
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//Secondary SDRAM
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//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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///////// Default values for ports not used in this core /////////
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign VGA_DISABLE = 0;
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assign USER_OUT = '1;
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assign LED_USER = ioctl_download;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign AUDIO_MIX = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign HDMI_BOB_DEINT = 0;
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wire [1:0] ar = status[17:16];
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assign VIDEO_ARX = (!ar) ? 8'd4 : (ar - 1'd1);
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assign VIDEO_ARY = (!ar) ? 8'd3 : 12'd0;
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`include "build_id.v"
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localparam CONF_STR = {
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"A.NRALLYX;;",
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"H0OGH,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
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"-;",
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//"OE,Cabinet,Upright,Cocktail;"
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//"-;",
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"DIP;",
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"-;",
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"H1OR,Autosave Hiscores,Off,On;",
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"P1,Pause options;",
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"P1OP,Pause when OSD is open,On,Off;",
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"P1OQ,Dim video after 10s,On,Off;",
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"-;",
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"R0,Reset;",
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"J1,Smoke,Start 1P,Start 2P,Coin,Pause;",
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"V,v",`BUILD_DATE
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};
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reg [7:0] dips;
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always @(posedge clk_sys)
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if (ioctl_wr && (ioctl_index==254) && (ioctl_addr==0))
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dips <= ioctl_dout;
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//////////////////// CLOCKS ///////////////////
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wire clk_hdmi;
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wire clk_24M;
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wire clk_sys = clk_24M;
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pll pll
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(
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.rst(0),
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.refclk(CLK_50M),
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.outclk_0(clk_hdmi),
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.outclk_1(clk_24M)
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);
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///////////////////////////////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire forced_scandoubler;
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wire [21:0] gamma_bus;
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wire direct_video;
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wire video_rotated;
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wire ioctl_download;
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wire ioctl_upload;
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wire ioctl_upload_req;
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wire ioctl_wr;
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wire [7:0] ioctl_index;
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wire [24:0] ioctl_addr;
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wire [7:0] ioctl_din;
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wire [7:0] ioctl_dout;
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wire [15:0] joystk1, joystk2;
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hps_io #(.CONF_STR(CONF_STR)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.buttons(buttons),
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.status(status),
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.forced_scandoubler(forced_scandoubler),
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.video_rotated(video_rotated),
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.gamma_bus(gamma_bus),
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.direct_video(direct_video),
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.status_menumask({~hs_configured,direct_video}),
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.ioctl_download(ioctl_download),
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.ioctl_upload(ioctl_upload),
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.ioctl_upload_req(ioctl_upload_req),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_din(ioctl_din),
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.ioctl_index(ioctl_index),
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.joystick_0(joystk1),
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.joystick_1(joystk2)
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);
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wire bCabinet = 1'b0; // (upright only)
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wire m_up2 = joystk2[3];
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wire m_down2 = joystk2[2];
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wire m_left2 = joystk2[1];
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wire m_right2 = joystk2[0];
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wire m_trig2 = joystk2[4];
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wire m_start1 = joystk1[5] | joystk2[5] ;
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wire m_start2 = joystk1[6] | joystk2[6] ;
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wire m_up1 = joystk1[3] | (bCabinet ? 1'b0 : m_up2);
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wire m_down1 = joystk1[2] | (bCabinet ? 1'b0 : m_down2);
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wire m_left1 = joystk1[1] | (bCabinet ? 1'b0 : m_left2);
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wire m_right1 = joystk1[0] | (bCabinet ? 1'b0 : m_right2);
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wire m_trig1 = joystk1[4] | (bCabinet ? 1'b0 : m_trig2);
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wire m_coin1 = joystk1[7];
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wire m_coin2 = joystk2[7];
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wire m_pause = joystk1[8] | joystk2[8];
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// PAUSE SYSTEM
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wire pause_cpu;
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wire [11:0] rgb_out;
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pause #(4,4,4,24) pause (
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.*,
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.reset(iRST),
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.user_button(m_pause),
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.pause_request(hs_pause),
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.options(~status[26:25])
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);
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///////////////////////////////////////////////////
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wire hblank, vblank;
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wire ce_vid;
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wire hs, vs;
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wire [3:0] r,g,b;
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reg ce_pix;
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always @(posedge clk_hdmi) begin
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reg old_clk;
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old_clk <= ce_vid;
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ce_pix <= old_clk & ~ce_vid;
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end
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arcade_video #(288,12) arcade_video
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(
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.*,
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.clk_video(clk_hdmi),
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.RGB_in(rgb_out),
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.HBlank(hblank),
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.VBlank(vblank),
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.HSync(~hs),
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.VSync(~vs),
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.fx(0)
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);
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wire PCLK;
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wire [8:0] HPOS,VPOS;
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wire [11:0] POUT;
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HVGEN hvgen
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(
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.HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
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.oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs)
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);
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assign ce_vid = PCLK;
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wire [15:0] AOUT;
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assign AUDIO_L = AOUT;
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assign AUDIO_R = AUDIO_L;
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assign AUDIO_S = 0; // unsigned PCM
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///////////////////////////////////////////////////
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wire rom_download = ioctl_download & !ioctl_index;
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wire iRST = RESET | status[0] | buttons[1] | rom_download;
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// Note that bit 0 on controller 1 in the real hardware is the service indicator,
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// which is mapped into the dip register bit 0. Dip 0 freezes the game, which is
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// implemented in hardware and not mapped into the dip register.
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wire [7:0] iCTR1 = ~{ m_coin1, m_start1, m_up1, m_down1, m_right1, m_left1, m_trig1, 1'b0 };
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wire [7:0] iCTR2 = ~{ m_coin2, m_start2, m_up2, m_down2, m_right2, m_left2, m_trig2, bCabinet };
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wire [7:0] oPIX;
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wire [7:0] oSND;
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fpga_NRX GameCore (
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.RESET(iRST),.CLK24M(clk_24M),
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.HP(HPOS),.VP(VPOS),.PCLK(PCLK),
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.POUT(oPIX),.SND(oSND),
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.DSW(~dips),.CTR1(iCTR1),.CTR2(iCTR2),
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.ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr & rom_download),
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.pause(pause_cpu),
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.hs_address(hs_address),
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.hs_data_in(hs_data_in),
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.hs_data_out(hs_data_out),
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.hs_write(hs_write_enable),
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.hs_access(hs_access_read|hs_access_write)
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);
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// HISCORE SYSTEM
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wire [15:0]hs_address;
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wire [7:0] hs_data_in;
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wire [7:0] hs_data_out;
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wire hs_write_enable;
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wire hs_access_read;
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wire hs_access_write;
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wire hs_pause;
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wire hs_configured;
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hiscore #(
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.HS_ADDRESSWIDTH(16),
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.HS_SCOREWIDTH(6),
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.CFG_ADDRESSWIDTH(2),
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.CFG_LENGTHWIDTH(2)
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) hi (
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.*,
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.clk(clk_sys),
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.reset(iRST),
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.paused(pause_cpu),
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.autosave(status[27]),
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.ram_address(hs_address),
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.data_from_ram(hs_data_out),
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.data_to_ram(hs_data_in),
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.data_from_hps(ioctl_dout),
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.data_to_hps(ioctl_din),
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.ram_write(hs_write_enable),
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.ram_intent_read(hs_access_read),
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.ram_intent_write(hs_access_write),
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.pause_cpu(hs_pause),
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.configured(hs_configured)
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);
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assign POUT = {oPIX[7:6],2'b00,oPIX[5:3],1'b0,oPIX[2:0],1'b0};
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assign AOUT = {oSND,8'h0};
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endmodule
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module HVGEN
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(
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output [8:0] HPOS,
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output [8:0] VPOS,
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input PCLK,
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input [11:0] iRGB,
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output reg [11:0] oRGB,
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output reg HBLK = 1,
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output reg VBLK = 1,
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output reg HSYN = 1,
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output reg VSYN = 1
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);
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reg [8:0] hcnt = 0;
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reg [8:0] vcnt = 0;
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assign HPOS = hcnt;
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assign VPOS = vcnt;
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always @(posedge PCLK) begin
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case (hcnt)
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288: begin HBLK <= 1; hcnt <= hcnt + 9'd1; end
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311: begin HSYN <= 0; hcnt <= hcnt + 9'd1; end
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342: begin HSYN <= 1; hcnt <= 9'd471; end
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511: begin HBLK <= 0; hcnt <= 9'd0;
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case (vcnt)
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223: begin VBLK <= 1; vcnt <= vcnt + 9'd1; end
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226: begin VSYN <= 0; vcnt <= vcnt + 9'd1; end
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233: begin VSYN <= 1; vcnt <= 9'd483; end
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511: begin VBLK <= 0; vcnt <= 9'd0; end
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default: vcnt <= vcnt + 9'd1;
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endcase
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end
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default: hcnt <= hcnt + 9'd1;
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endcase
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oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
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end
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endmodule
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