first check in

.gitignore

@@ -0,0 +1,40 @@
+db
+greybox_tmp
+incremental_db
+output_files
+simulation
+hc_output
+scaler
+hps_isw_handoff
+vip
+*_sim
+.qsys_edit
+PLLJ_PLLSPE_INFO.txt
+*.bak
+*.orig
+*.rej
+*.qdf
+*.rpt
+*.smsg
+*.summary
+*.done
+*.jdi
+*.pin
+*.sof
+*.qws
+*.ppf
+*.ddb
+build_id.v
+c5_pin_model_dump.txt
+*.sopcinfo
+*.csv
+*.f
+*.cmp
+*.sip
+*.spd
+*.bsf
+*~
+*.xml
+*.cdf
+*.qarlog
+qar_info.json

Arcade-RallyX.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+# Date created = 11:35:41  April 26, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.1"
+DATE = "11:35:41  April 26, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Arcade-RallyX"

Arcade-RallyX.qsf

@@ -0,0 +1,371 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
+# Date created = 01:53:32  April 20, 2017
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
+set_global_assignment -name SEED 1
+
+#============================================================
+# ADC
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_location_assignment PIN_U9 -to ADC_CONVST
+set_location_assignment PIN_V10 -to ADC_SCK
+set_location_assignment PIN_AC4 -to ADC_SDI
+set_location_assignment PIN_AD4 -to ADC_SDO
+
+#============================================================
+# ARDUINO
+#============================================================
+set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
+set_location_assignment PIN_U14 -to ARDUINO_IO[4]
+set_location_assignment PIN_U13 -to ARDUINO_IO[5]
+set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
+set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
+set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
+
+#============================================================
+# USER PORT
+#============================================================
+set_location_assignment PIN_AF15 -to USER_IO[5]
+set_location_assignment PIN_AG16 -to USER_IO[4]
+set_location_assignment PIN_AH11 -to USER_IO[3]
+set_location_assignment PIN_AH12 -to USER_IO[2]
+set_location_assignment PIN_AH9 -to USER_IO[1]
+set_location_assignment PIN_AG11 -to USER_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
+
+
+#============================================================
+# SDIO
+#============================================================
+set_location_assignment PIN_AF25 -to SDIO_DAT[0]
+set_location_assignment PIN_AF23 -to SDIO_DAT[1]
+set_location_assignment PIN_AD26 -to SDIO_DAT[2]
+set_location_assignment PIN_AF28 -to SDIO_DAT[3]
+set_location_assignment PIN_AF27 -to SDIO_CMD
+set_location_assignment PIN_AH26 -to SDIO_CLK
+set_location_assignment PIN_AH7 -to SDIO_CD
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_AE17 -to VGA_R[0]
+set_location_assignment PIN_AE20 -to VGA_R[1]
+set_location_assignment PIN_AF20 -to VGA_R[2]
+set_location_assignment PIN_AH18 -to VGA_R[3]
+set_location_assignment PIN_AH19 -to VGA_R[4]
+set_location_assignment PIN_AF21 -to VGA_R[5]
+
+set_location_assignment PIN_AE19 -to VGA_G[0]
+set_location_assignment PIN_AG15 -to VGA_G[1]
+set_location_assignment PIN_AF18 -to VGA_G[2]
+set_location_assignment PIN_AG18 -to VGA_G[3]
+set_location_assignment PIN_AG19 -to VGA_G[4]
+set_location_assignment PIN_AG20 -to VGA_G[5]
+
+set_location_assignment PIN_AG21 -to VGA_B[0]
+set_location_assignment PIN_AA20 -to VGA_B[1]
+set_location_assignment PIN_AE22 -to VGA_B[2]
+set_location_assignment PIN_AF22 -to VGA_B[3]
+set_location_assignment PIN_AH23 -to VGA_B[4]
+set_location_assignment PIN_AH21 -to VGA_B[5]
+
+set_location_assignment PIN_AH22 -to VGA_HS
+set_location_assignment PIN_AG24 -to VGA_VS
+
+set_location_assignment PIN_AH27 -to VGA_EN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
+
+#============================================================
+# AUDIO
+#============================================================
+set_location_assignment PIN_AC24 -to AUDIO_L
+set_location_assignment PIN_AE25 -to AUDIO_R
+set_location_assignment PIN_AG26 -to AUDIO_SPDIF
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_Y11 -to SDRAM_A[0]
+set_location_assignment PIN_AA26 -to SDRAM_A[1]
+set_location_assignment PIN_AA13 -to SDRAM_A[2]
+set_location_assignment PIN_AA11 -to SDRAM_A[3]
+set_location_assignment PIN_W11 -to SDRAM_A[4]
+set_location_assignment PIN_Y19 -to SDRAM_A[5]
+set_location_assignment PIN_AB23 -to SDRAM_A[6]
+set_location_assignment PIN_AC23 -to SDRAM_A[7]
+set_location_assignment PIN_AC22 -to SDRAM_A[8]
+set_location_assignment PIN_C12 -to SDRAM_A[9]
+set_location_assignment PIN_AB26 -to SDRAM_A[10]
+set_location_assignment PIN_AD17 -to SDRAM_A[11]
+set_location_assignment PIN_D12 -to SDRAM_A[12]
+set_location_assignment PIN_Y17 -to SDRAM_BA[0]
+set_location_assignment PIN_AB25 -to SDRAM_BA[1]
+
+set_location_assignment PIN_E8 -to SDRAM_DQ[0]
+set_location_assignment PIN_V12 -to SDRAM_DQ[1]
+set_location_assignment PIN_D11 -to SDRAM_DQ[2]
+set_location_assignment PIN_W12 -to SDRAM_DQ[3]
+set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
+set_location_assignment PIN_D8 -to SDRAM_DQ[5]
+set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
+set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
+set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
+set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
+set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
+set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
+set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
+set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
+set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
+set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
+set_location_assignment PIN_AG13 -to SDRAM_DQML
+set_location_assignment PIN_AF13 -to SDRAM_DQMH
+
+set_location_assignment PIN_AD20 -to SDRAM_CLK
+set_location_assignment PIN_AG10 -to SDRAM_CKE
+
+set_location_assignment PIN_AA19 -to SDRAM_nWE
+set_location_assignment PIN_AA18 -to SDRAM_nCAS
+set_location_assignment PIN_Y18 -to SDRAM_nCS
+set_location_assignment PIN_W14 -to SDRAM_nRAS
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
+
+#============================================================
+# I/O
+#============================================================
+set_location_assignment PIN_Y15 -to LED_USER
+set_location_assignment PIN_AA15 -to LED_HDD
+set_location_assignment PIN_AG28 -to LED_POWER
+
+set_location_assignment PIN_AH24 -to BTN_USER
+set_location_assignment PIN_AG25 -to BTN_OSD
+set_location_assignment PIN_AG23 -to BTN_RESET
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
+set_location_assignment PIN_V11 -to FPGA_CLK1_50
+set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_E11 -to FPGA_CLK3_50
+
+#============================================================
+# HDMI
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
+set_location_assignment PIN_U10 -to HDMI_I2C_SCL
+set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
+set_location_assignment PIN_T13 -to HDMI_I2S
+set_location_assignment PIN_T11 -to HDMI_LRCLK
+set_location_assignment PIN_U11 -to HDMI_MCLK
+set_location_assignment PIN_T12 -to HDMI_SCLK
+set_location_assignment PIN_AG5 -to HDMI_TX_CLK
+set_location_assignment PIN_AD19 -to HDMI_TX_DE
+set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
+set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
+set_location_assignment PIN_W8 -to HDMI_TX_D[2]
+set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
+set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
+set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
+set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
+set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
+set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
+set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
+set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
+set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
+set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
+set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
+set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
+set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
+set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
+set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
+set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
+set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
+set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
+set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
+set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
+set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
+set_location_assignment PIN_T8 -to HDMI_TX_HS
+set_location_assignment PIN_AF11 -to HDMI_TX_INT
+set_location_assignment PIN_V13 -to HDMI_TX_VS
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_AH17 -to KEY[0]
+set_location_assignment PIN_AH16 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+set_location_assignment PIN_W15 -to LED[0]
+set_location_assignment PIN_AA24 -to LED[1]
+set_location_assignment PIN_V16 -to LED[2]
+set_location_assignment PIN_V15 -to LED[3]
+set_location_assignment PIN_AF26 -to LED[4]
+set_location_assignment PIN_AE26 -to LED[5]
+set_location_assignment PIN_Y16 -to LED[6]
+set_location_assignment PIN_AA23 -to LED[7]
+
+#============================================================
+# SW
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_location_assignment PIN_Y24 -to SW[0]
+set_location_assignment PIN_W24 -to SW[1]
+set_location_assignment PIN_W21 -to SW[2]
+set_location_assignment PIN_W20 -to SW[3]
+
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
+
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER OFF
+set_global_assignment -name VHDL_FILE src/cpu/T80s.vhd
+set_global_assignment -name VHDL_FILE src/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE src/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE src/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE src/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE src/cpu/T80.vhd
+set_global_assignment -name VERILOG_FILE src/rams.v
+set_global_assignment -name VERILOG_FILE src/nrx_video.v
+set_global_assignment -name VERILOG_FILE src/nrx_sprite.v
+set_global_assignment -name VERILOG_FILE src/nrx_sound.v
+set_global_assignment -name QIP_FILE src/LINEBUF.qip
+set_global_assignment -name VERILOG_FILE src/fpga_nrx.v
+set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-RallyX.sv"
+set_global_assignment -name CDF_FILE jtag.cdf
+set_global_assignment -name QIP_FILE sys/sys.qip
+set_global_assignment -name QIP_FILE sys/pll.qip
+set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
+set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade-RallyX.srf

@@ -0,0 +1,29 @@
+{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface.  Export the driver(s) of HPS.h2f_reset" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface.  Export the driver(s) of HPS.h2f_reset" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1.  The extra bits will be ignored." {  } {  } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16.  The extra bits will be ignored." {  } {  } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_cvo_mode_banks.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

Arcade-RallyX.sv

@@ -0,0 +1,335 @@
+//============================================================================
+//  Arcade: New Rally-X
+//
+//  Original implimentation and port to MiSTer by MiSTer-X 2019
+//============================================================================
+
+//`define ALLOW_COIN
+
+module emu
+(
+	//Master input clock
+	input         CLK_50M,
+
+	//Async reset from top-level module.
+	//Can be used as initial reset.
+	input         RESET,
+
+	//Must be passed to hps_io module
+	inout  [44:0] HPS_BUS,
+
+	//Base video clock. Usually equals to CLK_SYS.
+	output        VGA_CLK,
+
+	//Multiple resolutions are supported using different VGA_CE rates.
+	//Must be based on CLK_VIDEO
+	output        VGA_CE,
+
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,    // = ~(VBlank | HBlank)
+
+	//Base video clock. Usually equals to CLK_SYS.
+	output        HDMI_CLK,
+
+	//Multiple resolutions are supported using different HDMI_CE rates.
+	//Must be based on CLK_VIDEO
+	output        HDMI_CE,
+
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,   // = ~(VBlank | HBlank)
+	output  [1:0] HDMI_SL,   // scanlines fx
+
+	//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
+	output  [7:0] HDMI_ARX,
+	output  [7:0] HDMI_ARY,
+
+	output        LED_USER,  // 1 - ON, 0 - OFF.
+
+	// b[1]: 0 - LED status is system status OR'd with b[0]
+	//       1 - LED status is controled solely by b[0]
+	// hint: supply 2'b00 to let the system control the LED.
+	output  [1:0] LED_POWER,
+	output  [1:0] LED_DISK,
+
+	output [15:0] AUDIO_L,
+	output [15:0] AUDIO_R,
+	output        AUDIO_S    // 1 - signed audio samples, 0 - unsigned
+);
+
+assign LED_USER  = ioctl_download;
+assign LED_DISK  = 0;
+assign LED_POWER = 0;
+
+assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
+assign HDMI_ARY = status[1] ? 8'd9  : 8'd3;
+
+`include "build_id.v" 
+localparam CONF_STR = {
+	"A.NRALLYX;;",
+
+	"F,rom;",		// allow loading of alternate ROMs
+	"-;",
+	"O1,Aspect Ratio,Original,Wide;",
+	"-;",
+	//"OE,Cabinet,Upright,Cocktail;",
+	"O8A,Difficulty,M1,M2,M3,M4,M5,M6,M7,M8;",
+	"OBC,Bonus Life,M1,M2,M3,Nothing;",
+	"OF,Service Mode,Off,On;",
+	"-;",
+	"R0,Reset;",
+`ifdef ALLOW_COIN
+	"J1,Smoke,Start 1P,Start 2P,Coin;",
+`else
+	"J1,Smoke,Start 1P,Start 2P;",
+`endif
+	"V,v",`BUILD_DATE
+};
+
+
+////////////////////   CLOCKS   ///////////////////
+
+wire clk_hdmi;
+wire clk_24M;
+wire clk_sys = clk_24M;
+
+pll pll
+(
+	.rst(0),
+	.refclk(CLK_50M),
+	.outclk_0(clk_hdmi),
+	.outclk_1(clk_24M)
+);
+
+///////////////////////////////////////////////////
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire        forced_scandoubler;
+
+wire        ioctl_download;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+
+wire [10:0] ps2_key;
+wire [15:0] joystk1, joystk2;
+
+hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
+(
+	.clk_sys(clk_sys),
+	.HPS_BUS(HPS_BUS),
+
+	.conf_str(CONF_STR),
+
+	.buttons(buttons),
+	.status(status),
+	.forced_scandoubler(forced_scandoubler),
+
+	.ioctl_download(ioctl_download),
+	.ioctl_wr(ioctl_wr),
+	.ioctl_addr(ioctl_addr),
+	.ioctl_dout(ioctl_dout),
+
+	.joystick_0(joystk1),
+	.joystick_1(joystk2),
+	.ps2_key(ps2_key)
+);
+
+wire       pressed = ps2_key[9];
+wire [8:0] code    = ps2_key[8:0];
+always @(posedge clk_sys) begin
+	reg old_state;
+	old_state <= ps2_key[10];
+	
+	if(old_state != ps2_key[10]) begin
+		casex(code)
+			'hX75: btn_up          <= pressed; // up
+			'hX72: btn_down        <= pressed; // down
+			'hX6B: btn_left        <= pressed; // left
+			'hX74: btn_right       <= pressed; // right
+			'h029: btn_fire        <= pressed; // space
+			'h014: btn_fire        <= pressed; // ctrl
+			'h005: btn_one_player  <= pressed; // F1
+			'h006: btn_two_players <= pressed; // F2
+
+			// JPAC/IPAC/MAME Style Codes
+			'h016: btn_start_1     <= pressed; // 1
+			'h01E: btn_start_2     <= pressed; // 2
+			'h02E: btn_coin_1      <= pressed; // 5
+			'h036: btn_coin_2      <= pressed; // 6
+			'h02D: btn_up_2        <= pressed; // R
+			'h02B: btn_down_2      <= pressed; // F
+			'h023: btn_left_2      <= pressed; // D
+			'h034: btn_right_2     <= pressed; // G
+			'h01C: btn_fire_2      <= pressed; // A
+		endcase
+	end
+end
+
+reg btn_up    = 0;
+reg btn_down  = 0;
+reg btn_right = 0;
+reg btn_left  = 0;
+reg btn_fire  = 0;
+reg btn_one_player  = 0;
+reg btn_two_players = 0;
+
+reg btn_start_1 = 0;
+reg btn_start_2 = 0;
+reg btn_coin_1  = 0;
+reg btn_coin_2  = 0;
+reg btn_up_2    = 0;
+reg btn_down_2  = 0;
+reg btn_left_2  = 0;
+reg btn_right_2 = 0;
+reg btn_fire_2  = 0;
+
+
+wire bCabinet  = 1'b0; //status[14];
+
+wire m_up2     = btn_up_2    | joystk2[3];
+wire m_down2   = btn_down_2  | joystk2[2];
+wire m_left2   = btn_left_2  | joystk2[1];
+wire m_right2  = btn_right_2 | joystk2[0];
+wire m_smoke2  = btn_fire_2  | joystk2[4];
+
+wire m_start1  = btn_one_player  | joystk1[5] | joystk2[5];
+wire m_start2  = btn_two_players | joystk1[6] | joystk2[6];
+
+wire m_up1     = btn_up      | joystk1[3] | (bCabinet ? 1'b0 : m_up2);
+wire m_down1   = btn_down    | joystk1[2] | (bCabinet ? 1'b0 : m_down2);
+wire m_left1   = btn_left    | joystk1[1] | (bCabinet ? 1'b0 : m_left2);
+wire m_right1  = btn_right   | joystk1[0] | (bCabinet ? 1'b0 : m_right2);
+wire m_smoke1  = btn_fire    | joystk1[4] | (bCabinet ? 1'b0 : m_smoke2);
+
+`ifdef ALLOW_COIN
+wire m_coin1   = btn_coin_1  | joystk1[7];
+wire m_coin2   = btn_coin_2  | joystk2[7];
+`else
+wire m_coin1   = m_start1    | m_start2;
+wire m_coin2   = 1'b0;
+`endif
+
+
+///////////////////////////////////////////////////
+
+wire hblank, vblank;
+wire ce_vid;
+wire hs, vs;
+wire [3:0] r,g,b;
+
+reg ce_pix;
+always @(posedge clk_hdmi) begin
+	reg old_clk;
+	old_clk <= ce_vid;
+	ce_pix  <= old_clk & ~ce_vid;
+end
+
+arcade_rotate_fx #(288,224,12) arcade_video
+(
+	.*,
+
+	.clk_video(clk_hdmi),
+
+	.RGB_in({r,g,b}),
+	.HBlank(hblank),
+	.VBlank(vblank),
+	.HSync(~hs),
+	.VSync(~vs),
+
+	.fx(0),
+	.no_rotate(1'b1)
+);
+
+wire			PCLK;
+wire  [8:0] HPOS,VPOS;
+wire [11:0] POUT;
+HVGEN hvgen
+(
+	.HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
+	.oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs)
+);
+assign ce_vid = PCLK;
+
+
+wire [15:0] AOUT;
+assign AUDIO_L = AOUT;
+assign AUDIO_R = AUDIO_L;
+assign AUDIO_S = 0; // unsigned PCM
+
+
+///////////////////////////////////////////////////
+
+wire			iRST  = RESET | status[0] | buttons[1] | ioctl_download;
+
+wire  [7:0] iDSW  = ~{ 2'b00, status[10:8], status[12:11], status[15] };
+wire  [7:0] iCTR1 = ~{ m_coin1, m_start1, m_up1, m_down1, m_right1, m_left1, m_smoke1, 1'b0 };
+wire  [7:0] iCTR2 = ~{ m_coin2, m_start2, m_up2, m_down2, m_right2, m_left2, m_smoke2, bCabinet };
+
+wire  [7:0] oPIX;
+wire  [7:0] oSND;
+
+fpga_NRX GameCore ( 
+	.RESET(iRST),.CLK24M(clk_24M),
+	.HP(HPOS),.VP(VPOS),.PCLK(PCLK),
+	.POUT(oPIX),.SND(oSND),
+	.DSW(iDSW),.CTR1(iCTR1),.CTR2(iCTR2),
+	
+	.ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
+);
+
+assign POUT = {oPIX[7:6],2'b00,oPIX[5:3],1'b0,oPIX[2:0],1'b0};
+assign AOUT = {oSND,8'h0};
+
+endmodule
+
+
+module HVGEN
+(
+	output  [8:0]		HPOS,
+	output  [8:0]		VPOS,
+	input 				PCLK,
+	input	 [11:0]		iRGB,
+
+	output reg [11:0]	oRGB,
+	output reg			HBLK = 1,
+	output reg			VBLK = 1,
+	output reg			HSYN = 1,
+	output reg			VSYN = 1
+);
+
+reg [8:0] hcnt = 0;
+reg [8:0] vcnt = 0;
+
+assign HPOS = hcnt;
+assign VPOS = vcnt;
+
+always @(posedge PCLK) begin
+	case (hcnt)
+		287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end
+		311: begin HSYN <= 1; hcnt <= hcnt+1; end
+		383: begin
+			HBLK <= 0; HSYN <= 1; hcnt <= 0;
+			case (vcnt)
+				223: begin VBLK <= 1; vcnt <= vcnt+1; end
+				226: begin VSYN <= 0; vcnt <= vcnt+1; end
+				233: begin VSYN <= 1; vcnt <= vcnt+1; end
+				262: begin VBLK <= 0; vcnt <= 0; end
+				default: vcnt <= vcnt+1;
+			endcase
+		end
+		default: hcnt <= hcnt+1;
+	endcase
+	oRGB <= (HBLK|VBLK|(HPOS<=1)) ? 12'h0 : iRGB;
+end
+
+endmodule
+

LICENSE

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
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+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
+or can get the source code.  And you must show them these terms so they
+know their rights.
+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
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+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

README.txt

@@ -0,0 +1,48 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: New Rally-X  port to MiSTer by MiSTer-X
+-- 18 September 2019
+-- 
+---------------------------------------------------------------------------------
+-- FPGA New Rally-X for Spartan-3 Starter Board
+------------------------------------------------
+-- Copyright (c) 2005 MiSTer-X
+---------------------------------------------------------------------------------
+-- T80/T80s - Version : 0242
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F2          : Coin + Start 2 players
+--   F1          : Coin + Start 1 player
+--   UP,DOWN,LEFT,RIGHT arrows : Movements
+--   SPACE,CTRL  : Smoke
+--
+--
+-- Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+                                *** Attention ***
+
+ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
+
+Find this zip file somewhere. You need to find the file exactly as required.
+Do not rename other zip files even if they also represent the same game - they are not compatible!
+The name of zip is taken from M.A.M.E. project, so you can get more info about
+hashes and contained files there.
+
+To generate the ROM using Windows:
+1) Copy the zip into "releases" directory
+2) Execute bat file - it will show the name of zip file containing required files.
+3) Put required zip into the same directory and execute the bat again.
+4) If everything will go without errors or warnings, then you will get the a.*.rom file.
+5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
+
+To generate the ROM using Linux/MacOS/MiSTer is in preparation.

clean.bat

@@ -0,0 +1,41 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+del sys\vip.qip
+del sys\sysmem.qip
+del sys\sdram.sv
+del sys\ddram.sv
+pause

releases/build_rom.ini

@@ -0,0 +1,6 @@
+zip=nrallyx.zip
+ifiles=(prg1_0 prg2_0 prg1_1 prg2_1 prg3_0 prg4_0 prg3_1 prg4_1 ../bang_snd.bin nrx_chg1.8e nrx_chg2.8d rx1-6.8m rx1-5.3p nrx1-7.8p nrx1-1.11n)
+ofile=a.nrallyx.rom
+ofileMd5sumValid=113b2afb644dd386dc7c3fc1ae685ff4
+
+split=("split nrx_prg1.1d -b 2048  prg1_ -d -a 1" "split nrx_prg2.1e -b 2048  prg2_ -d -a 1" "split nrx_prg3.1k -b 2048  prg3_ -d -a 1" "split nrx_prg4.1l -b 2048  prg4_ -d -a 1")

releases/build_rom.sh

@@ -0,0 +1,111 @@
+#!/bin/bash
+
+exit_with_error() {
+  echo -e "\nERROR:\n${1}\n"
+  exit 1
+}
+
+check_dependencies() {
+  if [[ $OSTYPE == darwin* ]]; then
+    for j in unzip md5 cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  else
+    for j in unzip md5sum cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  fi
+}
+
+check_permissions () {
+  if [ ! -w ${BASEDIR} ]; then
+    exit_with_error "Cannot write to\n${BASEDIR}"
+  fi
+}
+
+read_ini () {
+  if [ ! -f ${BASEDIR}/build_rom.ini ]; then
+    exit_with_error "Missing build_rom.ini"
+  else
+    source ${BASEDIR}/build_rom.ini
+  fi
+}
+
+uncompress_zip() {
+  if [ -f ${BASEDIR}/${zip} ]; then
+    tmpdir=tmp.`date +%Y%m%d%H%M%S%s`
+    unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip}
+    if [ $? != 0 ] ; then
+      rm -rf ${BASEDIR}/$tmpdir
+      exit_with_error "Something went wrong\nwhen extracting\n${zip}"
+    fi
+  else
+    exit_with_error "Cannot find ${zip}"
+  fi
+}
+split_files() {
+    #split nrx_prg1.1d -b 2048  prg1_ -d -a 1
+    pushd ${BASEDIR}/${tmpdir}/
+    for ((i=0;i< ${#split[@]}; i++))
+    do
+      #echo ${split[$i]}
+      ${split[$i]}
+    done
+    popd
+}
+generate_rom() {
+  for i in "${ifiles[@]}"; do
+      # ensure provided zip contains required files
+      if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then
+        rm -rf ${BASEDIR}/$tmpdir
+        exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}"
+      else
+        cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile}
+     fi
+  done
+}
+
+validate_rom() {
+
+  if [[ $OSTYPE == darwin* ]]; then
+    ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  else
+    ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  fi
+
+  if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then
+    echo -e "\nExpected checksum:\n${ofileMd5sumValid}"
+    echo -e "Actual checksum:\n${ofileMd5sumCurrent}"
+    mv ${BASEDIR}/${tmpdir}/${ofile} .
+    rm -rf ${BASEDIR}/$tmpdir
+    exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content."
+  else
+    mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/.
+    rm -rf ${BASEDIR}/$tmpdir
+    echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n"
+  fi
+}
+
+BASEDIR=$(dirname "$0")
+
+echo "Generating ROM ..."
+
+## verify dependencies
+check_dependencies
+
+## verify write permissions
+check_permissions
+
+## load ini
+read_ini
+
+## extract package
+uncompress_zip
+
+split_files
+
+## build rom
+generate_rom
+
+## verify rom
+validate_rom

releases/build_rom_NRallyX.bat

@@ -0,0 +1,37 @@
+@powershell -NoProfile -ExecutionPolicy Unrestricted "$s=[scriptblock]::create((gc \"%~f0\"|?{$_.readcount -gt 1})-join\"`n\");&$s" %*&goto:eof
+
+function SplitFile ($inFile, $outPrefix, [Int32] $bufSize) {
+  $stream = [System.IO.File]::OpenRead("tmp/$inFile")
+  $chunkNum = 0
+  $barr = New-Object byte[] $bufSize
+
+  while( $bytesRead = $stream.Read($barr,0,$bufsize)){
+    $outFile = "tmp/$outPrefix$chunkNum"
+    $ostream = [System.IO.File]::OpenWrite($outFile)
+    $ostream.Write($barr,0,$bytesRead);
+    $ostream.close();
+    $chunkNum += 1
+  }
+  $stream.close();
+}
+#==============================================================
+$zip="nrallyx.zip"
+$ifiles="prg1_0","prg2_0","prg1_1","prg2_1","prg3_0","prg4_0","prg3_1","prg4_1","../bang_snd.bin","nrx_chg1.8e","nrx_chg2.8d","rx1-6.8m","rx1-5.3p","nrx1-7.8p","nrx1-1.11n"
+$ofile="a.nrallyx.rom"
+
+Expand-Archive -Path "./$zip" -Destination ./tmp/ -Force
+SplitFile "nrx_prg1.1d" "prg1_" 2048
+SplitFile "nrx_prg2.1e" "prg2_" 2048
+SplitFile "nrx_prg3.1k" "prg3_" 2048
+SplitFile "nrx_prg4.1l" "prg4_" 2048
+cd tmp
+Get-Content $ifiles -Enc Byte -Read 512 | Set-Content "../$ofile" -Enc Byte
+cd ..
+Remove-Item ./tmp -Recurse -Force
+
+echo "** done **"
+echo ""
+echo "Copy $ofile into root of SD card"
+echo ""
+echo ""
+pause

releases/build_rom_RallyX.bat

@@ -0,0 +1,18 @@
+@powershell -NoProfile -ExecutionPolicy Unrestricted "$s=[scriptblock]::create((gc \"%~f0\"|?{$_.readcount -gt 1})-join\"`n\");&$s" %*&goto:eof
+#==============================================================
+$zip="rallyx.zip"
+$ifiles="1b","rallyxn.1e","rallyxn.1h","rallyxn.1k","../bang_snd.bin","8e","rx1-6.8m","rx1-5.3p","rx1-7.8p","rx1-1.11n"
+$ofile="a.rallyx.rom"
+
+Expand-Archive -Path "./$zip" -Destination ./tmp/ -Force
+cd tmp
+Get-Content $ifiles -Enc Byte -Read 512 | Set-Content "../$ofile" -Enc Byte
+cd ..
+Remove-Item ./tmp -Recurse -Force
+
+echo "** done **"
+echo ""
+echo "Copy $ofile into root of SD card"
+echo ""
+echo ""
+pause

releases/build_rom_alt.ini

@@ -0,0 +1,4 @@
+zip=rallyx.zip
+ifiles=(1b rallyxn.1e rallyxn.1h rallyxn.1k ../bang_snd.bin 8e rx1-6.8m rx1-5.3p rx1-7.8p rx1-1.11n)
+ofile=a.rallyx.rom
+ofileMd5sumValid=47b5dc3c2683e23b387115da19e2771a

releases/build_rom_alt.sh

@@ -0,0 +1,100 @@
+#!/bin/bash
+
+exit_with_error() {
+  echo -e "\nERROR:\n${1}\n"
+  exit 1
+}
+
+check_dependencies() {
+  if [[ $OSTYPE == darwin* ]]; then
+    for j in unzip md5 cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  else
+    for j in unzip md5sum cat cut; do
+      command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+    done
+  fi
+}
+
+check_permissions () {
+  if [ ! -w ${BASEDIR} ]; then
+    exit_with_error "Cannot write to\n${BASEDIR}"
+  fi
+}
+
+read_ini () {
+  if [ ! -f ${BASEDIR}/build_rom_alt.ini ]; then
+    exit_with_error "Missing build_rom_alt.ini"
+  else
+    source ${BASEDIR}/build_rom_alt.ini
+  fi
+}
+
+uncompress_zip() {
+  if [ -f ${BASEDIR}/${zip} ]; then
+    tmpdir=tmp.`date +%Y%m%d%H%M%S%s`
+    unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip}
+    if [ $? != 0 ] ; then
+      rm -rf ${BASEDIR}/$tmpdir
+      exit_with_error "Something went wrong\nwhen extracting\n${zip}"
+    fi
+  else
+    exit_with_error "Cannot find ${zip}"
+  fi
+}
+
+generate_rom() {
+  for i in "${ifiles[@]}"; do
+      # ensure provided zip contains required files
+      if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then
+        rm -rf ${BASEDIR}/$tmpdir
+        exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}"
+      else
+        cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile}
+     fi
+  done
+}
+
+validate_rom() {
+
+  if [[ $OSTYPE == darwin* ]]; then
+    ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  else
+    ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+  fi
+
+  if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then
+    echo -e "\nExpected checksum:\n${ofileMd5sumValid}"
+    echo -e "Actual checksum:\n${ofileMd5sumCurrent}"
+    mv ${BASEDIR}/${tmpdir}/${ofile} .
+    rm -rf ${BASEDIR}/$tmpdir
+    exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content."
+  else
+    mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/.
+    rm -rf ${BASEDIR}/$tmpdir
+    echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n"
+  fi
+}
+
+BASEDIR=$(dirname "$0")
+
+echo "Generating ROM ..."
+
+## verify dependencies
+check_dependencies
+
+## verify write permissions
+check_permissions
+
+## load ini
+read_ini
+
+## extract package
+uncompress_zip
+
+## build rom
+generate_rom
+
+## verify rom
+validate_rom

releases/rommap.txt

@@ -0,0 +1,10 @@
+
+0000-3FFF	CPU instruction
+4000-7FFF	"BANG!" PCM data
+8000-8FFF	Background/Object pattern
+9000-90FF	Rader dot pattern
+9100-91FF	Sound wave
+9200-92FF	Lookup table
+9300-931F	Palette
+
+[EOF]

src/LINEBUF.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LINEBUF.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LINEBUF_bb.v"]

src/LINEBUF.v

@@ -0,0 +1,246 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: LINEBUF.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2017  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module LINEBUF (
+	address_a,
+	address_b,
+	clock_a,
+	clock_b,
+	data_a,
+	data_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[9:0]  address_a;
+	input	[9:0]  address_b;
+	input	  clock_a;
+	input	  clock_b;
+	input	[8:0]  data_a;
+	input	[8:0]  data_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[8:0]  q_a;
+	output	[8:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock_a;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] sub_wire1;
+	wire [8:0] q_a = sub_wire0[8:0];
+	wire [8:0] q_b = sub_wire1[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock_a),
+				.clock1 (clock_b),
+				.data_a (data_a),
+				.data_b (data_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus (),
+				.rden_a (1'b1),
+				.rden_b (1'b1));
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK1",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK1",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.numwords_b = 1024,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.widthad_b = 10,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 9 0 INPUT NODEFVAL "data_a[8..0]"
+// Retrieval info: USED_PORT: data_b 0 0 9 0 INPUT NODEFVAL "data_b[8..0]"
+// Retrieval info: USED_PORT: q_a 0 0 9 0 OUTPUT NODEFVAL "q_a[8..0]"
+// Retrieval info: USED_PORT: q_b 0 0 9 0 OUTPUT NODEFVAL "q_b[8..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data_a 0 0 9 0
+// Retrieval info: CONNECT: @data_b 0 0 9 0 data_b 0 0 9 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 9 0 @q_a 0 0 9 0
+// Retrieval info: CONNECT: q_b 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

src/cpu/T80_ALU.vhd

@@ -0,0 +1,351 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--	0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--	0240 : Added GB operations
+--
+--	0242 : Cleanup
+--
+--	0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16		: in std_logic;
+		Z16			: in std_logic;
+		ALU_Op		: in std_logic_vector(3 downto 0);
+		IR			: in std_logic_vector(5 downto 0);
+		ISet		: in std_logic_vector(1 downto 0);
+		BusA		: in std_logic_vector(7 downto 0);
+		BusB		: in std_logic_vector(7 downto 0);
+		F_In		: in std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A : std_logic_vector;
+					B : std_logic_vector;
+					Sub : std_logic;
+					Carry_In : std_logic;
+					signal Res : out std_logic_vector;
+					signal Carry : out std_logic) is
+		variable B_i		: unsigned(A'length - 1 downto 0);
+		variable Res_i		: unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i := unsigned(B);
+		end if;
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal	UseCarry		: std_logic;
+	signal	Carry7_v		: std_logic;
+	signal	Overflow_v		: std_logic;
+	signal	HalfCarry_v		: std_logic;
+	signal	Carry_v			: std_logic;
+	signal	Q_v				: std_logic_vector(7 downto 0);
+
+	signal	BitMask			: std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+									"00000010" when "001",
+									"00000100" when "010",
+									"00001000" when "011",
+									"00010000" when "100",
+									"00100000" when "101",
+									"01000000" when "110",
+									"10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+	OverFlow_v <= Carry_v xor Carry7_v;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+
+end;

src/cpu/T80_Pack.vhd

@@ -0,0 +1,208 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		CEN			: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		IORQ		: out std_logic;
+		NoRead		: out std_logic;
+		Write		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DInst		: in std_logic_vector(7 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0);
+		MC			: out std_logic_vector(2 downto 0);
+		TS			: out std_logic_vector(2 downto 0);
+		IntCycle_n	: out std_logic;
+		IntE		: out std_logic;
+		Stop		: out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR				: in std_logic_vector(7 downto 0);
+		ISet			: in std_logic_vector(1 downto 0);
+		MCycle			: in std_logic_vector(2 downto 0);
+		F				: in std_logic_vector(7 downto 0);
+		NMICycle		: in std_logic;
+		IntCycle		: in std_logic;
+		MCycles			: out std_logic_vector(2 downto 0);
+		TStates			: out std_logic_vector(2 downto 0);
+		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC			: out std_logic;
+		Inc_WZ			: out std_logic;
+		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg		: out std_logic;
+		Read_To_Acc		: out std_logic;
+		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op			: out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU		: out std_logic;
+		PreserveC		: out std_logic;
+		Arith16			: out std_logic;
+		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ			: out std_logic;
+		Jump			: out std_logic;
+		JumpE			: out std_logic;
+		JumpXY			: out std_logic;
+		Call			: out std_logic;
+		RstP			: out std_logic;
+		LDZ				: out std_logic;
+		LDW				: out std_logic;
+		LDSPHL			: out std_logic;
+		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH		: out std_logic;
+		ExchangeRp		: out std_logic;
+		ExchangeAF		: out std_logic;
+		ExchangeRS		: out std_logic;
+		I_DJNZ			: out std_logic;
+		I_CPL			: out std_logic;
+		I_CCF			: out std_logic;
+		I_SCF			: out std_logic;
+		I_RETN			: out std_logic;
+		I_BT			: out std_logic;
+		I_BC			: out std_logic;
+		I_BTR			: out std_logic;
+		I_RLD			: out std_logic;
+		I_RRD			: out std_logic;
+		I_INRC			: out std_logic;
+		SetDI			: out std_logic;
+		SetEI			: out std_logic;
+		IMode			: out std_logic_vector(1 downto 0);
+		Halt			: out std_logic;
+		NoRead			: out std_logic;
+		Write			: out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16		: in std_logic;
+		Z16			: in std_logic;
+		ALU_Op		: in std_logic_vector(3 downto 0);
+		IR			: in std_logic_vector(5 downto 0);
+		ISet		: in std_logic_vector(1 downto 0);
+		BusA		: in std_logic_vector(7 downto 0);
+		BusB		: in std_logic_vector(7 downto 0);
+		F_In		: in std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;

src/cpu/T80_Reg.vhd

@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0242 : Initial release
+--
+--	0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal	RegsH	: Register_Image(0 to 7);
+	signal	RegsL	: Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;

src/cpu/T80s.vhd

@@ -0,0 +1,190 @@
+--
+-- Z80 compatible microprocessor core, synchronous top level
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0208 : First complete release
+--
+--	0210 : Fixed read with wait
+--
+--	0211 : Fixed interrupt cycle
+--
+--	0235 : Updated for T80 interface change
+--
+--	0236 : Added T2Write generic
+--
+--	0237 : Fixed T2Write with wait state
+--
+--	0238 : Updated for T80 interface change
+--
+--	0240 : Updated for T80 interface change
+--
+--	0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80s is
+	generic(
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
+		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		MREQ_n		: out std_logic;
+		IORQ_n		: out std_logic;
+		RD_n		: out std_logic;
+		WR_n		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0)
+	);
+end T80s;
+
+architecture rtl of T80s is
+
+	signal CEN			: std_logic;
+	signal IntCycle_n	: std_logic;
+	signal NoRead		: std_logic;
+	signal Write		: std_logic;
+	signal IORQ			: std_logic;
+	signal DI_Reg		: std_logic_vector(7 downto 0);
+	signal MCycle		: std_logic_vector(2 downto 0);
+	signal TState		: std_logic_vector(2 downto 0);
+
+begin
+
+	CEN <= '1';
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => IOWait)
+		port map(
+			CEN => CEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_n,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => RESET_n,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK_n,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			if MCycle = "001" then
+				if TState = "001" or (TState = "010" and Wait_n = '0') then
+					RD_n <= not IntCycle_n;
+					MREQ_n <= not IntCycle_n;
+					IORQ_n <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					MREQ_n <= '0';
+				end if;
+			else
+				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+					RD_n <= '0';
+					IORQ_n <= not IORQ;
+					MREQ_n <= IORQ;
+				end if;
+				if T2Write = 0 then
+					if TState = "010" and Write = '1' then
+						WR_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+						WR_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+				end if;
+			end if;
+			if TState = "010" and Wait_n = '1' then
+				DI_Reg <= DI;
+			end if;
+		end if;
+	end process;
+
+end;

src/fpga_nrx.v

@@ -0,0 +1,155 @@
+/**************************************************************
+	FPGA New Rally-X (Main part)
+***************************************************************/
+module fpga_NRX
+(
+	input				RESET,		// RESET
+	input				CLK24M,		// Clock 24.576MHz
+
+	input	  [8:0]	HP,			// VIDEO H-POSITION input
+	input   [8:0]	VP,			// VIDEO V-POSITION input
+	output			PCLK,			// PIXEL Clock output
+	output  [7:0]	POUT,			// PIXEL Color output
+
+	output  [7:0]	SND,			// Sound (unsigned PCM)
+
+	input   [7:0]	DSW,			// DipSW
+	input	  [7:0]	CTR1,			// Controler (Negative logic)
+	input	  [7:0]	CTR2,
+
+	output  [1:0]	LAMP,			// Lamp output
+
+	input				ROMCL,		// Downloaded ROM image
+	input  [15:0] 	ROMAD,
+	input	  [7:0]	ROMDT,
+	input				ROMEN
+);
+
+
+//--------------------------------------------------
+//  Clock Generators
+//--------------------------------------------------
+reg [2:0] _CCLK;
+always @( posedge CLK24M ) _CCLK <= _CCLK+1;
+
+wire	CLK    = CLK24M;		// 24MHz
+wire	CCLKx2 = _CCLK[1];	// CPU CLOCKx2 : 6.0MHz
+wire	CCLK   = _CCLK[2];	// CPU CLOCK   : 3.0MHz
+
+
+//--------------------------------------------------
+//  CPU
+//--------------------------------------------------
+// memory access signals
+wire			rd, wr, me, ie, rf, m1;
+wire [15:0] ad;
+wire [7:0]  odt, viddata;
+
+wire			mx      = rf & (~me);
+wire			mr		  = mx & (~rd);
+wire			mw      = mx & (~wr);
+
+// interrupt signal/vector generator & other latches
+reg			inte  = 1'b0;
+reg			intl  = 1'b0;
+reg  [7:0]	intv  = 8'h0;
+
+reg			bang  = 1'b0;
+
+reg			lp0r  = 1'b0;
+reg			lp1r  = 1'b0;
+assign		LAMP  = { lp1r, lp0r };
+
+wire			vblk  = (VP==224)&(HP<=8);
+
+wire			lat_Wce = ( ad[15:4] == 12'hA18 ) & mw;
+
+wire			bngw = ( lat_Wce & ( ad[3:0] == 4'h0 ) );
+wire			iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) );
+wire			flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );
+wire			lp0w = ( lat_Wce & ( ad[3:0] == 4'h4 ) );
+wire			lp1w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );
+wire			iowr = ( (~wr) & (~ie) & m1 );
+
+always @( posedge CCLK ) begin
+	if ( iowr ) intv <= odt;
+	if ( vblk ) intl <= 1'b1;
+	if ( iewr ) begin
+		inte <= odt[0];
+		intl <= 1'b0; 
+	end
+	if ( bngw ) bang <= odt[0];
+	if ( lp0w ) lp0r <= odt[0];
+	if ( lp1w ) lp1r <= odt[0];
+end
+
+wire	irq_n = ~( intl & inte );
+
+
+// address decoders
+wire	rom_Rce = ( ( ad[15:14] == 2'b00        ) & mr );		// $0000-$3FFF(R)
+wire	ram_Rce = ( ( ad[15:11] == 5'b1001_1    ) & mr );		// $9800-$9FFF(R)
+wire	ram_Wce = ( ( ad[15:11] == 5'b1001_1    ) & mw );		// $9800-$9FFF(W)
+wire	inp_Rce = ( ( ad[15:12] == 4'b1010      ) & mr );		// $A000-$AFFF(R)
+wire	snd_Wce = ( ( ad[15:8]  == 8'b1010_0001 ) & mw );		// $A100-$A1FF(W)
+wire	vid_Rce;
+
+
+wire  [7:0]	romdata;
+DLROM #(14,8) cpurom(CCLK,ad[13:0],romdata, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[15:14]==2'b00));
+
+// Work RAM (2KB)
+wire [7:0] ramdata;
+GSPRAM #(11,8) workram( CCLK, ad[10:0], ram_Wce, odt, ramdata );
+
+
+// Controler/DipSW input
+wire [7:0]  in0data = CTR1;
+wire [7:0]  in1data = CTR2;
+wire [7:0]  in2data = DSW;
+wire [7:0]  inpdata = ad[8] ? in2data : ad[7] ? in1data : in0data;
+
+
+// databus selector
+wire [7:0]	romd  = rom_Rce ? romdata : 8'h00;
+wire [7:0]  ramd  = ram_Rce ? ramdata : 8'h00;
+wire [7:0]  vidd  = vid_Rce ? viddata : 8'h00;
+wire [7:0]	inpd  = inp_Rce ? inpdata : 8'h00;
+wire [7:0]	irqv  = ( (~m1) & (~ie) ) ? intv : 8'h00;
+
+wire [7:0]	idt   = romd | ramd | irqv | vidd | inpd;
+
+
+T80s z80(
+	.RESET_n(~RESET), .CLK_n(CCLK),
+	.WAIT_n(1'b1), .INT_n(irq_n), .NMI_n(1'b1), .BUSRQ_n(1'b1), .DI(idt),
+	.M1_n(m1), .MREQ_n(me), .IORQ_n(ie), .RD_n(rd), .WR_n(wr), .RFSH_n(rf), .HALT_n(), .BUSAK_n(),
+	.A(ad),
+	.DO(odt)
+);
+
+
+//--------------------------------------------------
+//  VIDEO
+//--------------------------------------------------
+NRX_VIDEO video( 
+	.VCLKx4(CLK),  .HPOS(HP+3), .VPOS(VP+1), .PCLK(PCLK), .POUT(POUT), 
+	.CPUCLK(CCLK), .CPUADDR(ad),
+	.CPUDI(odt),   .CPUDO(viddata),
+	.CPUME(mx),    .CPUWE(mw), .CPUDT(vid_Rce),
+
+	.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
+);
+
+//--------------------------------------------------
+//  SOUND
+//--------------------------------------------------
+NRX_SOUND	sound(
+	.CLK24M(CLK), .CCLK(CCLK), .SND(SND),
+	.AD(ad[4:0]), .DI(odt[3:0]),.WR(snd_Wce),
+	.BANG(bang),
+
+	.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
+); 
+
+endmodule

src/nrx_sound.v

@@ -0,0 +1,163 @@
+/**************************************************************
+	FPGA New Rally-X (Sound Part)
+***************************************************************/
+module NPSG_VOICE
+(
+	input					clk,
+	output	[3:0]		out,
+
+	input		[19:0]	freq,
+	input		[3:0]		vol,
+	input		[2:0]		vn,
+
+	output	[7:0]		waveaddr,
+	input		[3:0]		wavedata
+);
+
+reg [19:0] counter = 20'h0;
+reg  [7:0] outreg0;
+
+assign waveaddr = { vn, counter[19:15] };
+assign out = outreg0[7:4];
+
+always @ ( posedge clk ) begin
+	outreg0 = ( { 4'b0000, wavedata } * { 4'b0000, vol } );
+	counter <= counter + freq;
+end
+
+endmodule
+
+
+module NPSG_WAV
+(
+	input			clk,
+	input [7:0] a0,
+	input	[7:0] a1,
+	input	[7:0] a2,
+
+	output reg [3:0] d0,
+	output reg [3:0] d1,
+	output reg [3:0] d2,
+	
+	input			 ROMCL,
+	input  [7:0] ROMAD,
+	input  [3:0] ROMDT,
+	input 		 ROMEN
+);
+
+reg  [1:0] ph=0;
+
+reg  [7:0] ad;
+wire [3:0] dt;
+DLROM #(8,4) wrom(clk,ad,dt, ROMCL,ROMAD,ROMDT,ROMEN);
+
+always @(negedge clk) begin
+	case (ph)
+	0: begin d2 <= dt; ad <= a0; ph <= 1; end
+	1: begin d0 <= dt; ad <= a1; ph <= 2; end
+	2: begin d1 <= dt; ad <= a2; ph <= 0; end
+	default:;
+	endcase
+end
+
+endmodule
+
+
+module NRX_SOUND
+(
+	input					CLK24M,
+	input					CCLK,
+	output reg [7:0]	SND,
+
+	input	 [4:0]	AD,
+	input  [3:0]	DI,
+	input				WR,
+
+	input				BANG,
+	
+	input				ROMCL,
+	input [15:0]	ROMAD,
+	input  [7:0]	ROMDT,
+	input				ROMEN
+);
+
+reg [11:0] ccnt;
+always @( posedge CLK24M ) ccnt <= ccnt+1;
+
+wire	CLK6K   = ccnt[11];
+wire  SCLKx8  = ccnt[4];
+wire	SCLK    = ccnt[7];
+
+wire  [7:0]		wa0, wa1, wa2;
+wire  [3:0]		wd0, wd1, wd2;
+NPSG_WAV waverom(
+	SCLKx8, wa0, wa1, wa2, wd0, wd1, wd2,
+	ROMCL,ROMAD[7:0],ROMDT[3:0],ROMEN & (ROMAD[15:8]==8'h91)
+);
+
+reg		  		bWavPlay = 1'b0;
+reg  [13:0] 	wap = 14'h0000;
+wire  [7:0] 	wdp;
+wire  [7:0]		wo = bWavPlay ? wdp : 8'h80;
+DLROM #(14,8) bangpcm(CLK6K,wap,wdp, ROMCL,ROMAD[13:0],ROMDT,ROMEN & (ROMAD[15:14]==2'b01));
+
+always @( posedge CLK6K ) begin
+	if ( BANG && (~bWavPlay) ) bWavPlay <= 1'b1;
+	if ( bWavPlay ) begin
+		wap <= wap+1;
+		if ( wap == 14'h29FF ) begin
+			wap <= 14'h0000;
+			bWavPlay <= 1'b0;
+		end
+	end
+end
+
+reg	[19:0]	f0;
+reg	[15:0]	fq1, fq2;
+reg	[3:0]		v0, v1, v2;
+reg	[2:0]		n0, n1, n2;
+
+wire	[19:0]	f1 = { fq1, 4'b0000 };
+wire	[19:0]	f2 = { fq2, 4'b0000 };
+
+wire	[3:0]		o0,  o1,  o2;
+
+NPSG_VOICE voice0( SCLK, o0, f0, v0, n0, wa0, wd0 );
+NPSG_VOICE voice1( SCLK, o1, f1, v1, n1, wa1, wd1 );
+NPSG_VOICE voice2( SCLK, o2, f2, v2, n2, wa2, wd2 );
+
+reg [7:0] wout;
+always @( posedge SCLK ) SND <= ( { 2'b0, wo[7:2] } ) + ( o0 + o1 + o2 );
+
+always @( posedge CCLK ) begin
+	if ( WR ) case ( AD )
+
+		5'h05:	n0         <= DI[2:0];
+		5'h0A:	n1         <= DI[2:0];
+		5'h0F:	n2         <= DI[2:0];
+
+		5'h10:	f0[3:0]    <= DI;
+		5'h11:	f0[7:4]    <= DI;
+		5'h12:	f0[11:8]   <= DI;
+		5'h13:	f0[15:12]  <= DI;
+		5'h14:	f0[19:16]  <= DI;
+		5'h15:   v0         <= DI;
+
+		5'h16:	fq1[3:0]   <= DI;
+		5'h17:	fq1[7:4]   <= DI;
+		5'h18:	fq1[11:8]  <= DI;
+		5'h19:	fq1[15:12] <= DI;
+		5'h1A:   v1         <= DI;
+
+		5'h1B:	fq2[3:0]   <= DI;
+		5'h1C:	fq2[7:4]   <= DI;
+		5'h1D:	fq2[11:8]  <= DI;
+		5'h1E:	fq2[15:12] <= DI;
+		5'h1F:   v2         <= DI;
+
+		default: ;
+
+	endcase
+end
+
+endmodule

src/nrx_sprite.v

@@ -0,0 +1,142 @@
+
+module NRX_SPRITE
+(
+	input					VCLKx4,
+	input					HBLK,
+
+	input	 [8:0]		HPOS,
+	input	 [8:0]		VPOS,
+
+	output reg [10:0]	SPRAADRS,
+	input  [15:0]		SPRADATA,
+
+	output [3:0]		ARAMADRS,
+	input	 [7:0]		ARAMDATA,
+
+	output [11:0]		SPCHRADR,
+	input	 [7:0]		SPCHRDAT,
+
+	output [7:0]		DROMAD,
+	input  [7:0]		DROMDT,
+
+	output reg [8:0]	SPCOL
+);
+
+reg [1:0] clkcnt;
+always @( posedge VCLKx4 ) clkcnt<=clkcnt+1;
+wire VCLKx2 = clkcnt[0];
+wire VCLK	= clkcnt[1];
+
+wire SIDE = VPOS[0];
+
+
+reg  [19:0] SPATR0;
+reg  [36:0] SPATRS[0:31];
+reg	[3:0] WWADR;
+reg			bHit;
+
+assign ARAMADRS = SPRAADRS[3:0];
+
+
+reg	[7:0] WRADR;
+reg	[8:0] HPOSW;
+reg	[8:0] SPWCL;
+
+wire [36:0] SPA  = SPATRS[{~SIDE,WRADR[7:4]}];
+
+wire	[3:0] SH	 = WRADR[3:0]+4'h4;
+wire	[3:0] SV	 = SPA[35:32];
+
+wire	[2:0] SPFY = { 3{SPA[1]} };
+wire	[1:0] SPFX = { 1'b0, SPA[0] };
+wire	[5:0] SPPL = SPA[29:24];
+
+assign SPCHRADR  = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) };
+wire	[7:0] CHRO = SPCHRDAT;
+
+
+wire	[8:0] YM =  ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0];
+
+assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] };
+
+always @ ( posedge VCLKx2 ) begin
+
+	// in H-BLANK
+	if ( HBLK ) begin
+
+		// Sprite V-hit check & list-up
+		if ( SPRAADRS < 10'h20 ) begin
+			if ( SPRAADRS[0] ) begin
+				if ( bHit ) begin
+					SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] };
+					WWADR <= WWADR+1;
+				end
+			end
+			else begin
+				if ( YM[7:4] == 4'b1111 ) begin
+					bHit	<= 1;
+					SPATR0 <= { SPRADATA, YM[3:0] };
+				end
+				else bHit <= 0;
+			end
+			SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1);
+		end
+		// Rader-dot V-hit check & list-up
+		else begin
+			if ( SPRAADRS < 10'h40 ) begin
+				if ( YM[7:2] == 6'b111111 ) begin
+					SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA };
+					WWADR <= WWADR+1;
+				end
+				SPRAADRS <= SPRAADRS+1;
+			end
+			else SPATRS[{SIDE,WWADR}] <= 0;
+		end
+
+		if ( SPA ) begin
+			// Rend Sprite
+			if ( SPA[36] ) begin
+				HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] };
+				case ( SH[1:0] ^ {2{SPFX[0]}} )
+					2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] };
+					2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] };
+					2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] };
+					2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] };
+				endcase
+				WRADR <= WRADR+1;
+			end
+			// Rend Rader-dot
+			else begin
+				HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] });
+				SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0;
+				WRADR <= WRADR+4;
+			end
+		end
+		else SPWCL <= 0;
+
+	end
+
+	// in H-DISP
+	else begin
+		SPRAADRS <= 10'h14;
+		WWADR <= 0;
+		WRADR <= 0;
+		SPWCL <= 0;
+	end
+
+end
+
+
+reg  [9:0] radr0=0,radr1=1;
+wire [8:0] SPCOLi;
+
+LINEBUF1024_9 linedbuf(VCLKx2,{SIDE,HPOS},(radr0==radr1),SPCOLi, VCLKx2,{~SIDE,HPOSW},(SPWCL[0]|SPWCL[1]),SPWCL);
+//GLINEBUF #(10,9) linedbuf(VCLKx2,{SIDE,HPOS},(radr0==radr1),SPCOLi, VCLKx2,{~SIDE,HPOSW},(SPWCL[0]|SPWCL[1]),SPWCL);
+
+always @(posedge VCLK) radr0 <= {SIDE,HPOS};
+always @(negedge VCLK) begin 
+	if (radr0!=radr1) SPCOL <= SPCOLi;
+	radr1 <= radr0;
+end
+
+endmodule

src/nrx_video.v

@@ -0,0 +1,172 @@
+/**************************************************************
+	FPGA New Rally-X (Video Part)
+***************************************************************/
+module NRX_VIDEO
+(
+	input				 VCLKx4,		// 24.976MHz
+
+	input  [8:0]		HPOS,
+	input  [8:0]		VPOS,
+	output				PCLK,
+	output reg [7:0]	POUT,
+
+	input					CPUCLK,
+	input	 [15:0]		CPUADDR,
+	input	 [7:0]		CPUDI,
+	output [7:0]		CPUDO,
+	input					CPUME,
+	input					CPUWE,
+	output				CPUDT,
+
+	input					ROMCL,
+	input  [15:0]		ROMAD,
+	input  [7:0]		ROMDT,
+	input					ROMEN
+);
+
+//-----------------------------------------
+//  Clock generators
+//-----------------------------------------
+reg VCLKx2;
+always @( posedge VCLKx4 ) begin
+	VCLKx2 <= ~VCLKx2;
+end
+
+reg VCLK;
+always @( posedge VCLKx2 ) begin
+	VCLK   <= ~VCLK;
+end
+
+//-----------------------------------------
+//  BG scroll registers
+//-----------------------------------------
+reg [7:0] BGHSCR;
+reg [7:0] BGVSCR;
+
+always @ ( posedge CPUCLK ) begin
+	if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin
+		BGHSCR <= CPUDI-3;
+	end
+	if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin
+		BGVSCR <= CPUDI;
+	end
+end
+
+
+//-----------------------------------------
+//  HV
+//-----------------------------------------
+wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR };
+wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR };
+
+wire oHB = ( HPOS > 288 ) ? 1 : 0;
+wire oVB = ( VPOS > 224 ) ? 1 : 0;
+
+
+//----------------------------------------
+//  VideoRAM Scanner
+//----------------------------------------
+wire				BF	= ( HPOS >= 224 );
+wire	[8:0]		HP  = BF ? HPOS : BGHPOS;
+wire	[8:0]		VP  = ( BF ? VPOS : BGVPOS ) + 9'h0F;
+
+wire	[10:0]	SPRAADRS;
+wire	[3:0]		ARAMADRS;
+
+reg	[10:0]	VRAMADRS;
+always @ ( HPOS ) begin
+	VRAMADRS <= oHB ? 
+		SPRAADRS :
+		BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] };
+end
+
+wire	[7:0]		CHRC;
+wire	[7:0]		ATTR;
+wire	[7:0]		ARDT;
+
+wire	[7:0]		V0DO, V1DO;
+
+wire				CEV0	= ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME;
+wire				CEV1	= ( ( CPUADDR[15:12] == 4'b1000 ) &   CPUADDR[11]  ) & CPUME;
+wire				CEAT  = (   CPUADDR[15:4]  == 12'b1010_0000_0000         ) & CPUME;
+
+wire	[7:0]		DTV0	= CEV0 ? V0DO : 8'h00;
+wire	[7:0]		DTV1	= CEV1 ? V1DO : 8'h00;
+
+assign			CPUDO = DTV0 | DTV1;
+assign			CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 );
+
+GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO );  
+GDPRAM #(11,8)	vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO );  
+GDPRAM #(4,8)	aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0],  ( CPUWE & CEAT ), CPUDI );
+
+wire				BGF = ATTR[5];
+
+
+//----------------------------------------
+//  BG/Sprite chip data reader
+//----------------------------------------
+wire				BGFX = ATTR[6];
+wire	[2:0]		BGFY = { ATTR[7], ATTR[7], ATTR[7] };
+
+wire	[11:0]	SPCHRADR;
+wire	[11:0]	CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) };
+
+wire	[7:0]		CHRO;
+DLROM #(12,8)  chrrom(VCLKx4,CHRA,CHRO, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[15:12]==4'h8));
+
+
+//----------------------------------------
+//  Rader-dot chip ROM
+//----------------------------------------
+wire  [7:0] 	DROMAD;
+wire  [7:0] 	DROMDT;
+DLROM #(8,8)	dotrom(VCLKx4,DROMAD,DROMDT, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[15:8]==8'h90));
+
+
+//----------------------------------------
+//  BG/FG scanline generator
+//----------------------------------------
+wire [5:0] BGPL = ATTR[5:0];
+reg  [7:0] BGCOL;
+
+always @ ( posedge VCLK ) begin
+	case ( HP[1:0]^{2{BGFX}} )
+		2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] };
+		2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] };
+		2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] };
+		2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] };
+	endcase
+end	
+
+
+//----------------------------------------
+//  Sprite Engine
+//----------------------------------------
+wire [8:0] SPCOL;
+NRX_SPRITE speng( VCLKx4, oHB, HPOS, VPOS, SPRAADRS, { ATTR, CHRC }, ARAMADRS, ARDT, SPCHRADR, CHRO, DROMAD, DROMDT, SPCOL );
+
+
+//----------------------------------------
+//  Color mixer
+//----------------------------------------
+wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) );
+wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 );
+
+wire	[7:0]		OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0];
+wire	[3:0]		CLUT;
+DLROM #(8,4)	colorlt(~VCLKx4,OUTCOL,CLUT, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[15:8]==8'h92));
+
+wire	[4:0]		PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT };
+wire	[7:0]		PALO;
+DLROM #(5,8)	palette(VCLKx4,PALA,PALO,  ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[15:5]=={8'h93,3'b000}));
+
+
+//----------------------------------------
+//  Color output
+//----------------------------------------
+always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO;
+assign PCLK = VCLK;
+
+
+endmodule

src/rams.v

@@ -0,0 +1,111 @@
+
+module LINEBUF1024_9
+(
+	input				CL0,
+	input	 [9:0]	AD0,
+	input				WE0,
+	output [8:0]	DO0,
+
+	input				CL1,
+	input	 [9:0]	AD1,
+	input				WE1,
+	input	 [8:0]	DI1
+);
+
+LINEBUF lbcore (
+	.clock_a(CL0),
+	.address_a(AD0),
+	.data_a(9'h0),
+	.wren_a(WE0),
+	.q_a(DO0),
+
+	.clock_b(CL1),
+	.address_b(AD1),
+	.data_b(DI1),
+	.wren_b(WE1)
+);
+
+endmodule
+
+
+module GSPRAM #(parameter AW,parameter DW)
+(
+	input							CL,
+	input [(AW-1):0]			AD,
+	input							WE,
+	input [(DW-1):0]			DI,
+	output reg [(DW-1):0]	DO
+);
+
+reg [(DW-1):0] core[0:((2**AW)-1)];
+
+always @(posedge CL) begin
+	DO <= core[AD];
+	if (WE) core[AD] <= DI;
+end
+	
+endmodule
+
+
+module GDPRAM #(parameter AW,parameter DW)
+(
+	input							CL0,
+	input [(AW-1):0]			AD0,
+	output reg [(DW-1):0]	DO0,
+
+	input							CL1,
+	input [(AW-1):0]			AD1,
+	input							WE1,
+	input [(DW-1):0]			DI1,
+	output reg [(DW-1):0]	DO1
+);
+
+reg [(DW-1):0] core[0:((2**AW)-1)];
+
+always @(posedge CL0) DO0 <= core[AD0];
+always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end
+
+endmodule
+
+
+module GLINEBUF #(parameter AW,parameter DW)
+(
+	input							CL0,
+	input	 [(AW-1):0]			AD0,
+	input							WE0,
+	output reg [(DW-1):0]	DO0,
+
+	input							CL1,
+	input	 [(AW-1):0]			AD1,
+	input							WE1,
+	input	 [(DW-1):0]			DI1
+);
+
+reg [(DW-1):0] core[0:((2**AW)-1)];
+
+always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end
+always @(posedge CL1) if (WE1) core[AD1] <= DI1;
+
+endmodule
+
+
+module DLROM #(parameter AW,parameter DW)
+(
+	input							CL0,
+	input [(AW-1):0]			AD0,
+	output reg [(DW-1):0]	DO0,
+
+	input							CL1,
+	input [(AW-1):0]			AD1,
+	input	[(DW-1):0]			DI1,
+	input							WE1
+);
+
+reg [DW:0] core[0:((2**AW)-1)];
+
+always @(posedge CL0) DO0 <= core[AD0];
+always @(posedge CL1) if (WE1) core[AD1] <= DI1;
+
+endmodule
+
+

sys/alsa.sv

@@ -0,0 +1,128 @@
+//============================================================================
+//
+//  ALSA sound support for MiSTer
+//  (c)2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module alsa
+(
+	input             reset,
+
+	input             ram_clk,
+	output reg [28:0] ram_address,
+	output reg  [7:0] ram_burstcount,
+	input             ram_waitrequest,
+	input      [63:0] ram_readdata,
+	input             ram_readdatavalid,
+	output reg        ram_read,
+	
+	input             spi_ss,
+	input             spi_sck,
+	input             spi_mosi,
+	
+	output reg [15:0] pcm_l,
+	output reg [15:0] pcm_r
+);
+
+reg         spi_new = 0;
+reg [127:0] spi_data;
+always @(posedge spi_sck, posedge spi_ss) begin
+	reg [7:0] mosi;
+	reg [6:0] spicnt = 0;
+	
+	if(spi_ss) spicnt <= 0;
+	else begin
+		mosi <= {mosi[6:0],spi_mosi};
+
+		spicnt <= spicnt + 1'd1;
+		if(&spicnt[2:0]) begin
+			spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
+			spi_new <= &spicnt;
+		end
+	end
+end
+
+reg [31:0] buf_addr;
+reg [31:0] buf_len;
+reg [31:0] buf_wptr = 0;
+
+always @(posedge ram_clk) begin
+	reg n1,n2,n3;
+	reg [127:0] data1,data2;
+
+	n1 <= spi_new;
+	n2 <= n1;
+	n3 <= n2;
+	
+	data1 <= spi_data;
+	data2 <= data1;
+	
+	if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
+end
+
+reg [31:0] buf_rptr = 0;
+always @(posedge ram_clk) begin
+	reg got_first = 0;
+	reg ready = 0;
+	reg ud;
+	reg [31:0] readdata;
+
+	if(~ram_waitrequest) ram_read <= 0;
+	if(ram_readdatavalid && ram_burstcount) begin
+		ram_burstcount <= 0;
+		ready <= 1;
+		readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
+		if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
+	end
+
+	if(reset) {ready, got_first} <= 0;
+	else
+	if(buf_rptr[31:2] != buf_wptr[31:2]) begin
+		if(~got_first) begin
+			buf_rptr <= buf_wptr;
+			got_first <= 1;
+		end
+		else
+		if(!ram_burstcount && ~ram_waitrequest && ~ready) begin
+			ram_address <= buf_addr[31:3] + buf_rptr[31:3];
+			ud <= buf_rptr[2];
+			ram_burstcount <= 1;
+			ram_read <= 1;
+			buf_rptr <= buf_rptr + 4;
+		end
+	end
+
+	if(ready & ce_48k) begin
+		{pcm_r,pcm_l} <= readdata;
+		ready <= 0;
+	end
+end
+
+reg ce_48k;
+always @(posedge ram_clk) begin
+	reg [15:0] acc = 0;
+
+	ce_48k <= 0;
+	acc <= acc + 16'd48;
+	if(acc >= 50000) begin
+		acc <= acc - 16'd50000;
+		ce_48k <= 1;
+	end
+end
+
+endmodule

sys/arcade_video.v

@@ -0,0 +1,478 @@
+//============================================================================
+//
+//  Screen +90/-90 deg. rotation
+//  Copyright (C) 2017-2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+//
+// Output timings are incompatible with any TV/VGA mode.
+// The output is supposed to be send to scaler input.
+//
+module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4, CCW=0)
+(
+	input              clk,
+	input              ce,
+
+	input  [DEPTH-1:0] video_in,
+	input              hblank,
+	input              vblank,
+
+	input              ce_out,
+	output [DEPTH-1:0] video_out,
+	output reg         hsync,
+	output reg         vsync,
+	output reg         hblank_out,
+	output reg         vblank_out
+);
+
+localparam bufsize = WIDTH*HEIGHT;
+localparam memsize = bufsize*2;
+localparam aw = memsize > 131072 ? 18 : memsize > 65536 ? 17 : 16; // resolutions up to ~ 512x256
+
+reg [aw-1:0] addr_in, addr_out;
+reg we_in;
+reg buff = 0;
+
+rram #(aw, DEPTH, memsize) ram
+(
+	.wrclock(clk),
+	.wraddress(addr_in),
+	.data(video_in),
+	.wren(en_we),
+	
+	.rdclock(clk),
+	.rdaddress(addr_out),
+	.q(out)
+);
+
+wire [DEPTH-1:0] out; 
+reg  [DEPTH-1:0] vout;
+
+assign video_out = vout;
+
+wire en_we = ce & ~blank & en_x & en_y;
+wire en_x = (xpos<WIDTH);
+wire en_y = (ypos<HEIGHT);
+integer xpos, ypos;
+
+wire blank = hblank | vblank;
+always @(posedge clk) begin
+	reg old_blank, old_vblank;
+	reg [aw-1:0] addr_row;
+
+	if(en_we) begin
+		addr_in <= CCW ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
+		xpos <= xpos + 1;
+	end
+
+	old_blank <= blank;
+	old_vblank <= vblank;
+	if(~old_blank & blank) begin
+		xpos <= 0;
+		ypos <= ypos + 1;
+		addr_in  <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
+		addr_row <= CCW ? addr_row + 1'd1 : addr_row - 1'd1;
+	end
+
+	if(~old_vblank & vblank) begin
+		if(buff) begin
+			addr_in  <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
+			addr_row <= CCW ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
+		end else begin
+			addr_in  <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
+			addr_row <= CCW ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
+		end
+		buff <= ~buff;
+		ypos <= 0;
+		xpos <= 0;
+	end
+end
+
+always @(posedge clk) begin
+	reg old_buff;
+	reg hs;
+	reg ced;
+
+	integer vbcnt;
+	integer xposo, yposo, xposd, yposd;
+	
+	ced <= 0;
+	if(ce_out) begin
+		ced <= 1;
+
+		xposd <= xposo;
+		yposd <= yposo;
+
+		if(xposo == (HEIGHT + 8))  hsync <= 1;
+		if(xposo == (HEIGHT + 10)) hsync <= 0;
+
+		if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
+			if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
+		end
+
+		xposo <= xposo + 1;
+		if(xposo > (HEIGHT + 16)) begin
+			xposo  <= 0;
+			
+			if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
+				vblank_out <= 1;
+				vbcnt <= vbcnt + 1;
+				if(vbcnt == 10	) vsync <= 1;
+				if(vbcnt == 12) vsync <= 0;
+			end
+			else yposo <= yposo + 1;
+			
+			old_buff <= buff;
+			if(old_buff != buff) begin
+				addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
+				yposo <= 0;
+				vsync <= 0;
+				vbcnt <= 0;
+				vblank_out <= 0;
+			end
+		end
+	end
+	
+	if(ced) begin
+		if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
+			vout <= 0;
+		end else begin
+			vout <= out;
+		end
+		if(xposd == 0)       hblank_out <= 0;
+		if(xposd == HEIGHT)  hblank_out <= 1;
+	end
+end
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+// DW:
+//  6 : 2R 2G 2B
+//  8 : 3R 3G 2B
+//  9 : 3R 3G 3B
+// 12 : 4R 4G 4B
+
+module arcade_rotate_fx #(parameter WIDTH=320, HEIGHT=240, DW=8, CCW=0)
+(
+	input         clk_video,
+	input         ce_pix,
+
+	input[DW-1:0] RGB_in,
+	input         HBlank,
+	input         VBlank,
+	input         HSync,
+	input         VSync,
+
+	output        VGA_CLK,
+	output        VGA_CE,
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,
+
+	output        HDMI_CLK,
+	output        HDMI_CE,
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,
+	output  [1:0] HDMI_SL,
+	
+	input   [2:0] fx,
+	input         forced_scandoubler,
+	input         no_rotate
+);
+
+assign VGA_CLK = clk_video;
+assign VGA_CE = ce_pix;
+assign VGA_HS = HSync;
+assign VGA_VS = VSync;
+assign VGA_DE = ~(HBlank | VBlank);
+
+generate
+	if(DW == 6) begin
+		assign VGA_R = {RGB_in[5:4],RGB_in[5:4],RGB_in[5:4],RGB_in[5:4]};
+		assign VGA_G = {RGB_in[3:2],RGB_in[3:2],RGB_in[3:2],RGB_in[3:2]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 8) begin
+		assign VGA_R = {RGB_in[7:5],RGB_in[7:5],RGB_in[7:6]};
+		assign VGA_G = {RGB_in[4:2],RGB_in[4:2],RGB_in[4:3]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 9) begin
+		assign VGA_R = {RGB_in[8:6],RGB_in[8:6],RGB_in[8:7]};
+		assign VGA_G = {RGB_in[5:3],RGB_in[5:3],RGB_in[5:4]};
+		assign VGA_B = {RGB_in[2:0],RGB_in[2:0],RGB_in[2:1]};
+	end
+	else begin
+		assign VGA_R = {RGB_in[11:8],RGB_in[11:8]};
+		assign VGA_G = {RGB_in[7:4],RGB_in[7:4]};
+		assign VGA_B = {RGB_in[3:0],RGB_in[3:0]};
+	end
+endgenerate
+
+wire [DW-1:0] RGB_out;
+wire rhs,rvs,rhblank,rvblank;
+
+screen_rotate #(WIDTH,HEIGHT,DW,4,CCW) rotator
+(
+	.clk(VGA_CLK),
+	.ce(VGA_CE),
+
+	.video_in(RGB_in),
+	.hblank(HBlank),
+	.vblank(VBlank),
+
+	.ce_out(VGA_CE | ~scandoubler),
+	.video_out(RGB_out),
+	.hsync(rhs),
+	.vsync(rvs),
+	.hblank_out(rhblank),
+	.vblank_out(rvblank)
+);
+
+wire [3:0] Rr,Gr,Br;
+
+generate
+	if(DW == 6) begin
+		assign Rr = {RGB_out[5:4],RGB_out[5:4]};
+		assign Gr = {RGB_out[3:2],RGB_out[3:2]};
+		assign Br = {RGB_out[1:0],RGB_out[1:0]};
+	end
+	else if(DW == 8) begin
+		assign Rr = {RGB_out[7:5],RGB_out[7]};
+		assign Gr = {RGB_out[4:2],RGB_out[4]};
+		assign Br = {RGB_out[1:0],RGB_out[1:0]};
+	end
+	else if(DW == 9) begin
+		assign Rr = {RGB_out[8:6],RGB_out[8]};
+		assign Gr = {RGB_out[5:3],RGB_out[5]};
+		assign Br = {RGB_out[2:0],RGB_out[2]};
+	end
+	else begin
+		assign Rr = RGB_out[11:8];
+		assign Gr = RGB_out[7:4];
+		assign Br = RGB_out[3:0];
+	end
+endgenerate
+
+assign HDMI_CLK = VGA_CLK;
+assign HDMI_SL  = no_rotate ? 2'd0 : sl[1:0];
+wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
+wire scandoubler = fx || forced_scandoubler;
+
+video_mixer #(WIDTH+4, 1) video_mixer
+(
+	.clk_sys(HDMI_CLK),
+	.ce_pix(VGA_CE | ~scandoubler),
+	.ce_pix_out(HDMI_CE),
+
+	.scandoubler(scandoubler),
+	.hq2x(fx==1),
+
+	.R(no_rotate ? VGA_R[7:4] : Rr),
+	.G(no_rotate ? VGA_G[7:4] : Gr),
+	.B(no_rotate ? VGA_B[7:4] : Br),
+
+	.HSync (no_rotate ? HSync  : rhs),
+	.VSync (no_rotate ? VSync  : rvs),
+	.HBlank(no_rotate ? HBlank : rhblank),
+	.VBlank(no_rotate ? VBlank : rvblank),
+
+	.VGA_R(HDMI_R),
+	.VGA_G(HDMI_G),
+	.VGA_B(HDMI_B),
+	.VGA_VS(HDMI_VS),
+	.VGA_HS(HDMI_HS),
+	.VGA_DE(HDMI_DE)
+);
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+// DW:
+//  6 : 2R 2G 2B
+//  8 : 3R 3G 2B
+//  9 : 3R 3G 3B
+// 12 : 4R 4G 4B
+
+module arcade_fx #(parameter WIDTH=320, DW=8)
+(
+	input         clk_video,
+	input         ce_pix,
+
+	input[DW-1:0] RGB_in,
+	input         HBlank,
+	input         VBlank,
+	input         HSync,
+	input         VSync,
+
+	output        VGA_CLK,
+	output        VGA_CE,
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,
+
+	output        HDMI_CLK,
+	output        HDMI_CE,
+	output  [7:0] HDMI_R,
+	output  [7:0] HDMI_G,
+	output  [7:0] HDMI_B,
+	output        HDMI_HS,
+	output        HDMI_VS,
+	output        HDMI_DE,
+	output  [1:0] HDMI_SL,
+	
+	input   [2:0] fx,
+	input         forced_scandoubler
+);
+
+assign VGA_CLK = clk_video;
+assign VGA_CE = ce_pix;
+assign VGA_HS = HSync;
+assign VGA_VS = VSync;
+assign VGA_DE = ~(HBlank | VBlank);
+
+generate
+	if(DW == 6) begin
+		assign VGA_R = {RGB_in[5:4],RGB_in[5:4],RGB_in[5:4],RGB_in[5:4]};
+		assign VGA_G = {RGB_in[3:2],RGB_in[3:2],RGB_in[3:2],RGB_in[3:2]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 8) begin
+		assign VGA_R = {RGB_in[7:5],RGB_in[7:5],RGB_in[7:6]};
+		assign VGA_G = {RGB_in[4:2],RGB_in[4:2],RGB_in[4:3]};
+		assign VGA_B = {RGB_in[1:0],RGB_in[1:0],RGB_in[1:0],RGB_in[1:0]};
+	end
+	else if(DW == 9) begin
+		assign VGA_R = {RGB_in[8:6],RGB_in[8:6],RGB_in[8:7]};
+		assign VGA_G = {RGB_in[5:3],RGB_in[5:3],RGB_in[5:4]};
+		assign VGA_B = {RGB_in[2:0],RGB_in[2:0],RGB_in[2:1]};
+	end
+	else begin
+		assign VGA_R = {RGB_in[11:8],RGB_in[11:8]};
+		assign VGA_G = {RGB_in[7:4],RGB_in[7:4]};
+		assign VGA_B = {RGB_in[3:0],RGB_in[3:0]};
+	end
+endgenerate
+
+assign HDMI_CLK = VGA_CLK;
+assign HDMI_SL  = sl[1:0];
+wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
+wire scandoubler = fx || forced_scandoubler;
+
+video_mixer #(WIDTH+4, 1) video_mixer
+(
+	.clk_sys(HDMI_CLK),
+	.ce_pix(VGA_CE),
+	.ce_pix_out(HDMI_CE),
+
+	.scandoubler(scandoubler),
+	.hq2x(fx==1),
+
+	.R(VGA_R[7:4]),
+	.G(VGA_G[7:4]),
+	.B(VGA_B[7:4]),
+
+	.HSync(HSync),
+	.VSync(VSync),
+	.HBlank(HBlank),
+	.VBlank(VBlank),
+
+	.VGA_R(HDMI_R),
+	.VGA_G(HDMI_G),
+	.VGA_B(HDMI_B),
+	.VGA_VS(HDMI_VS),
+	.VGA_HS(HDMI_HS),
+	.VGA_DE(HDMI_DE)
+);
+
+endmodule
+
+//////////////////////////////////////////////////////////
+
+module rram #(parameter AW=16, DW=8, NW=1<<AW)
+(
+	input           wrclock,
+	input  [AW-1:0] wraddress,
+	input  [DW-1:0] data,
+	input           wren,
+
+	input	          rdclock,
+	input	 [AW-1:0] rdaddress,
+	output [DW-1:0] q
+);
+
+altsyncram	altsyncram_component
+(
+	.address_a (wraddress),
+	.address_b (rdaddress),
+	.clock0 (wrclock),
+	.clock1 (rdclock),
+	.data_a (data),
+	.wren_a (wren),
+	.q_b (q),
+	.aclr0 (1'b0),
+	.aclr1 (1'b0),
+	.addressstall_a(1'b0),
+	.addressstall_b(1'b0),
+	.byteena_a(1'b1),
+	.byteena_b(1'b1),
+	.clocken0(1'b1),
+	.clocken1(1'b1),
+	.clocken2(1'b1),
+	.clocken3(1'b1),
+	.data_b({DW{1'b0}}),
+	.eccstatus (),
+	.q_a(),
+	.rden_a (1'b1),
+	.rden_b (1'b1),
+	.wren_b(1'b0)
+);
+
+defparam
+	altsyncram_component.address_aclr_b = "NONE",
+	altsyncram_component.address_reg_b = "CLOCK1",
+	altsyncram_component.clock_enable_input_a = "BYPASS",
+	altsyncram_component.clock_enable_input_b = "BYPASS",
+	altsyncram_component.clock_enable_output_b = "BYPASS",
+	altsyncram_component.intended_device_family = "Cyclone V",
+	altsyncram_component.lpm_type = "altsyncram",
+	altsyncram_component.numwords_a = NW,
+	altsyncram_component.numwords_b = NW,
+	altsyncram_component.operation_mode = "DUAL_PORT",
+	altsyncram_component.outdata_aclr_b = "NONE",
+	altsyncram_component.outdata_reg_b = "UNREGISTERED",
+	altsyncram_component.power_up_uninitialized = "FALSE",
+	altsyncram_component.widthad_a = AW,
+	altsyncram_component.widthad_b = AW,
+	altsyncram_component.width_a = DW,
+	altsyncram_component.width_b = DW,
+	altsyncram_component.width_byteena_a = 1;
+
+endmodule

sys/build_id.tcl

@@ -0,0 +1,69 @@
+
+# Build TimeStamp Verilog Module
+# Jeff Wiencrot - 8/1/2011
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Build CDF file
+# Sorgelig - 17/2/2018
+proc generateCDF {revision device outpath} {
+
+	set outputFileName "jtag.cdf"
+	set outputFile [open $outputFileName "w"]
+
+	puts $outputFile "JedecChain;"
+	puts $outputFile "	FileRevision(JESD32A);"
+	puts $outputFile "	DefaultMfr(6E);"
+	puts $outputFile ""
+	puts $outputFile "	P ActionCode(Ign)"
+	puts $outputFile "		Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
+	puts $outputFile "	P ActionCode(Cfg)"
+	puts $outputFile "		Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
+	puts $outputFile "ChainEnd;"
+	puts $outputFile ""
+	puts $outputFile "AlteraBegin;"
+	puts $outputFile "	ChainType(JTAG);"
+	puts $outputFile "AlteraEnd;"
+}
+
+set project_name [lindex $quartus(args) 1]
+set revision [lindex $quartus(args) 2]
+
+if {[project_exists $project_name]} {
+    if {[string equal "" $revision]} {
+        project_open $project_name -revision [get_current_revision $project_name]
+    } else {
+        project_open $project_name -revision $revision
+    }
+} else {
+    post_message -type error "Project $project_name does not exist"
+    exit
+}
+
+set device  [get_global_assignment -name DEVICE]
+set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
+
+if [is_project_open] {
+    project_close
+}
+
+generateBuildID_Verilog
+generateCDF $revision $device $outpath

sys/hdmi_config.sv

@@ -0,0 +1,202 @@
+
+module hdmi_config
+(
+	//	Host Side
+	input			iCLK,
+	input			iRST_N,
+	
+	input       dvi_mode,
+	input       audio_96k,
+
+	//	I2C Side
+	output		I2C_SCL,
+	inout 		I2C_SDA
+);
+
+//	Internal Registers/Wires
+reg        mI2C_GO = 0;
+wire       mI2C_END;
+wire       mI2C_ACK;
+reg [15:0] LUT_DATA;
+reg  [7:0] LUT_INDEX = 0;
+
+i2c #(50_000_000, 20_000) i2c_av
+(
+	.CLK(iCLK),
+
+	.I2C_SCL(I2C_SCL),		//	I2C CLOCK
+	.I2C_SDA(I2C_SDA),		//	I2C DATA
+
+	.I2C_DATA({8'h72,init_data[LUT_INDEX]}),	//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]. 0x72 is the Slave Address of the ADV7513 chip!
+	.START(mI2C_GO),    		//	START transfer
+	.END(mI2C_END),			//	END transfer 
+	.ACK(mI2C_ACK) 			//	ACK
+);
+
+//////////////////////	Config Control	////////////////////////////
+always@(posedge iCLK or negedge iRST_N) begin
+	reg  [1:0] mSetup_ST = 0;
+
+	if(!iRST_N) begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+	end else begin
+		if(init_data[LUT_INDEX] != 16'hFFFF) begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1: if(~mI2C_END) mSetup_ST	<=	2;
+			2:	begin
+					mI2C_GO <= 0;
+					if(mI2C_END) begin
+						mSetup_ST <= 0;
+						if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
+					end
+				end
+			endcase
+		end
+	end
+end
+
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT   //////////////////////////
+
+wire [15:0] init_data[58] = 
+'{
+	16'h9803,					// ADI required Write.
+
+	{8'hD6, 8'b1100_0000},	// [7:6] HPD Control...
+									// 00 = HPD is from both HPD pin or CDC HPD
+									// 01 = HPD is from CDC HPD
+									// 10 = HPD is from HPD pin
+									// 11 = HPD is always high
+
+	16'h4110,					// Power Down control
+	16'h9A70,					// ADI required Write.
+	16'h9C30,					// ADI required Write.
+	{8'h9D, 8'b0110_0001},	// [7:4] must be b0110!.
+									// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
+									//	[1:0] must be b01!
+	16'hA2A4,					// ADI required Write.
+	16'hA3A4,					// ADI required Write.
+	16'hE0D0,					// ADI required Write.
+
+
+	16'h35_40,
+	16'h36_D9,
+	16'h37_0A,
+	16'h38_00,
+	16'h39_2D,
+	16'h3A_00,
+
+	{8'h16, 8'b0011_1000},	// Output Format 444 [7]=0.
+									// [6] must be 0!
+									// Colour Depth for Input Video data [5:4] b11 = 8-bit.
+									// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
+									// DDR Input Edge falling [1]=0 (not using DDR atm).
+									// Output Colour Space RGB [0]=0.
+
+	{8'h17, 8'b01100010},   // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
+
+	{8'h18, 8'b0100_0110},	// CSC disabled [7]=0.
+									// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
+									// CSC Equation 3 [4:0] b00110.
+
+
+	{8'h3B, 8'b0000_0000},	// Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
+
+	16'h4000,					// General Control Packet Enable
+
+	{8'h48, 8'b0000_1000},	// [6]=0 Normal bus order!
+									// [5] DDR Alignment.
+									// [4:3] b01 Data right justified (for YCbCr 422 input modes).
+
+	16'h49A8,					// ADI required Write.
+	16'h4C00,					// ADI required Write.
+
+	{8'h55, 8'b0001_0000},	// [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
+									// AVI InfoFrame Valid [4].
+									// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
+									// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
+
+	16'h7301,
+
+	{8'h94, 8'b1000_0000},	// [7]=1 HPD Interrupt ENabled.
+
+	16'h9902,					// ADI required Write.
+	16'h9B18,					// ADI required Write.
+
+	16'h9F00,					// ADI required Write.
+
+	{8'hA1, 8'b0000_0000},	// [6]=1 Monitor Sense Power Down DISabled.
+	
+	16'hA408,					// ADI required Write.
+	16'hA504,					// ADI required Write.
+	16'hA600,					// ADI required Write.
+	16'hA700,					// ADI required Write.
+	16'hA800,					// ADI required Write.
+	16'hA900,					// ADI required Write.
+	16'hAA00,					// ADI required Write.
+	16'hAB40,					// ADI required Write.
+	
+	{8'hAF, 6'b0000_01,~dvi_mode,1'b0},	// [7]=0 HDCP Disabled.
+									// [6:5] must be b00!
+									// [4]=0 Current frame is unencrypted
+									// [3:2] must be b01!
+									//	[1]=1 HDMI Mode.
+									// [0] must be b0!
+
+	16'hB900,					// ADI required Write.
+
+	{8'hBA, 8'b0110_0000},	// [7:5] Input Clock delay...
+									// b000 = -1.2ns.
+									// b001 = -0.8ns.
+									// b010 = -0.4ns.
+									// b011 = No delay.
+									// b100 = 0.4ns.
+									// b101 = 0.8ns.
+									// b110 = 1.2ns.
+									// b111 = 1.6ns.
+					
+	16'hBB00,					// ADI required Write.
+	
+	16'hDE9C,					// ADI required Write.
+	16'hE460,					// ADI required Write.
+	16'hFA7D,					// Nbr of times to search for good phase
+
+	
+									// (Audio stuff on Programming Guide, Page 66)...
+	
+	{8'h0A, 8'b0000_0000},	// [6:4] Audio Select. b000 = I2S.
+									// [3:2] Audio Mode. (HBR stuff, leave at 00!).
+
+	{8'h0B, 8'b0000_1110},	//
+									
+	{8'h0C, 8'b0000_0100},	// [7] 0 = Use sampling rate from I2S stream.   1 = Use samp rate from I2C Register.
+									// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
+									// [2] 1 = I2S0 Enable.
+									// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
+									
+	{8'h0D, 8'b0001_0000},	// [4:0] I2S Bit (Word) Width for Right-Justified.
+	{8'h14, 8'b0000_0010},	// [3:0] Audio Word Length. b0010 = 16 bits.
+	{8'h15, audio_96k, 7'b010_0000},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
+									// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
+
+	// Audio Clock Config
+	16'h0100,					//  
+	audio_96k ? 16'h0230 : 16'h0218,	// Set N Value 12288/6144
+	16'h0300,					//
+
+	16'h0701,					//
+	16'h0822,					// Set CTS Value 74250
+	16'h090A,					//
+
+	16'hFFFF 				   // END
+};
+
+////////////////////////////////////////////////////////////////////
+
+endmodule

sys/hps_io.v

@@ -0,0 +1,734 @@
+//
+// hps_io.v
+//
+// mist_io-like module for MiSTer
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2017,2018 Sorgelig
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = CLK_SYS/(PS2DIV*2)
+//
+
+// WIDE=1 for 16 bit file I/O
+// VDNUM 1-4
+module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
+(
+	input             clk_sys,
+	inout      [44:0] HPS_BUS,
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	output reg [15:0] joystick_0,
+	output reg [15:0] joystick_1,
+	output reg [15:0] joystick_2,
+	output reg [15:0] joystick_3,
+	output reg [15:0] joystick_4,
+	output reg [15:0] joystick_5,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output reg [15:0] joystick_analog_2,
+	output reg [15:0] joystick_analog_3,
+	output reg [15:0] joystick_analog_4,
+	output reg [15:0] joystick_analog_5,
+
+	output      [1:0] buttons,
+	output            forced_scandoubler,
+
+	output reg [31:0] status,
+	input      [31:0] status_in,
+	input             status_set,
+
+	//toggle to force notify of video mode change
+	input             new_vmode,
+
+	// SD config
+	output reg [VD:0] img_mounted,  // signaling that new image has been mounted
+	output reg        img_readonly, // mounted as read only. valid only for active bit in img_mounted
+	output reg [63:0] img_size,     // size of image in bytes. valid only for active bit in img_mounted
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input      [VD:0] sd_rd,       // only single sd_rd can be active at any given time
+	input      [VD:0] sd_wr,       // only single sd_wr can be active at any given time
+	output reg        sd_ack,
+
+	// do not use in new projects.
+	// CID and CSD are fake except CSD image size field.
+	input             sd_conf,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg [AW:0] sd_buff_addr,
+	output reg [DW:0] sd_buff_dout,
+	input      [DW:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output reg        ioctl_wr,
+	output reg [24:0] ioctl_addr,         // in WIDE mode address will be incremented by 2
+	output reg [DW:0] ioctl_dout,
+	output reg [31:0] ioctl_file_ext,
+	input             ioctl_wait,
+
+	// RTC MSM6242B layout
+	output reg [64:0] RTC,
+
+	// Seconds since 1970-01-01 00:00:00
+	output reg [32:0] TIMESTAMP,
+
+	// UART flags
+	input      [15:0] uart_mode,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk_out,
+	output            ps2_kbd_data_out,
+	input             ps2_kbd_clk_in,
+	input             ps2_kbd_data_in,
+
+	input       [2:0] ps2_kbd_led_status,
+	input       [2:0] ps2_kbd_led_use,
+
+	output            ps2_mouse_clk_out,
+	output            ps2_mouse_data_out,
+	input             ps2_mouse_clk_in,
+	input             ps2_mouse_data_in,
+
+	// ps2 alternative interface.
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+
+	// [24] - toggles with every event
+	output reg [24:0] ps2_mouse = 0
+);
+
+localparam DW = (WIDE) ? 15 : 7;
+localparam AW = (WIDE) ?  7 : 8;
+localparam VD = VDNUM-1;
+
+wire        io_wait  = ioctl_wait;
+wire        io_enable= |HPS_BUS[35:34];
+wire        io_strobe= HPS_BUS[33];
+wire        io_wide  = (WIDE) ? 1'b1 : 1'b0;
+wire [15:0] io_din   = HPS_BUS[31:16];
+reg  [15:0] io_dout;
+
+assign HPS_BUS[37]   = io_wait;
+assign HPS_BUS[36]   = clk_sys;
+assign HPS_BUS[32]   = io_wide;
+assign HPS_BUS[15:0] = io_dout;
+
+reg [7:0] cfg;
+assign buttons = cfg[1:0];
+//cfg[2] - vga_scaler handled in sys_top
+//cfg[3] - csync handled in sys_top
+assign forced_scandoubler = cfg[4];
+//cfg[5] - ypbpr handled in sys_top
+
+// command byte read by the io controller
+wire [15:0] sd_cmd =
+{
+	2'b00,
+	(VDNUM>=4) ? sd_wr[3] : 1'b0,
+	(VDNUM>=3) ? sd_wr[2] : 1'b0,
+	(VDNUM>=2) ? sd_wr[1] : 1'b0,
+
+	(VDNUM>=4) ? sd_rd[3] : 1'b0,
+	(VDNUM>=3) ? sd_rd[2] : 1'b0,
+	(VDNUM>=2) ? sd_rd[1] : 1'b0,
+
+	4'h5, sd_conf, 1'b1,
+	sd_wr[0],
+	sd_rd[0]
+};
+
+///////////////// calc video parameters //////////////////
+
+wire clk_100 = HPS_BUS[43];
+wire clk_vid = HPS_BUS[42];
+wire ce_pix  = HPS_BUS[41];
+wire de      = HPS_BUS[40];
+wire hs      = HPS_BUS[39];
+wire vs      = HPS_BUS[38];
+wire vs_hdmi = HPS_BUS[44];
+
+reg [31:0] vid_hcnt = 0;
+reg [31:0] vid_vcnt = 0;
+reg  [7:0] vid_nres = 0;
+integer hcnt;
+
+always @(posedge clk_vid) begin
+	integer vcnt;
+	reg old_vs= 0, old_de = 0, old_vmode = 0;
+	reg calch = 0;
+
+	if(ce_pix) begin
+		old_vs <= vs;
+		old_de <= de;
+
+		if(~vs & ~old_de & de) vcnt <= vcnt + 1;
+		if(calch & de) hcnt <= hcnt + 1;
+		if(old_de & ~de) calch <= 0;
+
+		if(old_vs & ~vs) begin
+			if(hcnt && vcnt) begin
+				old_vmode <= new_vmode;
+				if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
+				vid_hcnt <= hcnt;
+				vid_vcnt <= vcnt;
+			end
+			vcnt <= 0;
+			hcnt <= 0;
+			calch <= 1;
+		end
+	end
+end
+
+reg [31:0] vid_htime = 0;
+reg [31:0] vid_vtime = 0;
+reg [31:0] vid_pix = 0;
+
+always @(posedge clk_100) begin
+	integer vtime, htime, hcnt;
+	reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
+	reg calch = 0;
+
+	old_vs <= vs;
+	old_hs <= hs;
+
+	old_vs2 <= old_vs;
+	old_hs2 <= old_hs;
+
+	vtime <= vtime + 1'd1;
+	htime <= htime + 1'd1;
+
+	if(~old_vs2 & old_vs) begin
+		vid_pix <= hcnt;
+		vid_vtime <= vtime;
+		vtime <= 0;
+		hcnt <= 0;
+	end
+
+	if(old_vs2 & ~old_vs) calch <= 1;
+
+	if(~old_hs2 & old_hs) begin
+		vid_htime <= htime;
+		htime <= 0;
+	end
+
+	old_de   <= de;
+	old_de2  <= old_de;
+
+	if(calch & old_de) hcnt <= hcnt + 1;
+	if(old_de2 & ~old_de) calch <= 0;
+end
+
+reg [31:0] vid_vtime_hdmi;
+always @(posedge clk_100) begin
+	integer vtime;
+	reg old_vs, old_vs2;
+
+	old_vs <= vs_hdmi;
+	old_vs2 <= old_vs;
+
+	vtime <= vtime + 1'd1;
+
+	if(~old_vs2 & old_vs) begin
+		vid_vtime_hdmi <= vtime;
+		vtime <= 0;
+	end
+end
+
+
+/////////////////////////////////////////////////////////
+
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+
+always@(posedge clk_sys) begin
+	reg [15:0] cmd;
+	reg  [9:0] byte_cnt;   // counts bytes
+	reg  [2:0] b_wr;
+	reg  [2:0] stick_idx;
+	reg        ps2skip = 0;
+	reg  [3:0] stflg = 0;
+	reg [31:0] status_req;
+	reg        old_status_set = 0;
+
+	old_status_set <= status_set;
+	if(~old_status_set & status_set) begin
+		stflg <= stflg + 1'd1;
+		status_req <= status_in;
+	end
+
+	sd_buff_wr <= b_wr[0];
+	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+	b_wr <= (b_wr<<1);
+
+	{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
+
+	if(~io_enable) begin
+		if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
+		if(cmd == 5 && !ps2skip) begin
+			ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+			if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+			if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+			if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+		end
+		if(cmd == 'h22) RTC[64] <= ~RTC[64];
+		if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
+		cmd <= 0;
+		byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+		io_dout <= 0;
+		ps2skip <= 0;
+	end else begin
+		if(io_strobe) begin
+
+			io_dout <= 0;
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
+
+			if(byte_cnt == 0) begin
+				cmd <= io_din;
+
+				case(io_din)
+					'h19: sd_ack_conf <= 1;
+					'h17,
+					'h18: sd_ack <= 1;
+					'h29: io_dout <= {4'hA, stflg};
+					'h2B: io_dout <= 1;
+				endcase
+
+				sd_buff_addr <= 0;
+				img_mounted <= 0;
+				if(io_din == 5) ps2_key_raw <= 0;
+			end else begin
+
+				case(cmd)
+					// buttons and switches
+					'h01: cfg        <= io_din[7:0];
+					'h02: joystick_0 <= io_din;
+					'h03: joystick_1 <= io_din;
+					'h10: joystick_2 <= io_din;
+					'h11: joystick_3 <= io_din;
+					'h12: joystick_4 <= io_din;
+					'h13: joystick_5 <= io_din;
+
+					// store incoming ps2 mouse bytes
+					'h04: begin
+							mouse_data <= io_din[7:0];
+							mouse_we   <= 1;
+							if(&io_din[15:8]) ps2skip <= 1;
+							if(~&io_din[15:8] & ~ps2skip) begin
+								case(byte_cnt)
+									1: ps2_mouse[7:0]   <= io_din[7:0];
+									2: ps2_mouse[15:8]  <= io_din[7:0];
+									3: ps2_mouse[23:16] <= io_din[7:0];
+								endcase
+							end
+						end
+
+					// store incoming ps2 keyboard bytes
+					'h05: begin
+							if(&io_din[15:8]) ps2skip <= 1;
+							if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
+							kbd_data <= io_din[7:0];
+							kbd_we <= 1;
+						end
+
+					// reading config string, returning a byte from string
+					'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
+
+					// reading sd card status
+					'h16: case(byte_cnt)
+								1: io_dout <= sd_cmd;
+								2: io_dout <= sd_lba[15:0];
+								3: io_dout <= sd_lba[31:16];
+							endcase
+
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					'h17: begin
+							sd_buff_dout <= io_din[DW:0];
+							b_wr <= 1;
+						end
+
+					// reading sd card write data
+					'h18: begin
+							if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+							io_dout <= sd_buff_din;
+						end
+
+					// joystick analog
+					'h1a: case(byte_cnt)
+								1: stick_idx <= io_din[2:0]; // first byte is joystick index
+								2: case(stick_idx)
+										0: joystick_analog_0 <= io_din;
+										1: joystick_analog_1 <= io_din;
+										2: joystick_analog_2 <= io_din;
+										3: joystick_analog_3 <= io_din;
+										4: joystick_analog_4 <= io_din;
+										5: joystick_analog_5 <= io_din;
+									endcase
+							endcase
+
+					// notify image selection
+					'h1c: begin
+							img_mounted  <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
+							img_readonly <= io_din[7];
+						end
+
+					// send image info
+					'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
+
+					// status, 32bit version
+					'h1e: if(byte_cnt==1) status[15:0] <= io_din;
+								else if(byte_cnt==2) status[31:16] <= io_din;
+
+					// reading keyboard LED status
+					'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
+
+					// reading ps2 keyboard/mouse control
+					'h21: if(byte_cnt == 1) begin
+								io_dout <= kbd_data_host;
+								kbd_rd <= 1;
+							end
+							else
+							if(byte_cnt == 2) begin
+								io_dout <= mouse_data_host;
+								mouse_rd <= 1;
+							end
+					//RTC
+					'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+					//Video res.
+					'h23: case(byte_cnt)
+								1: io_dout <= vid_nres;
+								2: io_dout <= vid_hcnt[15:0];
+								3: io_dout <= vid_hcnt[31:16];
+								4: io_dout <= vid_vcnt[15:0];
+								5: io_dout <= vid_vcnt[31:16];
+								6: io_dout <= vid_htime[15:0];
+								7: io_dout <= vid_htime[31:16];
+								8: io_dout <= vid_vtime[15:0];
+								9: io_dout <= vid_vtime[31:16];
+							  10: io_dout <= vid_pix[15:0];
+							  11: io_dout <= vid_pix[31:16];
+							  12: io_dout <= vid_vtime_hdmi[15:0];
+							  13: io_dout <= vid_vtime_hdmi[31:16];
+							endcase
+
+					//RTC
+					'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
+
+					//UART flags
+					'h28: io_dout <= uart_mode;
+
+					//status set
+					'h29: case(byte_cnt)
+								1: io_dout <= status_req[15:0];
+								2: io_dout <= status_req[31:16];
+							endcase
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+reg  [7:0] kbd_data;
+reg        kbd_we;
+wire [8:0] kbd_data_host;
+reg        kbd_rd;
+
+ps2_device keyboard
+(
+	.clk_sys(clk_sys),
+
+	.wdata(kbd_data),
+	.we(kbd_we),
+
+	.ps2_clk(clk_ps2),
+	.ps2_clk_out(ps2_kbd_clk_out),
+	.ps2_dat_out(ps2_kbd_data_out),
+
+	.ps2_clk_in(ps2_kbd_clk_in  || !PS2WE),
+	.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
+
+	.rdata(kbd_data_host),
+	.rd(kbd_rd)
+);
+
+reg  [7:0] mouse_data;
+reg        mouse_we;
+wire [8:0] mouse_data_host;
+reg        mouse_rd;
+
+ps2_device mouse
+(
+	.clk_sys(clk_sys),
+
+	.wdata(mouse_data),
+	.we(mouse_we),
+
+	.ps2_clk(clk_ps2),
+	.ps2_clk_out(ps2_mouse_clk_out),
+	.ps2_dat_out(ps2_mouse_data_out),
+
+	.ps2_clk_in(ps2_mouse_clk_in  || !PS2WE),
+	.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
+
+	.rdata(mouse_data_host),
+	.rd(mouse_rd)
+);
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+localparam UIO_FILE_INFO    = 8'h56;
+
+always@(posedge clk_sys) begin
+	reg [15:0] cmd;
+	reg  [2:0] cnt;
+	reg        has_cmd;
+	reg [24:0] addr;
+	reg        wr;
+
+	ioctl_wr <= wr;
+	wr <= 0;
+
+	if(~io_enable) has_cmd <= 0;
+	else begin
+		if(io_strobe) begin
+
+			if(!has_cmd) begin
+				cmd <= io_din;
+				has_cmd <= 1;
+				cnt <= 0;
+			end else begin
+
+				case(cmd)
+					UIO_FILE_INFO:
+						if(~cnt[1]) begin
+							case(cnt)
+								0: ioctl_file_ext[31:16] <= io_din;
+								1: ioctl_file_ext[15:00] <= io_din;
+							endcase
+							cnt <= cnt + 1'd1;
+						end
+
+					UIO_FILE_INDEX:
+						begin
+							ioctl_index <= io_din[7:0];
+						end
+
+					UIO_FILE_TX:
+						begin
+							if(io_din[7:0]) begin
+								addr <= 0;
+								ioctl_download <= 1;
+							end else begin
+								ioctl_addr <= addr;
+								ioctl_download <= 0;
+							end
+						end
+
+					UIO_FILE_TX_DAT:
+						begin
+							ioctl_addr <= addr;
+							ioctl_dout <= io_din[DW:0];
+							wr   <= 1;
+							addr <= addr + (WIDE ? 2'd2 : 2'd1);
+						end
+				endcase
+			end
+		end
+	end
+end
+
+endmodule
+
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ps2_device #(parameter PS2_FIFO_BITS=5)
+(
+	input        clk_sys,
+
+	input  [7:0] wdata,
+	input        we,
+
+	input        ps2_clk,
+	output reg   ps2_clk_out,
+	output reg   ps2_dat_out,
+	output reg   tx_empty,
+
+	input        ps2_clk_in,
+	input        ps2_dat_in,
+
+	output [8:0] rdata,
+	input        rd
+);
+
+
+(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
+
+reg [PS2_FIFO_BITS-1:0] wptr;
+reg [PS2_FIFO_BITS-1:0] rptr;
+
+reg [2:0] rx_state = 0;
+reg [3:0] tx_state = 0;
+
+reg       has_data;
+reg [7:0] data;
+assign    rdata = {has_data, data};
+
+always@(posedge clk_sys) begin
+	reg [7:0] tx_byte;
+	reg parity;
+	reg r_inc;
+	reg old_clk;
+	reg [1:0] timeout;
+
+	reg [3:0] rx_cnt;
+
+	reg c1,c2,d1;
+
+	tx_empty <= ((wptr == rptr) && (tx_state == 0));
+
+	if(we) begin
+		fifo[wptr] <= wdata;
+		wptr <= wptr + 1'd1;
+	end
+
+	if(rd) has_data <= 0;
+
+	c1 <= ps2_clk_in;
+	c2 <= c1;
+	d1 <= ps2_dat_in;
+	if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
+		rx_state <= rx_state + 1'b1;
+		ps2_dat_out <= 1;
+	end
+
+	old_clk <= ps2_clk;
+	if(~old_clk & ps2_clk) begin
+
+		if(rx_state) begin
+			case(rx_state)
+				1: begin
+						rx_state <= rx_state + 1'b1;
+						rx_cnt <= 0;
+					end
+
+				2: begin
+						if(rx_cnt <= 7) data <= {d1, data[7:1]};
+						else rx_state <= rx_state + 1'b1;
+						rx_cnt <= rx_cnt + 1'b1;
+					end
+
+				3: if(d1) begin
+						rx_state <= rx_state + 1'b1;
+						ps2_dat_out <= 0;
+					end
+
+				4: begin
+						ps2_dat_out <= 1;
+						has_data <= 1;
+						rx_state <= 0;
+					end
+			endcase
+		end else begin
+
+			// transmitter is idle?
+			if(tx_state == 0) begin
+				// data in fifo present?
+				if(c2 && c1 && d1 && wptr != rptr) begin
+
+					timeout <= timeout - 1'd1;
+					if(!timeout) begin
+						tx_byte <= fifo[rptr];
+						rptr <= rptr + 1'd1;
+
+						// reset parity
+						parity <= 1;
+
+						// start transmitter
+						tx_state <= 1;
+
+						// put start bit on data line
+						ps2_dat_out <= 0;			// start bit is 0
+					end
+				end
+			end else begin
+
+				// transmission of 8 data bits
+				if((tx_state >= 1)&&(tx_state < 9)) begin
+					ps2_dat_out <= tx_byte[0];	          // data bits
+					tx_byte[6:0] <= tx_byte[7:1]; // shift down
+					if(tx_byte[0])
+						parity <= !parity;
+				end
+
+				// transmission of parity
+				if(tx_state == 9) ps2_dat_out <= parity;
+
+				// transmission of stop bit
+				if(tx_state == 10) ps2_dat_out <= 1;    // stop bit is 1
+
+				// advance state machine
+				if(tx_state < 11) tx_state <= tx_state + 1'd1;
+					else tx_state <= 0;
+			end
+		end
+	end
+
+	if(~old_clk & ps2_clk) ps2_clk_out <= 1;
+	if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
+
+end
+
+endmodule

sys/hq2x.sv

@@ -0,0 +1,385 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017,2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input             clk,
+	input             ce_x4,
+	input  [DWIDTH:0] inputpixel,
+	input             mono,
+	input             disable_hq2x,
+	input             reset_frame,
+	input             reset_line,
+	input       [1:0] read_y,
+	input             hblank,
+	output [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = $clog2(LENGTH)-1;
+localparam DWIDTH = HALF_DEPTH ? 11 : 23;
+localparam DWIDTH1 = DWIDTH+1;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
+reg [23:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] cyc;
+
+reg  curbuf;
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
+wire [23:0] blend_result_pre;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
+
+wire [DWIDTH:0] Curr20tmp;
+wire     [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
+wire [DWIDTH:0] Curr21tmp;
+wire     [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [23:0] h2rgb;
+	input [11:0] v;
+begin
+	h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
+end
+endfunction
+
+function [11:0] rgb2h;
+	input [23:0] v;
+begin
+	rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(offs),
+	.rdbuf0(prevbuf),
+	.rdbuf1(curbuf),
+	.q0(Curr20tmp),
+	.q1(Curr21tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg     [AWIDTH+1:0] read_x;
+reg     [AWIDTH+1:0] wrout_addr; 
+reg                  wrout_en;
+reg  [DWIDTH1*4-1:0] wrdata, wrdata_pre;
+wire [DWIDTH1*4-1:0] outpixel_x4;
+reg  [DWIDTH1*2-1:0] outpixel_x2;
+
+assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
+
+hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
+(
+	.clock(clk),
+
+	.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
+	.q(outpixel_x4),
+
+	.data(wrdata),
+	.wraddress(wrout_addr),
+	.wren(wrout_en)
+);
+
+wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
+
+reg [AWIDTH:0] offs;
+always @(posedge clk) begin
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+		if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
+
+		if(~&offs) begin
+			if (cyc == 1) begin
+				Prev2 <= Curr20;
+				Curr2 <= Curr21;
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+
+			case({cyc[1],^cyc})
+				0: wrdata[DWIDTH:0]                   <= blend_result;
+				1: wrdata[DWIDTH1+DWIDTH:DWIDTH1]     <= blend_result;
+				2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
+				3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
+			endcase
+
+			if(cyc==3) begin
+				offs <= offs + 1'd1;
+				wrout_addr <= {offs, curbuf};
+				wrout_en <= 1;
+			end
+		end
+
+		if(cyc==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		cyc <= cyc + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			cyc <= 0;
+			curbuf <= ~curbuf;
+			prevbuf <= curbuf;
+			{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
+			if(old_reset_frame & ~reset_frame) begin
+				curbuf <= 0;
+				prevbuf <= 0;
+			end
+		end
+		
+		if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
+		if(hblank) read_x <= 0;
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf0, rdbuf1,
+	output[DWIDTH:0] q0,q1,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = $clog2(LENGTH)-1;
+	wire  [DWIDTH:0] out[2];
+	assign q0 = out[rdbuf0];
+	assign q1 = out[rdbuf1];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input                   clock,
+	input        [DWIDTH:0] data,
+	input        [AWIDTH:0] rdaddress,
+	input        [AWIDTH:0] wraddress,
+	input                   wren,
+	output logic [DWIDTH:0] q
+);
+
+logic [DWIDTH:0] ram[0:NUMWORDS-1];
+
+always_ff@(posedge clock) begin
+	if(wren) ram[wraddress] <= data;
+	q <= ram[rdaddress];
+end
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [23:0] rgb1,
+	input [23:0] rgb2,
+	output result
+);
+
+	wire [7:0] r = rgb1[7:1]   - rgb2[7:1];
+	wire [7:0] g = rgb1[15:9]  - rgb2[15:9];
+	wire [7:0] b = rgb1[23:17] - rgb2[23:17];
+	wire [8:0] t = $signed(r) + $signed(b);
+	wire [8:0] gx = {g[7], g};
+	wire [9:0] y = $signed(t) + $signed(gx);
+	wire [8:0] u = $signed(r) - $signed(b);
+	wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-96..96)
+	wire y_inside = (y < 10'h60 || y >= 10'h3a0);
+
+	// if u is inside (-16, 16)
+	wire u_inside = (u < 9'h10 || u >= 9'h1f0);
+
+	// if v is inside (-24, 24)
+	wire v_inside = (v < 10'h18 || v >= 10'h3e8);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [7:0] A,
+	input  [7:0] B,
+	input  [7:0] C,
+	output [7:0] O
+);
+
+	function  [10:0] mul8x3;
+		input   [7:0] op1;
+		input   [2:0] op2;
+	begin
+		mul8x3 = 11'd0;
+		if(op2[0]) mul8x3 = mul8x3 + op1;
+		if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
+		if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [10:0] Amul = mul8x3(A, Op[7:5]);
+	wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
+	wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
+	wire [10:0] At =  Amul;
+	wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [11:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[11:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [23:0] E,
+	input  [23:0] A,
+	input  [23:0] B,
+	input  [23:0] D,
+	input  [23:0] F,
+	input  [23:0] H,
+	output [23:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			 8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			 9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = {11{1'bx}};
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [23:0] Input1 = E;
+	wire [23:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [23:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[7:0],   Input2[7:0],   Input3[7:0],   Result[7:0]);
+	InnerBlend inner_blend2(op, Input1[15:8],  Input2[15:8],  Input3[15:8],  Result[15:8]);
+	InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
+endmodule

sys/i2c.v

@@ -0,0 +1,69 @@
+
+module i2c
+(
+	input        CLK,
+
+	input        START,
+	input [23:0] I2C_DATA,
+	output reg   END = 1,
+	output reg   ACK = 0,
+
+	//I2C bus
+	output       I2C_SCL,
+ 	inout        I2C_SDA
+);
+
+
+//	Clock Setting
+parameter CLK_Freq = 50_000_000;	//	50 MHz
+parameter I2C_Freq = 400_000;		//	400 KHz
+
+reg I2C_CLOCK;
+always@(negedge CLK) begin
+	integer mI2C_CLK_DIV = 0;
+	if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin
+		mI2C_CLK_DIV <= mI2C_CLK_DIV + 1;
+	end else	begin
+		mI2C_CLK_DIV <= 0;
+		I2C_CLOCK    <= ~I2C_CLOCK;
+	end
+end
+
+assign I2C_SCL = SCLK | I2C_CLOCK;
+assign I2C_SDA = SDO  ? 1'bz : 1'b0;
+
+reg SCLK = 1, SDO = 1;
+
+always @(posedge CLK) begin
+	reg old_clk;
+	reg old_st;
+
+	reg  [5:0] SD_COUNTER = 'b111111;
+	reg [0:31] SD;
+
+	old_clk <= I2C_CLOCK;
+	old_st  <= START;
+
+	if(~old_st && START) begin
+		SCLK <= 1;
+		SDO  <= 1;
+		ACK  <= 0;
+		END  <= 0;
+		SD   <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011};
+		SD_COUNTER <= 0;
+	end else begin
+		if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
+			SD_COUNTER <= SD_COUNTER + 6'd1;	
+			case(SD_COUNTER)
+				      01: SCLK <= 0;
+				10,19,28: ACK  <= ACK | I2C_SDA;
+				      29: SCLK <= 1;
+				      32: END  <= 1;
+			endcase
+		end
+
+		if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]];
+	end
+end
+
+endmodule

sys/i2s.v

@@ -0,0 +1,136 @@
+
+module i2s
+#(
+	parameter CLK_RATE   = 50000000,
+	parameter AUDIO_DW   = 16,
+	parameter AUDIO_RATE = 96000
+)
+(
+	input      reset,
+	input      clk_sys,
+	input      half_rate,
+
+	output reg sclk,
+	output reg lrclk,
+	output reg sdata,
+
+	input [AUDIO_DW-1:0]	left_chan,
+	input [AUDIO_DW-1:0]	right_chan
+);
+
+localparam WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
+localparam ERROR_BASE            = 10000;
+localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
+
+reg lpf_ce;
+wire [AUDIO_DW-1:0] al, ar;
+
+lpf_i2s lpf_l
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+   .IDATA(left_chan),
+   .ODATA(al)
+);
+
+lpf_i2s lpf_r
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+
+   .IDATA(right_chan),
+   .ODATA(ar)
+);
+
+always @(posedge clk_sys) begin
+	reg [31:0] count_q;
+	reg [31:0] error_q;
+	reg  [7:0] bit_cnt;
+	reg        skip = 0;
+
+	reg [AUDIO_DW-1:0] left;
+	reg [AUDIO_DW-1:0] right;
+
+	reg msclk;
+	reg ce;
+	
+	lpf_ce <= 0;
+
+	if (reset) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		ce        <= 0;
+		bit_cnt   <= 1;
+		lrclk     <= 1;
+		sclk      <= 1;
+		msclk     <= 1;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		sclk <= msclk;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) begin
+				msclk <= ~msclk;
+				if(msclk) begin
+					skip <= ~skip;
+					if(skip) lpf_ce <= 1;
+					if(bit_cnt >= AUDIO_DW) begin
+						bit_cnt <= 1;
+						lrclk <= ~lrclk;
+						if(lrclk) begin
+							left  <= al;
+							right <= ar;
+						end
+					end
+					else begin
+						bit_cnt <= bit_cnt + 1'd1;
+					end
+					sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
+				end
+			end
+		end
+	end
+end
+
+endmodule
+
+module lpf_i2s
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule

sys/osd.v

@@ -0,0 +1,195 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd
+(
+	input         clk_sys,
+
+	input         io_osd,
+	input         io_strobe,
+	input  [15:0] io_din,
+
+	input         clk_video,
+	input  [23:0] din,
+	output [23:0] dout,
+	input         de_in,
+	output reg    de_out,
+	output reg    osd_status
+);
+
+parameter  OSD_COLOR    =  3'd4;
+parameter  OSD_X_OFFSET = 12'd0;
+parameter  OSD_Y_OFFSET = 12'd0;
+
+localparam OSD_WIDTH    = 12'd256;
+localparam OSD_HEIGHT   = 12'd64;
+
+reg        osd_enable;
+reg  [7:0] osd_buffer[4096];
+
+reg        info = 0;
+reg  [8:0] infoh;
+reg  [8:0] infow;
+reg [11:0] infox;
+reg [21:0] infoy;
+reg [21:0] hrheight;
+
+always@(posedge clk_sys) begin
+	reg [11:0] bcnt;
+	reg  [7:0] cmd;
+	reg        has_cmd;
+	reg        old_strobe;
+	reg        highres = 0;
+
+	hrheight <= info ? infoh : (OSD_HEIGHT<<highres);
+
+	old_strobe <= io_strobe;
+
+	if(~io_osd) begin
+		bcnt <= 0;
+		has_cmd <= 0;
+		cmd <= 0;
+		if(cmd[7:4] == 4) osd_enable <= cmd[0];
+	end else begin
+		if(~old_strobe & io_strobe) begin
+			if(!has_cmd) begin
+				has_cmd <= 1;
+				cmd <= io_din[7:0];
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(io_din[7:4] == 4) begin
+					if(!io_din[0]) {osd_status,highres} <= 0;
+					else {osd_status,info} <= {~io_din[2],io_din[2]};
+					bcnt <= 0;
+				end
+				// command 0x20: OSDCMDWRITE
+				if(io_din[7:4] == 2) begin
+					if(io_din[3]) highres <= 1;
+					bcnt <= {io_din[3:0], 8'h00};
+				end
+			end else begin
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(cmd[7:4] == 4) begin
+					if(bcnt == 0) infox <= io_din[11:0];
+					if(bcnt == 1) infoy <= io_din[11:0];
+					if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
+					if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
+				end
+
+				// command 0x20: OSDCMDWRITE
+				if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0];
+
+				bcnt <= bcnt + 1'd1;
+			end
+		end
+	end
+end
+
+reg ce_pix;
+always @(negedge clk_video) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg deD;
+
+	cnt <= cnt + 1;
+	deD <= de_in;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(~deD && de_in) cnt <= 0;
+
+	if(deD && ~de_in) begin
+		pixsz  <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
+		pixcnt <= 0;
+	end
+end
+
+reg [2:0] osd_de;
+reg       osd_pixel;
+
+always @(posedge clk_video) begin
+	reg        deD;
+	reg  [1:0] osd_div;
+	reg  [1:0] multiscan;
+	reg  [7:0] osd_byte; 
+	reg [23:0] h_cnt;
+	reg [21:0] v_cnt;
+	reg [21:0] dsp_width;
+	reg [21:0] osd_vcnt;
+	reg [21:0] h_osd_start;
+	reg [21:0] v_osd_start;
+	reg [21:0] osd_hcnt;
+	reg        osd_de1,osd_de2;
+	reg  [1:0] osd_en;
+
+	if(ce_pix) begin
+
+		deD <= de_in;
+		if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
+
+		if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
+		if (h_cnt == h_osd_start) begin
+			osd_de[0] <= osd_en[1] && hrheight && (osd_vcnt < hrheight);
+			osd_hcnt <= 0;
+		end
+		if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
+
+		// falling edge of de
+		if(!de_in && deD) dsp_width <= h_cnt[21:0];
+
+		// rising edge of de
+		if(de_in && !deD) begin
+			h_cnt <= 0;
+			v_cnt <= v_cnt + 1'd1;
+			h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
+
+			if(h_cnt > {dsp_width, 2'b00}) begin
+				v_cnt <= 0;
+
+				osd_en <= (osd_en << 1) | osd_enable;
+				if(~osd_enable) osd_en <= 0;
+
+				if(v_cnt<320) begin
+					multiscan <= 0;
+					v_osd_start <= info ? infoy : (((v_cnt-hrheight)>>1) + OSD_Y_OFFSET);
+				end
+				else if(v_cnt<640) begin
+					multiscan <= 1;
+					v_osd_start <= info ? (infoy<<1) : (((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET);
+				end
+				else if(v_cnt<960) begin
+					multiscan <= 2;
+					v_osd_start <= info ? (infoy + (infoy << 1)) : (((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET);
+				end
+				else begin
+					multiscan <= 3;
+					v_osd_start <= info ? (infoy<<2) : (((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET);
+				end
+			end
+
+			osd_div <= osd_div + 1'd1;
+			if(osd_div == multiscan) begin
+				osd_div <= 0;
+				if(~&osd_vcnt) osd_vcnt <= osd_vcnt + 1'd1;
+			end
+			if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
+		end
+
+		osd_byte  <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
+		osd_pixel <= osd_byte[osd_vcnt[2:0]];
+		osd_de[2:1] <= osd_de[1:0];
+	end
+end
+
+reg [23:0] rdout;
+assign dout = rdout;
+
+always @(posedge clk_video) begin
+	rdout <= ~osd_de[2] ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
+	                             {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
+	                             {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
+	de_out <= de_in;
+end
+
+endmodule

sys/pll.qip

@@ -0,0 +1,337 @@
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MTM=::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Mjk=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NTk=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::Mjk=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTk=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MjQuNjE1Mzg0IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::OC4xMjU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::NDguMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::OC4zMzM=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::OC4w::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MjcxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MjQuNTc2MjcxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTUsMTQsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsMzAsMjksMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwzMCwyOSwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMjAsNDAwMCwxNDUwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
+set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
+
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"

sys/pll.v

@@ -0,0 +1,255 @@
+// megafunction wizard: %Altera PLL v17.1%
+// GENERATION: XML
+// pll.v
+
+// Generated using ACDS version 17.1 590
+
+`timescale 1 ps / 1 ps
+module pll (
+		input  wire  refclk,   //  refclk.clk
+		input  wire  rst,      //   reset.reset
+		output wire  outclk_0, // outclk0.clk
+		output wire  outclk_1, // outclk1.clk
+		output wire  locked    //  locked.export
+	);
+
+	pll_0002 pll_inst (
+		.refclk   (refclk),   //  refclk.clk
+		.rst      (rst),      //   reset.reset
+		.outclk_0 (outclk_0), // outclk0.clk
+		.outclk_1 (outclk_1), // outclk1.clk
+		.locked   (locked)    //  locked.export
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2019 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="true" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="2" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="13" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="24.576" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="10" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="24.576" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="10" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="24.615384 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="180.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="24.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="8.125" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="48.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="8.333" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="8.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll.vo
+// RELATED_FILES: pll.v, pll_0002.v

sys/pll/pll_0002.qip

@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

sys/pll/pll_0002.v

@@ -0,0 +1,90 @@
+`timescale 1ns/10ps
+module  pll_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(2),
+		.output_clock_frequency0("24.576271 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("24.576271 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+

sys/pll_hdmi.qip

@@ -0,0 +1,484 @@
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
+set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
+
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

sys/pll_hdmi.v

@@ -0,0 +1,256 @@
+// megafunction wizard: %Altera PLL v17.1%
+// GENERATION: XML
+// pll_hdmi.v
+
+// Generated using ACDS version 17.1 590
+
+`timescale 1 ps / 1 ps
+module pll_hdmi (
+		input  wire        refclk,            //            refclk.clk
+		input  wire        rst,               //             reset.reset
+		output wire        outclk_0,          //           outclk0.clk
+		input  wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		output wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
+	);
+
+	pll_hdmi_0002 pll_hdmi_inst (
+		.refclk            (refclk),            //            refclk.clk
+		.rst               (rst),               //             reset.reset
+		.outclk_0          (outclk_0),          //           outclk0.clk
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.locked            ()                   //       (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2019 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.1" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="Unknown" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="false" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="148.5" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="65.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="27.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="true" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_hdmi.vo
+// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v

sys/pll_hdmi/pll_hdmi_0002.qip

@@ -0,0 +1,2 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

sys/pll_hdmi/pll_hdmi_0002.v

@@ -0,0 +1,241 @@
+`timescale 1ns/10ps
+module  pll_hdmi_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'locked'
+	output wire locked,
+
+	// interface 'reconfig_to_pll'
+	input wire [63:0] reconfig_to_pll,
+
+	// interface 'reconfig_from_pll'
+	output wire [63:0] reconfig_from_pll
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.pll_fractional_cout(32),
+		.pll_dsm_out_sel("1st_order"),
+		.operation_mode("direct"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("148.500000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("0 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("Cyclone V"),
+		.pll_subtype("Reconfigurable"),
+		.m_cnt_hi_div(4),
+		.m_cnt_lo_div(4),
+		.n_cnt_hi_div(256),
+		.n_cnt_lo_div(256),
+		.m_cnt_bypass_en("false"),
+		.n_cnt_bypass_en("true"),
+		.m_cnt_odd_div_duty_en("false"),
+		.n_cnt_odd_div_duty_en("false"),
+		.c_cnt_hi_div0(2),
+		.c_cnt_lo_div0(1),
+		.c_cnt_prst0(1),
+		.c_cnt_ph_mux_prst0(0),
+		.c_cnt_in_src0("ph_mux_clk"),
+		.c_cnt_bypass_en0("false"),
+		.c_cnt_odd_div_duty_en0("true"),
+		.c_cnt_hi_div1(1),
+		.c_cnt_lo_div1(1),
+		.c_cnt_prst1(1),
+		.c_cnt_ph_mux_prst1(0),
+		.c_cnt_in_src1("ph_mux_clk"),
+		.c_cnt_bypass_en1("true"),
+		.c_cnt_odd_div_duty_en1("false"),
+		.c_cnt_hi_div2(1),
+		.c_cnt_lo_div2(1),
+		.c_cnt_prst2(1),
+		.c_cnt_ph_mux_prst2(0),
+		.c_cnt_in_src2("ph_mux_clk"),
+		.c_cnt_bypass_en2("true"),
+		.c_cnt_odd_div_duty_en2("false"),
+		.c_cnt_hi_div3(1),
+		.c_cnt_lo_div3(1),
+		.c_cnt_prst3(1),
+		.c_cnt_ph_mux_prst3(0),
+		.c_cnt_in_src3("ph_mux_clk"),
+		.c_cnt_bypass_en3("true"),
+		.c_cnt_odd_div_duty_en3("false"),
+		.c_cnt_hi_div4(1),
+		.c_cnt_lo_div4(1),
+		.c_cnt_prst4(1),
+		.c_cnt_ph_mux_prst4(0),
+		.c_cnt_in_src4("ph_mux_clk"),
+		.c_cnt_bypass_en4("true"),
+		.c_cnt_odd_div_duty_en4("false"),
+		.c_cnt_hi_div5(1),
+		.c_cnt_lo_div5(1),
+		.c_cnt_prst5(1),
+		.c_cnt_ph_mux_prst5(0),
+		.c_cnt_in_src5("ph_mux_clk"),
+		.c_cnt_bypass_en5("true"),
+		.c_cnt_odd_div_duty_en5("false"),
+		.c_cnt_hi_div6(1),
+		.c_cnt_lo_div6(1),
+		.c_cnt_prst6(1),
+		.c_cnt_ph_mux_prst6(0),
+		.c_cnt_in_src6("ph_mux_clk"),
+		.c_cnt_bypass_en6("true"),
+		.c_cnt_odd_div_duty_en6("false"),
+		.c_cnt_hi_div7(1),
+		.c_cnt_lo_div7(1),
+		.c_cnt_prst7(1),
+		.c_cnt_ph_mux_prst7(0),
+		.c_cnt_in_src7("ph_mux_clk"),
+		.c_cnt_bypass_en7("true"),
+		.c_cnt_odd_div_duty_en7("false"),
+		.c_cnt_hi_div8(1),
+		.c_cnt_lo_div8(1),
+		.c_cnt_prst8(1),
+		.c_cnt_ph_mux_prst8(0),
+		.c_cnt_in_src8("ph_mux_clk"),
+		.c_cnt_bypass_en8("true"),
+		.c_cnt_odd_div_duty_en8("false"),
+		.c_cnt_hi_div9(1),
+		.c_cnt_lo_div9(1),
+		.c_cnt_prst9(1),
+		.c_cnt_ph_mux_prst9(0),
+		.c_cnt_in_src9("ph_mux_clk"),
+		.c_cnt_bypass_en9("true"),
+		.c_cnt_odd_div_duty_en9("false"),
+		.c_cnt_hi_div10(1),
+		.c_cnt_lo_div10(1),
+		.c_cnt_prst10(1),
+		.c_cnt_ph_mux_prst10(0),
+		.c_cnt_in_src10("ph_mux_clk"),
+		.c_cnt_bypass_en10("true"),
+		.c_cnt_odd_div_duty_en10("false"),
+		.c_cnt_hi_div11(1),
+		.c_cnt_lo_div11(1),
+		.c_cnt_prst11(1),
+		.c_cnt_ph_mux_prst11(0),
+		.c_cnt_in_src11("ph_mux_clk"),
+		.c_cnt_bypass_en11("true"),
+		.c_cnt_odd_div_duty_en11("false"),
+		.c_cnt_hi_div12(1),
+		.c_cnt_lo_div12(1),
+		.c_cnt_prst12(1),
+		.c_cnt_ph_mux_prst12(0),
+		.c_cnt_in_src12("ph_mux_clk"),
+		.c_cnt_bypass_en12("true"),
+		.c_cnt_odd_div_duty_en12("false"),
+		.c_cnt_hi_div13(1),
+		.c_cnt_lo_div13(1),
+		.c_cnt_prst13(1),
+		.c_cnt_ph_mux_prst13(0),
+		.c_cnt_in_src13("ph_mux_clk"),
+		.c_cnt_bypass_en13("true"),
+		.c_cnt_odd_div_duty_en13("false"),
+		.c_cnt_hi_div14(1),
+		.c_cnt_lo_div14(1),
+		.c_cnt_prst14(1),
+		.c_cnt_ph_mux_prst14(0),
+		.c_cnt_in_src14("ph_mux_clk"),
+		.c_cnt_bypass_en14("true"),
+		.c_cnt_odd_div_duty_en14("false"),
+		.c_cnt_hi_div15(1),
+		.c_cnt_lo_div15(1),
+		.c_cnt_prst15(1),
+		.c_cnt_ph_mux_prst15(0),
+		.c_cnt_in_src15("ph_mux_clk"),
+		.c_cnt_bypass_en15("true"),
+		.c_cnt_odd_div_duty_en15("false"),
+		.c_cnt_hi_div16(1),
+		.c_cnt_lo_div16(1),
+		.c_cnt_prst16(1),
+		.c_cnt_ph_mux_prst16(0),
+		.c_cnt_in_src16("ph_mux_clk"),
+		.c_cnt_bypass_en16("true"),
+		.c_cnt_odd_div_duty_en16("false"),
+		.c_cnt_hi_div17(1),
+		.c_cnt_lo_div17(1),
+		.c_cnt_prst17(1),
+		.c_cnt_ph_mux_prst17(0),
+		.c_cnt_in_src17("ph_mux_clk"),
+		.c_cnt_bypass_en17("true"),
+		.c_cnt_odd_div_duty_en17("false"),
+		.pll_vco_div(2),
+		.pll_cp_current(20),
+		.pll_bwctrl(4000),
+		.pll_output_clk_frequency("445.499999 MHz"),
+		.pll_fractional_division("3908420153"),
+		.mimic_fbclk_type("none"),
+		.pll_fbclk_mux_1("glb"),
+		.pll_fbclk_mux_2("m_cnt"),
+		.pll_m_cnt_in_src("ph_mux_clk"),
+		.pll_slf_rst("true")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_0}),
+		.locked	(locked),
+		.reconfig_to_pll	(reconfig_to_pll),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk),
+		.reconfig_from_pll	(reconfig_from_pll)
+	);
+endmodule
+

sys/pll_hdmi/pll_hdmi_0002_q13.qip

@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

sys/pll_hdmi_adj.vhd

@@ -0,0 +1,360 @@
+--------------------------------------------------------------------------------
+-- HDMI PLL Adjust
+--------------------------------------------------------------------------------
+
+-- Changes the HDMI PLL frequency according to the scaler suggestions.
+--------------------------------------------
+-- LLTUNE :
+--  0   : Input Syncline
+--  1   : 
+--  2   : Input Interlaced mode
+--  3   : Input Interlaced field
+--  4   : Output Syncline
+--  5   : 
+--  6   : Input clock
+--  7   : Output clock
+  
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY pll_hdmi_adj IS
+  PORT (
+    -- Scaler
+    llena         : IN  std_logic; -- 0=Disabled 1=Enabled
+    lltune        : IN  unsigned(15 DOWNTO 0); -- Outputs from scaler
+    
+    locked        : OUT std_logic;
+    
+    -- Signals from reconfig commands
+    i_waitrequest : OUT std_logic;
+    i_write       : IN  std_logic;
+    i_address     : IN  unsigned(5 DOWNTO 0);
+    i_writedata   : IN  unsigned(31 DOWNTO 0);
+
+    -- Outputs to PLL_HDMI_CFG
+    o_waitrequest : IN  std_logic;
+    o_write       : OUT std_logic;
+    o_address     : OUT unsigned(5 DOWNTO 0);
+    o_writedata   : OUT unsigned(31 DOWNTO 0);
+    
+    ------------------------------------
+    clk           : IN  std_logic;
+    reset_na      : IN  std_logic
+    );
+
+BEGIN
+
+  
+END ENTITY pll_hdmi_adj;
+
+--##############################################################################
+
+ARCHITECTURE rtl OF pll_hdmi_adj IS
+  SIGNAL pwrite : std_logic;
+  SIGNAL paddress : unsigned(5 DOWNTO 0);
+  SIGNAL pdata    : unsigned(31 DOWNTO 0);
+  TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
+  SIGNAL state : enum_state;
+  SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
+  SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
+  SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
+  SIGNAL mul : unsigned(15 DOWNTO 0);
+  SIGNAL sign,sign_pre : std_logic;
+  SIGNAL up,modo,phm,dir : std_logic;
+  SIGNAL cpt : natural RANGE 0 TO 3;
+  SIGNAL col : natural RANGE 0 TO 15;
+  
+  SIGNAL icpt,ocpt,ssh : natural RANGE 0 TO 2**24-1;
+  SIGNAL isync,isync2,itog,ipulse : std_logic;
+  SIGNAL osync,osync2,otog,opulse : std_logic;
+  SIGNAL sync,pulse,los,lop : std_logic;
+  SIGNAL osize,isize,offset,osizep : signed(23 DOWNTO 0);
+  SIGNAL logcpt : natural RANGE 0 TO 31;
+  SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
+  
+BEGIN
+  ----------------------------------------------------------------------------
+  -- Sample image sizes
+  Sampler:PROCESS(clk,reset_na) IS
+  BEGIN
+    IF reset_na='0' THEN
+--pragma synthesis_off
+      otog<='0';
+      itog<='0';
+      isync<='0';
+      isync2<='0';
+      osync<='0';
+      osync2<='0';
+--pragma synthesis_on
+      
+    ELSIF rising_edge(clk) THEN
+      -- Clock domain crossing
+      isync<=lltune(0); -- <ASYNC>
+      isync2<=isync;
+      osync<=lltune(4); -- <ASYNC>
+      osync2<=osync;
+      
+      itog<=itog XOR (isync AND NOT isync2);
+      otog<=otog XOR (osync AND NOT osync2);
+      
+      --ipulse<=isync AND NOT isync2 AND itog;
+      --opulse<=osync AND NOT osync2 AND otog;
+      
+      -- Measure output image size
+      IF osync='1' AND osync2='0' AND otog='1' THEN
+        ocpt<=0;
+        osizep<=to_signed(ocpt,24);
+      ELSE
+        ocpt<=ocpt+1;
+      END IF;
+      
+      -- Measure input image size
+      IF isync='1' AND isync2='0' AND itog='1' THEN
+        icpt<=0;
+        --isize<=to_signed(icpt,24);
+        osize<=osizep;
+        offset<=to_signed(ocpt,24);
+        udiff<=integer(to_integer(osizep)) - integer(icpt);
+        sync<='1';
+      ELSE
+        icpt<=icpt+1;
+        sync<='0';
+      END IF;
+
+      --------------------------------------------
+      pulse<='0';
+      IF sync='1' THEN
+        logcpt<=0;
+        ssh<=to_integer(osize);
+        los<='0';
+        lop<='0';
+        
+      ELSIF logcpt<24 THEN
+        -- Frequency difference
+        IF udiff>0 AND ssh<udiff AND los='0' THEN
+          tune_freq<='0' & to_unsigned(logcpt,5);
+          los<='1';
+        ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
+          tune_freq<='1' & to_unsigned(logcpt,5);
+          los<='1';
+        END IF;
+        -- Phase difference
+        IF offset<osize/2 AND ssh<offset AND lop='0' THEN
+          tune_phase<='0' & to_unsigned(logcpt,5);
+          lop<='1';
+        ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
+          tune_phase<='1' & to_unsigned(logcpt,5);
+          lop<='1';
+        END IF;
+        ssh<=ssh/2;
+        logcpt<=logcpt+1;
+        
+      ELSIF logcpt=24 THEN
+        pulse<='1';
+        ssh<=ssh/2;
+        logcpt<=logcpt+1;
+      END IF;
+
+    END IF;
+  END PROCESS Sampler;
+  
+    ----------------------------------------------------------------------------
+  -- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
+  -- 000100 : M counter
+  -- 000111 : M counter Fractional Value K
+  
+  Comb:PROCESS(i_write,i_address,
+               i_writedata,pwrite,paddress,pdata) IS
+  BEGIN
+    IF i_write='1' THEN
+      o_write      <=i_write;
+      o_address    <=i_address;
+      o_writedata  <=i_writedata;
+    ELSE
+      o_write    <=pwrite;
+      o_address  <=paddress;
+      o_writedata<=pdata;
+    END IF;
+  END PROCESS Comb;
+  
+  i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
+    
+  ----------------------------------------------------------------------------
+  Schmurtz:PROCESS(clk,reset_na) IS
+    VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
+    VARIABLE diff_v : unsigned(40 DOWNTO 0);
+    VARIABLE mulco : unsigned(15 DOWNTO 0);
+    VARIABLE up_v,sign_v : std_logic;
+  BEGIN
+    IF reset_na='0' THEN
+      modo<='0';
+      state<=sIDLE;
+    ELSIF rising_edge(clk) THEN
+      ------------------------------------------------------
+      -- Snoop accesses to PLL reconfiguration
+      IF i_address="000100" AND i_write='1' THEN
+        mfrac    (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
+                                 ('0' & i_writedata(7  DOWNTO 0));
+        mul<=i_writedata(15 DOWNTO 0);
+        modo<='1';
+      END IF;
+      
+      IF i_address="000111" AND i_write='1' THEN
+        mfrac    (31 DOWNTO 0)<=i_writedata;
+        mfrac_ref(31 DOWNTO 0)<=i_writedata;
+        mfrac_mem(31 DOWNTO 0)<=i_writedata;
+        modo<='1';
+      END IF;
+      
+      ------------------------------------------------------
+      -- Tuning
+      off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
+      ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
+      --IF off_v<8 THEN off_v:=8; END IF;
+      --IF ofp_v<7 THEN ofp_v:=7; END IF;
+      IF off_v<4 THEN off_v:=4; END IF;
+      IF ofp_v<4 THEN ofp_v:=4; END IF;
+      
+      IF off_v>=18 AND ofp_v>=18 THEN
+        locked<=llena;
+      ELSE
+        locked<='0';
+      END IF;
+      
+      up_v:='0';
+      IF pulse='1' THEN
+        cpt<=(cpt+1) MOD 4;
+        IF llena='0' THEN 
+          -- Recover original freq when disabling low lag mode
+          cpt<=0;
+          col<=0;
+          IF modo='1' THEN
+            mfrac<=mfrac_mem;
+            mfrac_ref<=mfrac_mem;
+            up<='1';
+            modo<='0';
+          END IF;
+          
+        ELSIF phm='0' AND cpt=0 THEN
+          -- Frequency adjust
+          sign_v:=tune_freq(5);
+          IF col<10 THEN col<=col+1; END IF;
+          IF off_v>=16 AND col>=10 THEN
+            phm<='1';
+            col<=0;
+          ELSE
+            off_v:=off_v+1;
+            IF off_v>17 THEN
+              off_v:=off_v + 3;
+            END IF;
+            up_v:='1';
+            up<='1';
+          END IF;
+          
+        ELSIF cpt=0 THEN
+          -- Phase adjust
+          sign_v:=NOT tune_phase(5);
+          col<=col+1;
+          IF col>=10 THEN
+            phm<='0';
+            up_v:='1';
+            off_v:=31;
+            col<=0;
+          ELSE
+            off_v:=ofp_v + 1;
+            IF ofp_v>7 THEN
+              off_v:=off_v + 1;
+            END IF;
+            IF ofp_v>14 THEN
+              off_v:=off_v + 2;
+            END IF;
+            IF ofp_v>17 THEN
+              off_v:=off_v + 3;
+            END IF;
+            up_v:='1';
+          END IF;
+          up<='1';
+        END IF;
+      END IF;
+      
+      diff_v:=shift_right(mfrac_ref,off_v);
+      IF sign_v='0' THEN
+        diff_v:=mfrac_ref + diff_v;
+      ELSE
+        diff_v:=mfrac_ref - diff_v;
+      END IF;
+      
+      IF up_v='1' THEN
+        mfrac<=diff_v;
+      END IF;
+      
+      IF up_v='1' AND phm='0' THEN
+        mfrac_ref<=diff_v;
+      END IF;
+      
+      ------------------------------------------------------
+      -- Update PLL registers
+      mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
+      
+      CASE state IS
+        WHEN sIDLE =>
+          pwrite<='0';
+          IF up='1' THEN
+            up<='0';
+            IF mulco/=mul THEN
+              state<=sW1;
+            ELSE
+              state<=sW3;
+            END IF;
+          END IF;
+          
+        WHEN sW1 => -- Change M multiplier
+          mul<=mulco;
+          pdata<=x"0000" & mulco;
+          paddress<="000100";
+          pwrite<='1';
+          state<=sW2;
+          
+        WHEN sW2 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            state<=sW3;
+            pwrite<='0';
+          END IF;
+          
+        WHEN sW3 => -- Change M fractional value
+          pdata<=mfrac(31 DOWNTO 0);
+          paddress<="000111";
+          pwrite<='1';
+          state<=sW4;
+          
+        WHEN sW4 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            state<=sW5;
+            pwrite<='0';
+          END IF;
+          
+        WHEN sW5 =>
+          pdata<=x"0000_0001";
+          paddress<="000010";
+          pwrite<='1';
+          state<=sW6;
+          
+        WHEN sW6 =>
+          IF pwrite='1' AND o_waitrequest='0' THEN
+            pwrite<='0';
+            state<=sIDLE;
+          END IF;
+      END CASE;
+
+    END IF;
+  END PROCESS Schmurtz;
+  
+  ----------------------------------------------------------------------------
+  
+END ARCHITECTURE rtl;
+

sys/pll_hdmi_cfg.qip

@@ -0,0 +1,45 @@
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.cmp"]
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_top.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_core.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_std_synchronizer.v"]
+
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"

sys/pll_hdmi_cfg.v

@@ -0,0 +1,86 @@
+// megafunction wizard: %Altera PLL Reconfig v17.1%
+// GENERATION: XML
+// pll_hdmi_cfg.v
+
+// Generated using ACDS version 17.1 590
+
+`timescale 1 ps / 1 ps
+module pll_hdmi_cfg #(
+		parameter ENABLE_BYTEENABLE   = 0,
+		parameter BYTEENABLE_WIDTH    = 4,
+		parameter RECONFIG_ADDR_WIDTH = 6,
+		parameter RECONFIG_DATA_WIDTH = 32,
+		parameter reconf_width        = 64,
+		parameter WAIT_FOR_LOCK       = 1
+	) (
+		input  wire        mgmt_clk,          //          mgmt_clk.clk
+		input  wire        mgmt_reset,        //        mgmt_reset.reset
+		output wire        mgmt_waitrequest,  // mgmt_avalon_slave.waitrequest
+		input  wire        mgmt_read,         //                  .read
+		input  wire        mgmt_write,        //                  .write
+		output wire [31:0] mgmt_readdata,     //                  .readdata
+		input  wire [5:0]  mgmt_address,      //                  .address
+		input  wire [31:0] mgmt_writedata,    //                  .writedata
+		output wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		input  wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
+	);
+
+	altera_pll_reconfig_top #(
+		.device_family       ("Cyclone V"),
+		.ENABLE_MIF          (0),
+		.MIF_FILE_NAME       ("sys/pll_hdmi_cfg.mif"),
+		.ENABLE_BYTEENABLE   (ENABLE_BYTEENABLE),
+		.BYTEENABLE_WIDTH    (BYTEENABLE_WIDTH),
+		.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
+		.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
+		.reconf_width        (reconf_width),
+		.WAIT_FOR_LOCK       (WAIT_FOR_LOCK)
+	) pll_hdmi_cfg_inst (
+		.mgmt_clk          (mgmt_clk),          //          mgmt_clk.clk
+		.mgmt_reset        (mgmt_reset),        //        mgmt_reset.reset
+		.mgmt_waitrequest  (mgmt_waitrequest),  // mgmt_avalon_slave.waitrequest
+		.mgmt_read         (mgmt_read),         //                  .read
+		.mgmt_write        (mgmt_write),        //                  .write
+		.mgmt_readdata     (mgmt_readdata),     //                  .readdata
+		.mgmt_address      (mgmt_address),      //                  .address
+		.mgmt_writedata    (mgmt_writedata),    //                  .writedata
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.mgmt_byteenable   (4'b0000)            //       (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2019 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.1" >
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="ENABLE_MIF" value="false" />
+// Retrieval info: 	<generic name="MIF_FILE_NAME" value="sys/pll_hdmi_cfg.mif" />
+// Retrieval info: 	<generic name="ENABLE_BYTEENABLE" value="false" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_hdmi_cfg.vo
+// RELATED_FILES: pll_hdmi_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v

sys/pll_hdmi_cfg/altera_pll_reconfig_top.v

@@ -0,0 +1,428 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+module altera_pll_reconfig_top
+#(
+    parameter   reconf_width            = 64,
+    parameter   device_family           = "Stratix V",
+    parameter   RECONFIG_ADDR_WIDTH     = 6,
+    parameter   RECONFIG_DATA_WIDTH     = 32,
+    
+	parameter   ROM_ADDR_WIDTH          = 9,
+    parameter   ROM_DATA_WIDTH          = 32,
+	parameter	ROM_NUM_WORDS           = 512,
+
+    parameter   ENABLE_MIF              = 0,    
+    parameter   MIF_FILE_NAME           = "",
+	
+	parameter 	ENABLE_BYTEENABLE		= 0,
+	parameter	BYTEENABLE_WIDTH		= 4,
+    parameter   WAIT_FOR_LOCK           = 1
+) ( 
+
+    //input
+    input   wire    mgmt_clk,
+    input   wire    mgmt_reset,
+
+
+    //conduits
+    output  wire [reconf_width-1:0] reconfig_to_pll,
+    input  wire [reconf_width-1:0] reconfig_from_pll,
+
+    // user data (avalon-MM slave interface)
+    output  wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
+    output  wire        mgmt_waitrequest,
+    input   wire [RECONFIG_ADDR_WIDTH-1:0]  mgmt_address,
+    input   wire        mgmt_read,
+    input   wire        mgmt_write,
+    input   wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
+	
+	//conditional input 
+	input 	wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
+);
+
+localparam  NM28_START_REG 		= 6'b000010;
+localparam  NM20_START_REG 		= 9'b000000000;
+localparam 	NM20_MIFSTART_ADDR	= 9'b000010000;
+
+localparam MIF_STATE_DONE = 2'b00;
+localparam MIF_STATE_START = 2'b01;
+localparam MIF_STATE_BUSY = 2'b10;
+
+wire mgmt_byteenable_write;
+assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? 
+										((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : 
+										mgmt_write;
+										
+generate
+if (device_family == "Arria 10")
+begin:nm20_reconfig
+	if(ENABLE_MIF == 1)
+	begin:mif_reconfig_20nm // Generate Reconfig with MIF
+	
+		// MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr; 
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire							 mif_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+		//wire 							mif_user_start; // start signal provided by user to start mif
+        //reg user_start;
+
+		reg [1:0] mif_curstate;
+		reg [1:0] mif_nextstate;
+
+        wire mif_start; //start signal to mif reader
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+		//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
+		assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
+		
+		//mif base addr is initially specified by the user
+		assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
+		
+		//MIF statemachine
+		always @(posedge mgmt_clk)
+		begin
+			if(mgmt_reset)
+				mif_curstate <= MIF_STATE_DONE;
+			else
+				mif_curstate <= mif_nextstate;
+		end
+		
+		always @(*)
+		begin
+			case (mif_curstate)
+				MIF_STATE_DONE:
+				begin
+					if(mif_start)
+						mif_nextstate <= MIF_STATE_START;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+				MIF_STATE_START:
+				begin
+					mif_nextstate <= MIF_STATE_BUSY;
+				end				
+				MIF_STATE_BUSY:
+				begin
+					if(mif_busy)
+						mif_nextstate <= MIF_STATE_BUSY;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+			endcase
+		end
+		
+		//Mif muxes
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                //user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                //user_start              <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
+            end
+        end
+	
+        twentynm_pll_reconfig_mif_reader  
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) twentynm_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_waitrequest(reconfig_mgmt_waitrequest),
+			//.reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(mif_start),
+            //outputs
+            .mif_busy(mif_busy)
+        );
+		
+        // ------ END MIF-RELATED MANAGEMENT ------	
+		
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(reconfig_mgmt_read),
+			.mgmt_write(reconfig_mgmt_write),
+			.mgmt_address(reconfig_mgmt_addr),
+			.mgmt_writedata(reconfig_mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(reconfig_mgmt_readdata),
+			.mgmt_waitrequest(reconfig_mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+		
+	end // End generate reconfig with MIF
+	else 
+	begin:reconfig_core_20nm
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(mgmt_read),
+			.mgmt_write(mgmt_byteenable_write),
+			.mgmt_address(mgmt_address),
+			.mgmt_writedata(mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(mgmt_readdata),
+			.mgmt_waitrequest(mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+	end
+end // 20nm reconfig
+else
+begin:NM28_reconfig
+    if (ENABLE_MIF == 1)
+    begin:mif_reconfig // Generate Reconfig with MIF
+
+        // MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr;
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire										mif2reconfig_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+        reg user_start;
+
+        wire reconfig2mif_start_out;
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+        always @(posedge mgmt_clk)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                user_start              <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
+            end
+        end
+
+        altera_pll_reconfig_mif_reader 
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) altera_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_busy(reconfig_mgmt_waitrequest),
+            .reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(reconfig2mif_start_out),
+            //outputs
+            .mif_busy(mif2reconfig_busy)
+        );
+
+        // ------ END MIF-RELATED MANAGEMENT ------
+
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(reconfig_mgmt_readdata),
+            .mgmt_waitrequest(reconfig_mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(reconfig_mgmt_addr),
+            .mgmt_read(reconfig_mgmt_read),
+            .mgmt_write(reconfig_mgmt_write),
+            .mgmt_writedata(reconfig_mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+    end // End generate reconfig with MIF
+    else
+    begin:reconfig_core // Generate Reconfig core only
+
+        wire reconfig2mif_start_out;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(mgmt_readdata),
+            .mgmt_waitrequest(mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(mgmt_address),
+            .mgmt_read(mgmt_read),
+            .mgmt_write(mgmt_byteenable_write),
+            .mgmt_writedata(mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+        
+    end // End generate reconfig core only
+end // End 28nm Reconfig
+endgenerate
+
+endmodule
+

sys/pll_hdmi_cfg/altera_std_synchronizer.v

@@ -0,0 +1,159 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/17.1std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2017/07/30 $
+// $Author: swbranch $
+//-----------------------------------------------------------------------------
+//
+// File: altera_std_synchronizer.v
+//
+// Abstract: Single bit clock domain crossing synchronizer. 
+//           Composed of two or more flip flops connected in series.
+//           Random metastable condition is simulated when the 
+//           __ALTERA_STD__METASTABLE_SIM macro is defined.
+//           Use +define+__ALTERA_STD__METASTABLE_SIM argument 
+//           on the Verilog simulator compiler command line to 
+//           enable this mode. In addition, dfine the macro
+//           __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output 
+//           with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+//-----------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_std_synchronizer (
+				clk, 
+				reset_n, 
+				din, 
+				dout
+				);
+
+   parameter depth = 3; // This value must be >= 2 !
+     
+   input   clk;
+   input   reset_n;    
+   input   din;
+   output  dout;
+
+   // QuartusII synthesis directives:
+   //     1. Preserve all registers ie. do not touch them.
+   //     2. Do not merge other flip-flops with synchronizer flip-flops.
+   // QuartusII TimeQuest directives:
+   //     1. Identify all flip-flops in this module as members of the synchronizer 
+   //        to enable automatic metastability MTBF analysis.
+   //     2. Cut all timing paths terminating on data input pin of the first flop din_s1.
+
+   (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]\" "} *) reg din_s1;
+
+   (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;    
+   
+   //synthesis translate_off
+   initial begin
+      if (depth <2) begin
+	 $display("%m: Error: synchronizer length: %0d less than 2.", depth);
+      end
+   end
+
+   // the first synchronizer register is either a simple D flop for synthesis
+   // and non-metastable simulation or a D flop with a method to inject random
+   // metastable events resulting in random delay of [0,1] cycles
+   
+`ifdef __ALTERA_STD__METASTABLE_SIM
+
+   reg[31:0]  RANDOM_SEED = 123456;      
+   wire  next_din_s1;
+   wire  dout;
+   reg   din_last;
+   reg 	 random;
+   event metastable_event; // hook for debug monitoring
+
+   initial begin
+      $display("%m: Info: Metastable event injection simulation mode enabled");
+   end
+   
+   always @(posedge clk) begin
+      if (reset_n == 0)
+	random <= $random(RANDOM_SEED);
+      else
+	random <= $random;
+   end
+
+   assign next_din_s1 = (din_last ^ din) ? random : din;   
+
+   always @(posedge clk or negedge reset_n) begin
+       if (reset_n == 0) 
+	 din_last <= 1'b0;
+       else
+	 din_last <= din;
+   end
+
+   always @(posedge clk or negedge reset_n) begin
+       if (reset_n == 0) 
+	 din_s1 <= 1'b0;
+       else
+	 din_s1 <= next_din_s1;
+   end
+   
+`else 
+
+   //synthesis translate_on   
+   always @(posedge clk or negedge reset_n) begin
+       if (reset_n == 0) 
+	 din_s1 <= 1'b0;
+       else
+	 din_s1 <= din;
+   end
+   //synthesis translate_off      
+
+`endif
+
+`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
+   always @(*) begin
+      if (reset_n && (din_last != din) && (random != din)) begin
+	 $display("%m: Verbose Info: metastable event @ time %t", $time);
+	 ->metastable_event;
+      end
+   end      
+`endif
+
+   //synthesis translate_on
+
+   // the remaining synchronizer registers form a simple shift register
+   // of length depth-1
+   generate
+      if (depth < 3) begin
+	 always @(posedge clk or negedge reset_n) begin
+	    if (reset_n == 0) 
+	      dreg <= {depth-1{1'b0}};	    
+	    else
+	      dreg <= din_s1;
+	 end	 
+      end else begin
+	 always @(posedge clk or negedge reset_n) begin
+	    if (reset_n == 0) 
+	      dreg <= {depth-1{1'b0}};
+	    else
+	      dreg <= {dreg[depth-3:0], din_s1};
+	 end
+      end
+   endgenerate
+
+   assign dout = dreg[depth-2];
+   
+endmodule 
+
+
+			

sys/pll_hdmi_q13.qip

@@ -0,0 +1,13 @@
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
+set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
+set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
+
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

sys/scandoubler.v

@@ -0,0 +1,195 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017-2019 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	output            ce_pix_out,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             hb_in,
+	input             vb_in,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output            hb_out,
+	output            vb_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+assign vs_out = vso[3];
+assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
+
+//Compensate picture shift after HQ2x
+assign vb_out = vbo[3];
+assign hb_out = hbo[6];
+
+reg  [7:0] pix_len = 0;
+reg  [7:0] pix_cnt = 0;
+wire [7:0] pl = pix_len + 1'b1;
+wire [7:0] pc = pix_cnt + 1'b1;
+
+reg ce_x4, ce_x2, ce_x1;
+always @(negedge clk_sys) begin
+	reg old_ce, valid, hs;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz, pixsz2, pixsz4 = 0;
+
+	if(~&pix_len) pix_len <= pl;
+	if(~&pix_cnt) pix_cnt <= pc;
+
+	ce_x4 <= 0;
+	ce_x2 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
+	if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
+	if( pc == pixsz2) ce_x2 <= 1;
+
+	old_ce <= ce_pix;
+	if(~old_ce & ce_pix) begin
+		if(valid & ~hb_in & ~vb_in) begin
+			pixsz  <= pl;
+			pixsz2 <= {1'b0,  pl[7:1]};
+			pixsz4 <= {2'b00, pl[7:2]};
+		end
+		pix_len <= 0;
+		valid <= 1;
+	end
+
+	if(hb_in | vb_in) valid <= 0;
+
+	hs <= hs_out;
+	if((~hs & hs_out) || (pc >= pixsz)) begin
+		ce_x2 <= 1;
+		ce_x4 <= 1;
+		ce_x1 <= 1;
+		pix_cnt <= 0;
+	end
+end
+
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4),
+	.inputpixel({b_d,g_d,r_d}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vb_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.hblank(hbo[0]&hbo[8]),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [DWIDTH:0] r_d;
+reg [DWIDTH:0] g_d;
+reg [DWIDTH:0] b_d;
+
+reg [1:0] sd_line;
+reg [3:0] vbo;
+reg [3:0] vso;
+reg [8:0] hbo;
+
+reg req_line_reset;
+always @(posedge clk_sys) begin
+
+	reg [31:0] hcnt;
+	reg [30:0] sd_hcnt;
+	reg [30:0] hs_start, hs_end;
+	reg [30:0] hde_start, hde_end;
+
+	reg hs, hb;
+
+	if(ce_x4) begin
+		hbo[8:1] <= hbo[7:0];
+	end
+
+	// output counter synchronous to input and at twice the rate
+	sd_hcnt <= sd_hcnt + 1'd1;
+	if(sd_hcnt == hde_start) begin
+		sd_hcnt <= 0;
+		vbo[3:1] <= vbo[2:0];
+	end
+
+	if(sd_hcnt == hs_end) begin
+		sd_line <= sd_line + 1'd1;
+		if(&vbo[3:2]) sd_line <= 1;
+		vso[3:1] <= vso[2:0];
+	end
+
+	if(sd_hcnt == hde_start)hbo[0] <= 0;
+	if(sd_hcnt == hde_end)  hbo[0] <= 1;
+
+	// replicate horizontal sync at twice the speed
+	if(sd_hcnt == hs_end)   hs_out <= 0;
+	if(sd_hcnt == hs_start) hs_out <= 1;
+
+	hs <= hs_in;
+	hb <= hb_in;
+
+	if(ce_x1) begin
+		req_line_reset <= hb_in;
+		r_d <= r_in;
+		g_d <= g_in;
+		b_d <= b_in;
+	end
+
+	hcnt <= hcnt + 1'd1;
+	if(hb && !hb_in) begin
+		hde_start <= hcnt[31:1];
+		hbo[0] <= 0;
+		hcnt <= 0;
+		sd_hcnt <= 0;
+		vbo <= {vbo[2:0],vb_in};
+	end
+
+	if(!hb && hb_in) hde_end <= hcnt[31:1];
+
+	// falling edge of hsync indicates start of line
+	if(hs && !hs_in) begin
+		hs_end <= hcnt[31:1];
+		vso[0] <= vs_in;
+	end
+
+	// save position of rising edge
+	if(!hs && hs_in) hs_start <= hcnt[31:1];
+end
+
+endmodule

sys/scanlines.v

@@ -0,0 +1,52 @@
+module scanlines #(parameter v2=0)
+(
+	input         clk,
+
+	input       [1:0] scanlines,
+	input      [23:0] din,
+	output reg [23:0] dout,
+	input             hs,vs
+);
+
+reg [1:0] scanline;
+always @(posedge clk) begin
+	reg old_hs, old_vs;
+
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) begin
+		if(v2) begin
+			scanline <= scanline + 1'd1;
+			if (scanline == scanlines) scanline <= 0;
+		end
+		else scanline <= scanline ^ scanlines;
+	end
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [7:0] r,g,b;
+assign {r,g,b} = din;
+
+always @(*) begin
+	case(scanline)
+		1: // reduce 25% = 1/2 + 1/4
+			dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
+					  {1'b0, g[7:1]} + {2'b00, g[7:2]},
+					  {1'b0, b[7:1]} + {2'b00, b[7:2]}};
+
+		2: // reduce 50% = 1/2
+			dout = {{1'b0, r[7:1]},
+					  {1'b0, g[7:1]},
+					  {1'b0, b[7:1]}};
+
+		3: // reduce 75% = 1/4
+			dout = {{2'b00, r[7:2]},
+					  {2'b00, g[7:2]},
+					  {2'b00, b[7:2]}};
+
+		default: dout = {r,g,b};
+	endcase
+end
+
+endmodule

sys/sd_card.v

@@ -0,0 +1,538 @@
+// 
+// sd_card.v
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2018 Sorgelig
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the Lesser GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+// http://elm-chan.org/docs/mmc/mmc_e.html
+//
+/////////////////////////////////////////////////////////////////////////
+
+//
+// Made module syncrhronous. Total code refactoring. (Sorgelig)
+// clk_spi must be at least 4 x sck for proper work.
+
+module sd_card
+(
+	input         clk_sys,
+	input         reset,
+
+	input         sdhc,
+	
+	output [31:0] sd_lba,
+	output reg    sd_rd,
+	output reg    sd_wr,
+	input         sd_ack,
+	input         sd_ack_conf,
+
+	input   [8:0] sd_buff_addr,
+	input   [7:0] sd_buff_dout,
+	output  [7:0] sd_buff_din,
+	input         sd_buff_wr,
+
+	// SPI interface
+	input         clk_spi,
+
+	input         ss,
+	input         sck,
+	input         mosi,
+	output reg    miso
+);
+
+assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
+
+wire[31:0] OCR = { 1'b1, sdhc, 30'd0 };  // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
+wire [7:0] READ_DATA_TOKEN     = 8'hfe;
+wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
+
+// number of bytes to wait after a command before sending the reply
+localparam NCR=3;
+
+localparam RD_STATE_IDLE       = 0;
+localparam RD_STATE_WAIT_IO    = 1;
+localparam RD_STATE_SEND_TOKEN = 2;
+localparam RD_STATE_SEND_DATA  = 3;
+localparam RD_STATE_WAIT_M     = 4;
+
+localparam WR_STATE_IDLE       = 0;
+localparam WR_STATE_EXP_DTOKEN = 1;
+localparam WR_STATE_RECV_DATA  = 2;
+localparam WR_STATE_RECV_CRC0  = 3;
+localparam WR_STATE_RECV_CRC1  = 4;
+localparam WR_STATE_SEND_DRESP = 5;
+localparam WR_STATE_BUSY       = 6;
+
+sdbuf buffer
+(
+	.clock_a(clk_sys),
+	.address_a(sd_buff_addr),
+	.data_a(sd_buff_dout),
+	.wren_a(sd_ack & sd_buff_wr),
+	.q_a(sd_buff_din),
+
+	.clock_b(clk_spi),
+	.address_b(buffer_ptr),
+	.data_b(buffer_din),
+	.wren_b(buffer_wr),
+	.q_b(buffer_dout)
+);
+
+sdbuf conf
+(
+	.clock_a(clk_sys),
+	.address_a(sd_buff_addr),
+	.data_a(sd_buff_dout),
+	.wren_a(sd_ack_conf & sd_buff_wr),
+
+	.clock_b(clk_spi),
+	.address_b(buffer_ptr),
+	.q_b(config_dout)
+);
+
+reg [31:0] lba, new_lba;
+reg  [8:0] buffer_ptr;
+reg  [7:0] buffer_din;
+wire [7:0] buffer_dout;
+wire [7:0] config_dout;
+reg        buffer_wr;
+
+always @(posedge clk_spi) begin
+	reg [2:0] read_state;
+	reg [2:0] write_state;
+	reg [6:0] sbuf;
+	reg       cmd55;
+	reg [7:0] cmd;
+	reg [2:0] bit_cnt;
+	reg [3:0] byte_cnt;
+	reg [7:0] reply;
+	reg [7:0] reply0, reply1, reply2, reply3;
+	reg [3:0] reply_len;
+	reg       tx_finish;
+	reg       rx_finish;
+	reg       old_sck;
+	reg       synced;
+	reg [5:0] ack;
+	reg       io_ack;
+	reg [4:0] idle_cnt = 0;
+	reg [2:0] wait_m_cnt;
+
+	if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
+	buffer_wr <= 0;
+
+	ack <= {ack[4:0], sd_ack};
+	if(ack[5:4] == 2'b10) io_ack <= 1;
+	if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0;
+
+	old_sck <= sck;
+	
+	if(~ss)                              idle_cnt <= 31;
+	else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1;
+
+	if(reset || !idle_cnt) begin
+		bit_cnt     <= 0;
+		byte_cnt    <= 15;
+		synced      <= 0;
+		miso        <= 1;
+		sbuf        <= 7'b1111111;
+		tx_finish   <= 0;
+		rx_finish   <= 0;
+		read_state  <= RD_STATE_IDLE;
+		write_state <= WR_STATE_IDLE;
+	end
+
+	if(old_sck & ~sck & ~ss) begin
+		tx_finish <= 0;
+		miso <= 1;				// default: send 1's (busy/wait)
+
+		if(byte_cnt == 5+NCR) begin
+			miso <= reply[~bit_cnt];
+
+			if(bit_cnt == 7) begin
+				// these three commands all have a reply_len of 0 and will thus
+				// not send more than a single reply byte
+
+				// CMD9: SEND_CSD
+				// CMD10: SEND_CID
+				if((cmd == 'h49) | (cmd ==  'h4a))
+					read_state <= RD_STATE_SEND_TOKEN;      // jump directly to data transmission
+						
+				// CMD17/CMD18
+				if((cmd == 'h51) | (cmd == 'h52)) begin
+					io_ack <= 0;
+					read_state <= RD_STATE_WAIT_IO;         // start waiting for data from io controller
+					lba <= new_lba;
+					sd_rd <= 1;                      // trigger request to io controller
+				end
+			end
+		end
+		else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt];
+		else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt];
+		else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt];
+		else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt];
+		else begin
+			if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1;
+		end
+
+		// ---------- read state machine processing -------------
+
+		case(read_state)
+			RD_STATE_IDLE: ; // do nothing
+
+
+			// waiting for io controller to return data
+			RD_STATE_WAIT_IO: begin
+				if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN;
+			end
+
+			// send data token
+			RD_STATE_SEND_TOKEN: begin
+				miso <= READ_DATA_TOKEN[~bit_cnt];
+	
+				if(bit_cnt == 7) begin
+					read_state <= RD_STATE_SEND_DATA;   // next: send data
+					buffer_ptr <= 0;
+					if(cmd == 'h49) buffer_ptr <= 16;
+				end
+			end
+
+			// send data
+			RD_STATE_SEND_DATA: begin
+
+				miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt];
+
+				if(bit_cnt == 7) begin
+
+					// sent 512 sector data bytes?
+					if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE;
+					else if((cmd == 'h52) & &buffer_ptr) begin
+						read_state <= RD_STATE_WAIT_M;
+						wait_m_cnt <= 0;
+					end
+
+					// sent 16 cid/csd data bytes?
+					else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE;
+
+					// not done yet -> trigger read of next data byte
+					else buffer_ptr <= buffer_ptr + 1'd1;
+				end
+			end
+
+			RD_STATE_WAIT_M: begin
+				if(bit_cnt == 7) begin
+					wait_m_cnt <= wait_m_cnt + 1'd1;
+					if(&wait_m_cnt) begin
+						lba <= lba + 1;
+						io_ack <= 0;
+						sd_rd <= 1;
+						read_state <= RD_STATE_WAIT_IO;
+					end
+				end
+			end
+		endcase
+
+		// ------------------ write support ----------------------
+		// send write data response
+		if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt];
+
+		// busy after write until the io controller sends ack
+		if(write_state == WR_STATE_BUSY) miso <= 0;
+   end
+
+	if(~old_sck & sck & ~ss) begin
+
+	   if(synced) bit_cnt <= bit_cnt + 1'd1;
+
+		// assemble byte
+		if(bit_cnt != 7) begin
+			sbuf[6:0] <= { sbuf[5:0], mosi };
+
+			// resync while waiting for token
+			if(write_state==WR_STATE_EXP_DTOKEN) begin
+				if(cmd == 'h58) begin
+					if({sbuf,mosi} == 8'hfe) begin
+						write_state <= WR_STATE_RECV_DATA;
+						buffer_ptr <= 0;
+						bit_cnt <= 0;
+					end
+				end
+				else begin
+					if({sbuf,mosi} == 8'hfc) begin
+						write_state <= WR_STATE_RECV_DATA;
+						buffer_ptr <= 0;
+						bit_cnt <= 0;
+					end
+					if({sbuf,mosi} == 8'hfd) begin
+						write_state <= WR_STATE_IDLE;
+						rx_finish <= 1;
+						bit_cnt <= 0;
+					end
+				end
+			end
+		end
+		else begin
+			// finished reading one byte
+			// byte counter runs against 15 byte boundary
+			if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1;
+
+			// byte_cnt > 6 -> complete command received
+			// first byte of valid command is 01xxxxxx
+			// don't accept new commands once a write or read command has been accepted
+ 			if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin
+				byte_cnt <= 0;
+				cmd <= { sbuf, mosi};
+
+			   // set cmd55 flag if previous command was 55
+			   cmd55 <= (cmd == 'h77);
+			end
+
+ 			if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin
+				byte_cnt <= 0;
+				rx_finish <= 0;
+				cmd <= {sbuf, mosi};
+				read_state <= RD_STATE_IDLE;
+			end
+
+			// parse additional command bytes
+			if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi};
+			if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi};
+			if(byte_cnt == 2) new_lba[15:8]  <= { sbuf, mosi};
+			if(byte_cnt == 3) new_lba[7:0]   <= { sbuf, mosi};
+
+			// last byte (crc) received, evaluate
+			if(byte_cnt == 4) begin
+
+				// default:
+				reply <= 4;      // illegal command
+				reply_len <= 0;  // no extra reply bytes
+				rx_finish <= 1;
+
+				case(cmd)
+					// CMD0: GO_IDLE_STATE
+					'h40: reply <= 1;    // ok, busy
+
+					// CMD1: SEND_OP_COND
+					'h41: reply <= 0;    // ok, not busy
+
+					// CMD8: SEND_IF_COND (V2 only)
+					'h48: begin
+							reply  <= 1;   // ok, busy
+
+							reply0 <= 'h00;
+							reply1 <= 'h00;
+							reply2 <= 'h01;
+							reply3 <= 'hAA;
+							reply_len <= 4;
+						end
+
+					// CMD9: SEND_CSD
+					'h49: reply <= 0;    // ok
+
+					// CMD10: SEND_CID
+					'h4a: reply <= 0;    // ok
+
+					// CMD12: STOP_TRANSMISSION 
+					'h4c: reply <= 0;    // ok
+
+					// CMD16: SET_BLOCKLEN
+					'h50: begin
+							// we only support a block size of 512
+							if(new_lba == 512) reply <= 0;  // ok
+								else reply <= 'h40;         // parmeter error
+						end
+
+					// CMD17: READ_SINGLE_BLOCK
+					'h51: reply <= 0;    // ok
+
+					// CMD18: READ_MULTIPLE
+					'h52: reply <= 0;    // ok
+
+					// CMD24: WRITE_BLOCK
+					'h58,
+					// CMD25: WRITE_MULTIPLE
+					'h59: begin
+							reply <= 0;    // ok
+							write_state <= WR_STATE_EXP_DTOKEN;  // expect data token
+							rx_finish <=0;
+							lba <= new_lba;
+						end
+
+					// ACMD41: APP_SEND_OP_COND
+					'h69: if(cmd55) reply <= 0;    // ok, not busy
+
+					// CMD55: APP_COND
+					'h77: reply <= 1;    // ok, busy
+
+					// CMD58: READ_OCR
+					'h7a: begin
+							reply <= 0;    // ok
+
+							reply0 <= OCR[31:24];   // bit 30 = 1 -> high capacity card
+							reply1 <= OCR[23:16];
+							reply2 <= OCR[15:8];
+							reply3 <= OCR[7:0];
+							reply_len <= 4;
+						end
+
+					// CMD59: CRC_ON_OFF
+					'h7b: reply <= 0;    // ok
+				endcase
+			end
+
+				// ---------- handle write -----------
+			case(write_state)
+				// do nothing in idle state
+				WR_STATE_IDLE: ;
+
+				// waiting for data token
+				WR_STATE_EXP_DTOKEN: begin
+					buffer_ptr <= 0;
+					if(cmd == 'h58) begin
+						if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA;
+					end
+					else begin
+						if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA;
+						if({sbuf,mosi} == 8'hfd) begin
+							write_state <= WR_STATE_IDLE;
+							rx_finish <= 1;
+						end
+					end
+				end
+
+				// transfer 512 bytes
+				WR_STATE_RECV_DATA: begin
+					// push one byte into local buffer
+					buffer_wr  <= 1;
+					buffer_din <= {sbuf, mosi};
+
+					// all bytes written?
+					if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
+				end
+
+				// transfer 1st crc byte
+				WR_STATE_RECV_CRC0:
+					write_state <= WR_STATE_RECV_CRC1;
+
+				// transfer 2nd crc byte
+				WR_STATE_RECV_CRC1:
+					write_state <= WR_STATE_SEND_DRESP;
+
+				// send data response
+				WR_STATE_SEND_DRESP: begin
+					write_state <= WR_STATE_BUSY;
+					io_ack <= 0;
+					sd_wr <= 1;
+				end
+
+				// wait for io controller to accept data
+				WR_STATE_BUSY:
+					if(io_ack) begin
+						if(cmd == 'h59) begin
+							write_state <= WR_STATE_EXP_DTOKEN;
+							lba <= lba + 1;
+						end
+						else begin
+							write_state <= WR_STATE_IDLE;
+							rx_finish <= 1;
+						end
+					end
+			endcase
+		end
+		
+		// wait for first 0 bit until start counting bits
+		if(!synced && !mosi) begin
+			synced   <= 1;
+			bit_cnt  <= 1; // byte assembly prepare for next time loop
+			sbuf     <= 7'b1111110; // byte assembly prepare for next time loop
+			rx_finish<= 0;
+		end else if (synced && tx_finish && rx_finish ) begin
+			synced   <= 0;
+			bit_cnt  <= 0;
+			rx_finish<= 0;
+		end
+	end
+end
+
+endmodule
+
+module sdbuf
+(
+	input	       clock_a,
+	input	       clock_b,
+	input	 [8:0] address_a,
+	input	 [8:0] address_b,
+	input	 [7:0] data_a,
+	input	 [7:0] data_b,
+	input	       wren_a,
+	input	       wren_b,
+	output [7:0] q_a,
+	output [7:0] q_b
+);
+
+altsyncram	altsyncram_component
+(
+	.address_a (address_a),
+	.address_b (address_b),
+	.clock0 (clock_a),
+	.clock1 (clock_b),
+	.data_a (data_a),
+	.data_b (data_b),
+	.wren_a (wren_a),
+	.wren_b (wren_b),
+	.q_a (q_a),
+	.q_b (q_b),
+	.aclr0 (1'b0),
+	.aclr1 (1'b0),
+	.addressstall_a (1'b0),
+	.addressstall_b (1'b0),
+	.byteena_a (1'b1),
+	.byteena_b (1'b1),
+	.clocken0 (1'b1),
+	.clocken1 (1'b1),
+	.clocken2 (1'b1),
+	.clocken3 (1'b1),
+	.eccstatus (),
+	.rden_a (1'b1),
+	.rden_b (1'b1)
+);
+defparam
+	altsyncram_component.address_reg_b = "CLOCK1",
+	altsyncram_component.clock_enable_input_a = "BYPASS",
+	altsyncram_component.clock_enable_input_b = "BYPASS",
+	altsyncram_component.clock_enable_output_a = "BYPASS",
+	altsyncram_component.clock_enable_output_b = "BYPASS",
+	altsyncram_component.indata_reg_b = "CLOCK1",
+	altsyncram_component.intended_device_family = "Cyclone V",
+	altsyncram_component.lpm_type = "altsyncram",
+	altsyncram_component.numwords_a = 512,
+	altsyncram_component.numwords_b = 512,
+	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+	altsyncram_component.outdata_aclr_a = "NONE",
+	altsyncram_component.outdata_aclr_b = "NONE",
+	altsyncram_component.outdata_reg_a = "UNREGISTERED",
+	altsyncram_component.outdata_reg_b = "UNREGISTERED",
+	altsyncram_component.power_up_uninitialized = "FALSE",
+	altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+	altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+	altsyncram_component.widthad_a = 9,
+	altsyncram_component.widthad_b = 9,
+	altsyncram_component.width_a = 8,
+	altsyncram_component.width_b = 8,
+	altsyncram_component.width_byteena_a = 1,
+	altsyncram_component.width_byteena_b = 1,
+	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+endmodule
+

sys/sigma_delta_dac.v

@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule

sys/spdif.v

@@ -0,0 +1,445 @@
+//-----------------------------------------------------------------
+//                        SPDIF Transmitter
+//                              V0.1
+//                        Ultra-Embedded.com
+//                          Copyright 2012
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: GPL
+// If you would like a version with a more permissive license for
+// use in closed source commercial applications please contact me
+// for details.
+//-----------------------------------------------------------------
+//
+// This file is open source HDL; you can redistribute it and/or 
+// modify it under the terms of the GNU General Public License as 
+// published by the Free Software Foundation; either version 2 of 
+// the License, or (at your option) any later version.
+//
+// This file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public 
+// License along with this file; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//-----------------------------------------------------------------
+// altera message_off 10762
+// altera message_off 10240
+
+module spdif
+
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+    parameter CLK_RATE              = 50000000,
+    parameter AUDIO_RATE            = 48000,
+
+    // Generated params
+    parameter WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*128),
+    parameter ERROR_BASE            = 10000,
+    parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
+)
+
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+    input        clk_i,
+    input        rst_i,
+    input        half_rate,
+
+    // Output
+    output       spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [15:0] audio_r,
+    input [15:0] audio_l,
+    output       sample_req_o
+);
+
+reg lpf_ce;
+always @(posedge clk_i) begin
+	reg [2:0] div;
+
+	if(bit_clk_q) div <= div + 1'd1;
+	lpf_ce <= !div;
+end
+
+wire [15:0] al, ar;
+
+lpf_spdif lpf_l
+(
+   .CLK(clk_i),
+   .CE(lpf_ce),
+   .IDATA(audio_l),
+   .ODATA(al)
+);
+
+lpf_spdif lpf_r
+(
+   .CLK(clk_i),
+   .CE(lpf_ce),
+
+   .IDATA(audio_r),
+   .ODATA(ar)
+);
+
+reg         bit_clk_q;
+
+// Clock pulse generator
+always @ (posedge rst_i or posedge clk_i) begin
+	reg [31:0]  count_q;
+	reg [31:0]  error_q;
+	reg ce;
+
+	if (rst_i) begin
+		count_q   <= 0;
+		error_q   <= 0;
+		bit_clk_q <= 1;
+		ce        <= 0;
+	end
+	else
+	begin
+		if(count_q == WHOLE_CYCLES-1) begin
+			if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0];
+				count_q <= 0;
+			end else begin
+				error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
+				count_q <= count_q + 1;
+			end
+		end else if(count_q == WHOLE_CYCLES) begin
+			count_q <= 0;
+		end else begin
+			count_q <= count_q + 1;
+		end
+
+		bit_clk_q <= 0;
+		if(!count_q) begin
+			ce <= ~ce;
+			if(~half_rate || ce) bit_clk_q <= 1;
+		end
+	end
+end
+
+//-----------------------------------------------------------------
+// Core SPDIF
+//-----------------------------------------------------------------
+
+wire [31:0] sample_i = {ar, al};
+
+spdif_core
+u_core
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    .bit_out_en_i(bit_clk_q),
+
+    .spdif_o(spdif_o),
+
+    .sample_i(sample_i),
+    .sample_req_o(sample_req_o)
+);
+
+endmodule
+
+module spdif_core
+(
+    input           clk_i,
+    input           rst_i,
+
+    // SPDIF bit output enable
+    // Single cycle pulse synchronous to clk_i which drives
+    // the output bit rate.
+    // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
+    // For 48KHz,   48000×32×2×2 = 6,144,000Hz
+    input           bit_out_en_i,
+
+    // Output
+    output          spdif_o,
+
+    // Audio interface (16-bit x 2 = RL)
+    input [31:0]    sample_i,
+    output reg      sample_req_o
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [15:0]  audio_sample_q;
+reg [8:0]   subframe_count_q;
+
+reg         load_subframe_q;
+reg [7:0]   preamble_q;
+wire [31:0] subframe_w;
+
+reg [5:0]   bit_count_q;
+reg         bit_toggle_q;
+
+reg         spdif_out_q;
+
+reg [5:0]   parity_count_q;
+
+//-----------------------------------------------------------------
+// Subframe Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+    if (rst_i == 1'b1)
+        subframe_count_q    <= 9'd0;
+    else if (load_subframe_q)
+    begin
+        // 192 frames (384 subframes) in an audio block
+        if (subframe_count_q == 9'd383)
+            subframe_count_q <= 9'd0;
+        else
+            subframe_count_q <= subframe_count_q + 9'd1;
+    end
+end
+
+//-----------------------------------------------------------------
+// Sample capture
+//-----------------------------------------------------------------
+reg [15:0] sample_buf_q;
+
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        audio_sample_q      <= 16'h0000;
+        sample_buf_q        <= 16'h0000;
+        sample_req_o        <= 1'b0;
+   end
+   else if (load_subframe_q)
+   begin
+        // Start of frame (first subframe)?
+        if (subframe_count_q[0] == 1'b0)
+        begin
+            // Use left sample
+            audio_sample_q <= sample_i[15:0];
+
+            // Store right sample
+            sample_buf_q <= sample_i[31:16];
+
+            // Request next sample
+            sample_req_o <= 1'b1;
+        end
+        else
+        begin
+            // Use right sample
+            audio_sample_q <= sample_buf_q;
+
+            sample_req_o <= 1'b0;
+        end
+   end
+   else
+        sample_req_o <= 1'b0;
+end
+
+// Timeslots 3 - 0 = Preamble
+assign subframe_w[3:0] = 4'b0000;
+
+// Timeslots 7 - 4 = 24-bit audio LSB
+assign subframe_w[7:4] = 4'b0000;
+
+// Timeslots 11 - 8 = 20-bit audio LSB
+assign subframe_w[11:8] = 4'b0000;
+
+// Timeslots 27 - 12 = 16-bit audio
+assign subframe_w[27:12] = audio_sample_q;
+
+// Timeslots 28 = Validity
+assign subframe_w[28] = 1'b0; // Valid
+
+// Timeslots 29 = User bit
+assign subframe_w[29] = 1'b0;
+
+// Timeslots 30 = Channel status bit
+assign subframe_w[30] = 1'b0;
+
+// Timeslots 31 = Even Parity bit (31:4)
+assign subframe_w[31] = 1'b0;
+
+//-----------------------------------------------------------------
+// Preamble
+//-----------------------------------------------------------------
+localparam PREAMBLE_Z = 8'b00010111;
+localparam PREAMBLE_Y = 8'b00100111;
+localparam PREAMBLE_X = 8'b01000111;
+
+reg [7:0] preamble_r;
+
+always @ *
+begin
+    // Start of audio block?
+    // Z(B) - Left channel
+    if (subframe_count_q == 9'd0)
+        preamble_r = PREAMBLE_Z; // Z(B)
+    // Right Channel?
+    else if (subframe_count_q[0] == 1'b1)
+        preamble_r = PREAMBLE_Y; // Y(W)
+    // Left Channel (but not start of block)?
+    else
+        preamble_r = PREAMBLE_X; // X(M)
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    preamble_q  <= 8'h00;
+else if (load_subframe_q)
+    preamble_q  <= preamble_r;
+
+//-----------------------------------------------------------------
+// Parity Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i )
+begin
+   if (rst_i == 1'b1)
+   begin
+        parity_count_q  <= 6'd0;
+   end
+   // Time to output a bit?
+   else if (bit_out_en_i)
+   begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            parity_count_q  <= 6'd0;
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            // On first pass through this timeslot, count number of high bits
+            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
+                parity_count_q <= parity_count_q + 6'd1;
+        end
+   end
+end
+
+//-----------------------------------------------------------------
+// Bit Counter
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+begin
+    if (rst_i == 1'b1)
+    begin
+        bit_count_q     <= 6'b0;
+        load_subframe_q <= 1'b1;
+    end
+    // Time to output a bit?
+    else if (bit_out_en_i)
+    begin
+        // 32 timeslots (x2 for double frequency)
+        if (bit_count_q == 6'd63)
+        begin
+            bit_count_q     <= 6'd0;
+            load_subframe_q <= 1'b1;
+        end
+        else
+        begin
+            bit_count_q     <= bit_count_q + 6'd1;
+            load_subframe_q <= 1'b0;
+        end
+    end
+    else
+        load_subframe_q <= 1'b0;
+end
+
+//-----------------------------------------------------------------
+// Bit half toggle
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+if (rst_i == 1'b1)
+    bit_toggle_q    <= 1'b0;
+// Time to output a bit?
+else if (bit_out_en_i)
+    bit_toggle_q <= ~bit_toggle_q;
+
+//-----------------------------------------------------------------
+// Output bit (BMC encoded)
+//-----------------------------------------------------------------
+reg bit_r;
+
+always @ *
+begin
+    bit_r = spdif_out_q;
+
+    // Time to output a bit?
+    if (bit_out_en_i)
+    begin
+        // Preamble bits?
+        if (bit_count_q < 6'd8)
+        begin
+            bit_r = preamble_q[bit_count_q[2:0]];
+        end
+        // Normal timeslots
+        else if (bit_count_q < 6'd62)
+        begin
+            if (subframe_w[bit_count_q / 2] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+        // Parity timeslot
+        else
+        begin
+            // Even number of high bits, make odd
+            if (parity_count_q[0] == 1'b0)
+            begin
+                if (bit_toggle_q == 1'b0)
+                    bit_r = ~spdif_out_q;
+                else
+                    bit_r = spdif_out_q;
+            end
+            else
+                bit_r = ~spdif_out_q;
+        end
+    end
+end
+
+always @ (posedge rst_i or posedge clk_i )
+if (rst_i == 1'b1)
+    spdif_out_q <= 1'b0;
+else
+    spdif_out_q <= bit_r;
+
+assign spdif_o  = spdif_out_q;
+
+endmodule
+
+module lpf_spdif
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule

sys/sys.qip

@@ -0,0 +1,25 @@
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sys_top.v ]
+set_global_assignment -name SDC_FILE           [file join $::quartus(qip_path) sys_top.sdc ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) ascal.vhd ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scandoubler.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scanlines.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) spdif.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sigma_delta_dac.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sd_card.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) hps_io.v ]
+set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi

sys/sys_q13.qip

@@ -0,0 +1,29 @@
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sys_top.v ]
+set_global_assignment -name SDC_FILE           [file join $::quartus(qip_path) sys_top.sdc ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll/pll_0002.v ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll/pll_0002.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) ascal.vhd ]
+set_global_assignment -name VHDL_FILE          [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scandoubler.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) scanlines.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) spdif.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sigma_delta_dac.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sd_card.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) hps_io.v ]
+set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi

sys/sys_top.sdc

@@ -0,0 +1,38 @@
+# Specify root clocks
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
+create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] 
+create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
+
+derive_pll_clocks
+
+# Specify PLL-generated clock(s)
+create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+                       -name HDMI_CLK [get_ports HDMI_TX_CLK]
+
+derive_clock_uncertainty
+
+# Decouple different clock groups (to simplify routing)
+set_clock_groups -asynchronous \
+   -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+   -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+   -group [get_clocks { *|h2f_user0_clk}] \
+   -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
+
+set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+
+set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
+
+
+# Put constraints on input ports
+set_false_path -from [get_ports {KEY*}] -to *
+set_false_path -from [get_ports {BTN_*}] -to *
+
+# Put constraints on output ports
+set_false_path -from * -to [get_ports {LED_*}]
+set_false_path -from * -to [get_ports {VGA_*}]
+set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
+set_false_path -from * -to [get_ports {AUDIO_L}]
+set_false_path -from * -to [get_ports {AUDIO_R}]

sys/sys_top.v

@@ -0,0 +1,933 @@
+//============================================================================
+//
+//  MiSTer hardware abstraction module (Arcade version)
+//  (c)2017-2019 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module sys_top
+(
+	/////////// CLOCK //////////
+	input         FPGA_CLK1_50,
+	input         FPGA_CLK2_50,
+	input         FPGA_CLK3_50,
+
+	//////////// VGA ///////////
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	inout         VGA_HS,  // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
+	output		  VGA_VS,
+	input         VGA_EN,  // active low
+
+	/////////// AUDIO //////////
+	output		  AUDIO_L,
+	output		  AUDIO_R,
+	output		  AUDIO_SPDIF,
+
+	//////////// HDMI //////////
+	output        HDMI_I2C_SCL,
+	inout         HDMI_I2C_SDA,
+
+	output        HDMI_MCLK,
+	output        HDMI_SCLK,
+	output        HDMI_LRCLK,
+	output        HDMI_I2S,
+
+	output        HDMI_TX_CLK,
+	output        HDMI_TX_DE,
+	output [23:0] HDMI_TX_D,
+	output        HDMI_TX_HS,
+	output        HDMI_TX_VS,
+	
+	input         HDMI_TX_INT,
+
+	//////////// SDR ///////////
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE,
+
+	//////////// I/O ///////////
+	output        LED_USER,
+	output        LED_HDD,
+	output        LED_POWER,
+	input         BTN_USER,
+	input         BTN_OSD,
+	input         BTN_RESET,
+
+	//////////// SDIO ///////////
+	inout   [3:0] SDIO_DAT,
+	inout         SDIO_CMD,
+	output        SDIO_CLK,
+	input         SDIO_CD,
+
+	////////// MB KEY ///////////
+	input   [1:0] KEY,
+
+	////////// MB SWITCH ////////
+	input   [3:0] SW,
+
+	////////// MB LED ///////////
+	output  [7:0] LED,
+
+	///////// USER IO ///////////
+	inout   [5:0] USER_IO
+);
+
+
+assign SDIO_DAT[2:1] = 2'bZZ;
+
+
+//////////////////////////  LEDs  ///////////////////////////////////////
+
+reg [7:0] led_overtake = 0;
+reg [7:0] led_state    = 0;
+
+wire led_p =  led_power[1] ? ~led_power[0] : 1'b0;
+wire led_d =  led_disk[1]  ? ~led_disk[0]  : ~(led_disk[0] | gp_out[29]);
+wire led_u = ~led_user;
+wire led_locked;
+
+assign LED_POWER = led_p ? 1'bZ : 1'b0;
+assign LED_HDD   = led_d ? 1'bZ : 1'b0;
+assign LED_USER  = led_u ? 1'bZ : 1'b0;
+
+//LEDs on main board
+assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
+
+
+//////////////////////////  Buttons  ///////////////////////////////////
+reg btn_user, btn_osd;
+always @(posedge FPGA_CLK2_50) begin
+	integer div;
+	reg [7:0] deb_user;
+	reg [7:0] deb_osd;
+
+	div <= div + 1'b1;
+	if(div > 100000) div <= 0;
+	
+	if(!div) begin
+		deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])};
+		if(&deb_user) btn_user <= 1;
+		if(!deb_user) btn_user <= 0;
+
+		deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])};
+		if(&deb_osd) btn_osd <= 1;
+		if(!deb_osd) btn_osd <= 0;
+	end
+end
+
+reg btn_reset = 1;
+always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET;
+
+
+/////////////////////////  HPS I/O  /////////////////////////////////////
+
+// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
+//                 used to avoid lockups while JTAG loading
+wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout};
+wire [31:0] gp_out;
+
+wire  [1:0] io_ver    = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future.
+wire        io_wait;
+wire        io_wide;
+wire [15:0] io_dout;                  
+wire [15:0] io_din    = gp_outr[15:0];
+wire        io_clk    = gp_outr[17];
+wire        io_fpga   = gp_outr[18];
+wire        io_osd    = gp_outr[19];
+wire        io_uio    = gp_outr[20];
+//wire        io_sdd    = gp_outr[21]; // used only in ST core
+
+reg  io_ack;
+reg  rack;
+wire io_strobe = ~rack & io_clk;
+
+always @(posedge clk_sys) begin
+	if(~io_wait | io_strobe) begin
+		rack <= io_clk;
+		io_ack <= rack;
+	end
+end
+
+reg [31:0] gp_outr;
+always @(posedge clk_sys) begin
+	reg [31:0] gp_outd;
+	gp_outr <= gp_outd;
+	gp_outd <= gp_out;
+end
+
+wire  [7:0] core_type  = 'hA4; // A4 - generic core.
+
+// HPS will not communicate to core if magic is different
+wire [31:0] core_magic = {24'h5CA623, core_type};
+
+cyclonev_hps_interface_mpu_general_purpose h2f_gp
+(
+	.gp_in({~gp_out[31] ? core_magic : gp_in}),
+	.gp_out(gp_out)
+);
+
+
+reg [15:0] cfg;
+
+reg  cfg_got   = 0;
+reg  cfg_set   = 0;
+//wire [2:0] hdmi_res  = cfg[10:8];
+wire dvi_mode  = cfg[7];
+wire audio_96k = cfg[6];
+wire ypbpr_en  = cfg[5];
+wire csync     = cfg[3];
+wire vga_scaler= cfg[2];
+
+reg        cfg_custom_t = 0;
+reg  [5:0] cfg_custom_p1;
+reg [31:0] cfg_custom_p2;
+
+reg  [4:0] vol_att = 0;
+
+reg  [6:0] coef_addr;
+reg  [8:0] coef_data;
+reg        coef_wr = 0;
+
+wire  [7:0] ARX, ARY;
+reg  [11:0] VSET = 0;
+reg   [2:0] scaler_flt;
+reg         lowlat = 0;
+
+always@(posedge clk_sys) begin
+	reg  [7:0] cmd;
+	reg        has_cmd;
+	reg        old_strobe;
+	reg  [7:0] cnt = 0;
+
+	old_strobe <= io_strobe;
+	coef_wr <= 0;
+
+	if(~io_uio) begin
+		has_cmd <= 0;
+	end
+	else
+	if(~old_strobe & io_strobe) begin
+		if(!has_cmd) begin
+			has_cmd <= 1;
+			cmd <= io_din[7:0];
+			cnt <= 0;
+		end
+		else begin
+			if(cmd == 1) begin
+				cfg <= io_din;
+				cfg_set <= 1;
+			end
+			if(cmd == 'h20) begin
+				cfg_set <= 0;
+				cnt <= cnt + 1'd1;
+				if(cnt<8) begin
+					case(cnt)
+						0: if(WIDTH  != io_din[11:0]) begin WIDTH  <= io_din[11:0]; end
+						1: if(HFP    != io_din[11:0]) begin HFP    <= io_din[11:0]; end
+						2: if(HS     != io_din[11:0]) begin HS     <= io_din[11:0]; end
+						3: if(HBP    != io_din[11:0]) begin HBP    <= io_din[11:0]; end
+						4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; end
+						5: if(VFP    != io_din[11:0]) begin VFP    <= io_din[11:0]; end
+						6: if(VS     != io_din[11:0]) begin VS     <= io_din[11:0]; end
+						7: if(VBP    != io_din[11:0]) begin VBP    <= io_din[11:0]; end
+					endcase
+					if(cnt == 1) begin
+						cfg_custom_p1 <= 0;
+						cfg_custom_p2 <= 0;
+						cfg_custom_t <= ~cfg_custom_t;
+					end
+				end
+				else begin
+					if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0];
+					if(cnt[1:0]==1) cfg_custom_p2[15:0]  <= io_din;
+					if(cnt[1:0]==2) begin
+						cfg_custom_p2[31:16] <= io_din;
+						cfg_custom_t <= ~cfg_custom_t;
+						cnt[2:0] <= 3'b100;
+					end
+					if(cnt == 8) lowlat <= io_din[15];
+				end
+			end
+			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
+			if(cmd == 'h26) vol_att <= io_din[4:0];
+			if(cmd == 'h27) VSET    <= io_din[11:0];
+			if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
+			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
+		end
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg vsd, vsd2;
+	if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
+	else begin
+		vsd  <= HDMI_TX_VS;
+		vsd2 <= vsd;
+		if(~vsd2 & vsd) cfg_got <= cfg_set;
+	end
+end
+
+wire aspi_sck,aspi_mosi,aspi_ss;
+cyclonev_hps_interface_peripheral_spi_master spi
+(
+	.sclk_out(aspi_sck),
+	.txd(aspi_mosi), // mosi
+	.rxd(1),         // miso
+
+	.ss_0_n(aspi_ss),
+	.ss_in_n(1)
+);
+
+
+///////////////////////////  RESET  ///////////////////////////////////
+
+reg reset_req = 0;
+always @(posedge FPGA_CLK2_50) begin
+	reg [1:0] resetd, resetd2;
+	reg       old_reset;
+
+	//latch the reset
+	old_reset <= reset;
+	if(~old_reset & reset) reset_req <= 1;
+
+	//special combination to set/clear the reset
+	//preventing of accidental reset control
+	if(resetd==1) reset_req <= 1;
+	if(resetd==2 && resetd2==0) reset_req <= 0;
+
+	resetd  <= gp_out[31:30];
+	resetd2 <= resetd;
+end
+
+wire clk_100m;
+wire clk_hdmi  = ~HDMI_TX_CLK;  // Internal HDMI clock, inverted in relation to external clock
+wire clk_audio = FPGA_CLK3_50;
+
+////////////////////  SYSTEM MEMORY & SCALER  /////////////////////////
+
+wire reset;
+sysmem_lite sysmem
+(
+	//Reset/Clock
+	.reset_core_req(reset_req),
+	.reset_out(reset),
+	.clock(clk_100m),
+
+	//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
+	.reset_hps_cold_req(~btn_reset),
+
+	//64-bit DDR3 RAM access
+	.ram2_clk(clk_audio),
+	.ram2_address(aram_address),
+	.ram2_burstcount(aram_burstcount),
+	.ram2_waitrequest(aram_waitrequest),
+	.ram2_readdata(aram_readdata),
+	.ram2_readdatavalid(aram_readdatavalid),
+	.ram2_read(aram_read),
+	.ram2_writedata(0),
+	.ram2_byteenable(8'hFF),
+	.ram2_write(0),
+
+	// HDMI frame buffer
+	.vbuf_clk(clk_100m),
+	.vbuf_address(vbuf_address),
+	.vbuf_burstcount(vbuf_burstcount),
+	.vbuf_waitrequest(vbuf_waitrequest),
+	.vbuf_writedata(vbuf_writedata),
+	.vbuf_byteenable(vbuf_byteenable),
+	.vbuf_write(vbuf_write),
+	.vbuf_readdata(vbuf_readdata),
+	.vbuf_readdatavalid(vbuf_readdatavalid),
+	.vbuf_read(vbuf_read)
+);
+
+wire  [27:0] vbuf_address;
+wire   [7:0] vbuf_burstcount;
+wire         vbuf_waitrequest;
+wire [127:0] vbuf_readdata;
+wire         vbuf_readdatavalid;
+wire         vbuf_read;
+wire [127:0] vbuf_writedata;
+wire  [15:0] vbuf_byteenable;
+wire         vbuf_write;
+
+ascal 
+#(
+	.RAMBASE(32'h20000000),
+	.N_DW(128),
+	.N_AW(28)
+)
+ascal
+(
+	.reset_na (~reset_req),
+	.run      (1),
+	.freeze   (0),
+
+	.i_clk  (clk_ihdmi),
+	.i_ce   (ce_hpix),
+	.i_r    (hr_out),
+	.i_g    (hg_out),
+	.i_b    (hb_out),
+	.i_hs   (hhs),
+	.i_vs   (hvs),
+	.i_fl   (0),
+	.i_de   (hde),
+	.iauto  (1),
+	.himin  (0),
+	.himax  (0),
+	.vimin  (0),
+	.vimax  (0),
+
+	.o_clk  (clk_hdmi),
+	.o_ce   (1),
+	.o_r    (hdmi_data[23:16]),
+	.o_g    (hdmi_data[15:8]),
+	.o_b    (hdmi_data[7:0]),
+	.o_hs   (HDMI_TX_HS),
+	.o_vs   (HDMI_TX_VS),
+	.o_de   (hdmi_de),
+	.o_lltune (lltune),
+	.htotal (WIDTH+HFP+HBP+HS),
+	.hsstart(WIDTH + HFP),
+	.hsend  (WIDTH + HFP + HS),
+	.hdisp  (WIDTH),
+	.hmin   (hmin),
+	.hmax   (hmax),
+	.vtotal (HEIGHT+VFP+VBP+VS),
+	.vsstart(HEIGHT + VFP),
+	.vsend  (HEIGHT + VFP + VS),
+	.vdisp  (HEIGHT),
+	.vmin   (vmin),
+	.vmax   (vmax),
+
+	.mode     ({~lowlat,|scaler_flt,2'b00}),
+	.poly_clk (clk_sys),
+	.poly_a   (coef_addr),
+	.poly_dw  (coef_data),
+	.poly_wr  (coef_wr),
+
+	.avl_clk          (clk_100m),
+	.avl_waitrequest  (vbuf_waitrequest),
+	.avl_readdata     (vbuf_readdata),
+	.avl_readdatavalid(vbuf_readdatavalid),
+	.avl_burstcount   (vbuf_burstcount),
+	.avl_writedata    (vbuf_writedata),
+	.avl_address      (vbuf_address),
+	.avl_write        (vbuf_write),
+	.avl_read         (vbuf_read),
+	.avl_byteenable   (vbuf_byteenable)
+);
+
+reg [11:0] hmin;
+reg [11:0] hmax;
+reg [11:0] vmin;
+reg [11:0] vmax;
+
+always @(posedge clk_vid) begin
+	reg [31:0] wcalc;
+	reg [31:0] hcalc;
+	reg  [2:0] state;
+	reg [11:0] videow;
+	reg [11:0] videoh;
+
+	state <= state + 1'd1;
+	case(state)
+		0: begin
+				wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
+				hcalc <= (WIDTH*ARY)/ARX;
+			end
+		6: begin
+				videow <= (!VSET && (wcalc > WIDTH))     ? WIDTH  : wcalc[11:0];
+				videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
+			end
+		7: begin
+				hmin <= ((WIDTH  - videow)>>1);
+				hmax <= ((WIDTH  - videow)>>1) + videow - 1'd1;
+				vmin <= ((HEIGHT - videoh)>>1);
+				vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1;
+			end
+	endcase
+end
+
+wire [15:0] lltune;
+
+pll_hdmi_adj pll_hdmi_adj
+(
+   .clk(FPGA_CLK1_50),
+	.reset_na(~reset_req),
+
+	.llena(lowlat),
+	.lltune(lltune),
+	.locked(led_locked),
+	.i_waitrequest(adj_waitrequest),
+	.i_write(adj_write),
+	.i_address(adj_address),
+	.i_writedata(adj_data),
+	.o_waitrequest(cfg_waitrequest),
+	.o_write(cfg_write),
+	.o_address(cfg_address),
+	.o_writedata(cfg_data)
+);
+
+
+/////////////////////////  HDMI output  /////////////////////////////////
+
+pll_hdmi pll_hdmi
+(
+	.refclk(FPGA_CLK1_50),
+	.rst(reset_req),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll),
+	.outclk_0(HDMI_TX_CLK)
+);
+
+//1920x1080@60 PCLK=148.5MHz CEA
+reg  [11:0] WIDTH  = 1920;
+reg  [11:0] HFP    = 88;
+reg  [11:0] HS     = 48;
+reg  [11:0] HBP    = 148;
+reg  [11:0] HEIGHT = 1080;
+reg  [11:0] VFP    = 4;
+reg  [11:0] VS     = 5;
+reg  [11:0] VBP    = 36;
+
+wire [63:0] reconfig_to_pll;
+wire [63:0] reconfig_from_pll;
+wire        cfg_waitrequest,adj_waitrequest;
+reg         cfg_write,adj_write;
+reg   [5:0] cfg_address,adj_address;
+reg  [31:0] cfg_data,adj_data;
+
+pll_hdmi_cfg pll_hdmi_cfg
+(
+	.mgmt_clk(FPGA_CLK1_50),
+	.mgmt_reset(reset_req),
+	.mgmt_waitrequest(cfg_waitrequest),
+	.mgmt_read(0),
+	.mgmt_readdata(),
+	.mgmt_write(cfg_write),
+	.mgmt_address(cfg_address),
+	.mgmt_writedata(cfg_data),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll)
+);
+
+reg cfg_ready = 0;
+
+always @(posedge FPGA_CLK1_50) begin
+	reg gotd = 0, gotd2 = 0;
+	reg custd = 0, custd2 = 0;
+	reg old_wait = 0;
+
+	gotd  <= cfg_got;
+	gotd2 <= gotd;
+	
+	adj_write <= 0;
+	
+	custd <= cfg_custom_t;
+	custd2 <= custd;
+	if(custd2 != custd & ~gotd) begin
+		adj_address <= cfg_custom_p1;
+		adj_data <= cfg_custom_p2;
+		adj_write <= 1;
+	end
+
+	if(~gotd2 & gotd) begin
+		adj_address <= 2;
+		adj_data <= 0;
+		adj_write <= 1;
+	end
+
+	old_wait <= adj_waitrequest;
+	if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
+end
+
+hdmi_config hdmi_config
+(
+	.iCLK(FPGA_CLK1_50),
+	.iRST_N(cfg_ready & ~HDMI_TX_INT),
+
+	.I2C_SCL(HDMI_I2C_SCL),
+	.I2C_SDA(HDMI_I2C_SDA),
+
+	.dvi_mode(dvi_mode),
+	.audio_96k(audio_96k)
+);
+
+wire [23:0] hdmi_data;
+wire [23:0] hdmi_data_sl;
+wire        hdmi_de;
+
+scanlines #(1) HDMI_scanlines
+(
+	.clk(clk_hdmi),
+
+	.scanlines(scanlines),
+	.din(hdmi_data),
+	.dout(hdmi_data_sl),
+	.hs(HDMI_TX_HS),
+	.vs(HDMI_TX_VS)
+);
+
+osd hdmi_osd
+(
+	.clk_sys(clk_sys),
+
+	.io_osd(io_osd),
+	.io_strobe(io_strobe),
+	.io_din(io_din),
+
+	.clk_video(clk_hdmi),
+	.din(hdmi_data_sl),
+	.dout(HDMI_TX_D),
+	.de_in(hdmi_de),
+	.de_out(HDMI_TX_DE)
+);
+
+/////////////////////////  VGA output  //////////////////////////////////
+
+wire [23:0] vga_data_sl;
+
+scanlines #(0) VGA_scanlines
+(
+	.clk(clk_vid),
+
+	.scanlines(scanlines),
+	.din(de ? {r_out, g_out, b_out} : 24'd0),
+	.dout(vga_data_sl),
+	.hs(hs1),
+	.vs(vs1)
+);
+
+osd vga_osd
+(
+	.clk_sys(clk_sys),
+
+	.io_osd(io_osd),
+	.io_strobe(io_strobe),
+	.io_din(io_din),
+
+	.clk_video(clk_vid),
+	.din(vga_data_sl),
+	.dout(vga_q),
+	.de_in(de)
+);
+
+wire [23:0] vga_q;
+wire [23:0] vga_o;
+
+vga_out vga_out
+(
+	.ypbpr_full(1),
+	.ypbpr_en(ypbpr_en),
+	.dout(vga_o),
+	.din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q)
+);
+
+wire vs1 = vga_scaler ? HDMI_TX_VS : vs;
+wire hs1 = vga_scaler ? HDMI_TX_HS : hs;
+
+assign VGA_VS = VGA_EN ? 1'bZ      : csync ?     1'b1     : ~vs1;
+assign VGA_HS = VGA_EN ? 1'bZ      : csync ? ~(vs1 ^ hs1) : ~hs1;
+assign VGA_R  = VGA_EN ? 6'bZZZZZZ : vga_o[23:18];
+assign VGA_G  = VGA_EN ? 6'bZZZZZZ : vga_o[15:10];
+assign VGA_B  = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
+
+
+/////////////////////////  Audio output  ////////////////////////////////
+
+assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
+assign AUDIO_R     = SW[0] ? HDMI_I2S   : anr;
+assign AUDIO_L     = SW[0] ? HDMI_SCLK  : anl;
+
+assign HDMI_MCLK = 0;
+i2s i2s
+(
+	.clk_sys(clk_audio),
+	.reset(reset),
+
+	.half_rate(~audio_96k),
+
+	.sclk(HDMI_SCLK),
+	.lrclk(HDMI_LRCLK),
+	.sdata(HDMI_I2S),
+
+	.left_chan (audio_l),
+	.right_chan(audio_r)
+);
+
+wire anl;
+sigma_delta_dac #(15) dac_l
+(
+	.CLK(clk_audio),
+	.RESET(reset),
+	.DACin({~audio_l[15], audio_l[14:0]}),
+	.DACout(anl)
+);
+
+wire anr;
+sigma_delta_dac #(15) dac_r
+(
+	.CLK(clk_audio),
+	.RESET(reset),
+	.DACin({~audio_r[15], audio_r[14:0]}),
+	.DACout(anr)
+);
+
+wire aspdif;
+spdif toslink
+(
+	.clk_i(clk_audio),
+
+	.rst_i(reset),
+	.half_rate(0),
+
+	.audio_l(audio_l),
+	.audio_r(audio_r),
+
+	.spdif_o(aspdif)
+);
+
+wire [15:0] audio_l, audio_l_pre;
+aud_mix_top audmix_l
+(
+	.clk(clk_audio),
+	.att(vol_att),
+	.mix(audio_mix),
+	.is_signed(audio_s),
+
+	.core_audio(audio_ls),
+	.pre_in(audio_r_pre),
+	.linux_audio(alsa_l),
+
+	.pre_out(audio_l_pre),
+	.out(audio_l)
+);
+
+wire [15:0] audio_r, audio_r_pre;
+aud_mix_top audmix_r
+(
+	.clk(clk_audio),
+	.att(vol_att),
+	.mix(audio_mix),
+	.is_signed(audio_s),
+
+	.core_audio(audio_rs),
+	.pre_in(audio_l_pre),
+	.linux_audio(alsa_r),
+
+	.pre_out(audio_r_pre),
+	.out(audio_r)
+);
+
+wire [28:0] aram_address;
+wire  [7:0] aram_burstcount;
+wire        aram_waitrequest;
+wire [63:0] aram_readdata;
+wire        aram_readdatavalid;
+wire        aram_read;
+
+wire [15:0] alsa_l, alsa_r;
+
+alsa alsa
+(
+	.reset(reset),
+
+	.ram_clk(clk_audio),
+	.ram_address(aram_address),
+	.ram_burstcount(aram_burstcount),
+	.ram_waitrequest(aram_waitrequest),
+	.ram_readdata(aram_readdata),
+	.ram_readdatavalid(aram_readdatavalid),
+	.ram_read(aram_read),
+
+	.spi_ss(aspi_ss),
+	.spi_sck(aspi_sck),
+	.spi_mosi(aspi_mosi),
+
+	.pcm_l(alsa_l),
+	.pcm_r(alsa_r)
+);
+
+
+////////////////  User I/O (USB 3.0 connector) /////////////////////////
+
+assign USER_IO[0] = 1'bZ;
+assign USER_IO[1] = 1'bZ;
+assign USER_IO[2] = (SW[1] & ~HDMI_I2S)   ? 1'b0 : 1'bZ;
+assign USER_IO[3] = 1'bZ;
+assign USER_IO[4] = (SW[1] & ~HDMI_SCLK)  ? 1'b0 : 1'bZ;
+assign USER_IO[5] = (SW[1] & ~HDMI_LRCLK) ? 1'b0 : 1'bZ;
+
+
+///////////////////  User module connection ////////////////////////////
+
+wire [15:0] audio_ls, audio_rs;
+wire        audio_s;
+wire  [1:0] audio_mix;
+wire  [7:0] r_out, g_out, b_out;
+wire        vs, hs, de;
+wire  [1:0] scanlines;
+wire        clk_sys, clk_vid, ce_pix;
+wire        led_user;
+wire  [1:0] led_power;
+wire  [1:0] led_disk;
+
+wire  [7:0] hr_out, hg_out, hb_out;
+wire        hvs, hhs, hde;
+wire        clk_ihdmi, ce_hpix;
+
+wire hvs_emu, hhs_emu;
+sync_fix hdmi_sync_v(clk_ihdmi, hvs_emu, hvs);
+sync_fix hdmi_sync_h(clk_ihdmi, hhs_emu, hhs);
+
+wire vs_emu, hs_emu;
+sync_fix sync_v(clk_vid, vs_emu, vs);
+sync_fix sync_h(clk_vid, hs_emu, hs);
+
+assign audio_mix = 0;
+assign {SDIO_CLK, SDIO_CMD, SDIO_DAT[3]} = {3{1'bZ}};
+assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39{1'bZ}};
+
+emu emu
+(
+	.CLK_50M(FPGA_CLK3_50),
+	.RESET(reset),
+	.HPS_BUS({HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
+
+	.VGA_CLK(clk_vid),
+	.VGA_CE(ce_pix),
+	.VGA_R(r_out),
+	.VGA_G(g_out),
+	.VGA_B(b_out),
+	.VGA_HS(hs_emu),
+	.VGA_VS(vs_emu),
+	.VGA_DE(de),
+
+	.HDMI_CLK(clk_ihdmi),
+	.HDMI_CE(ce_hpix),
+	.HDMI_R(hr_out),
+	.HDMI_G(hg_out),
+	.HDMI_B(hb_out),
+	.HDMI_HS(hhs_emu),
+	.HDMI_VS(hvs_emu),
+	.HDMI_DE(hde),
+	.HDMI_SL(scanlines),
+	.HDMI_ARX(ARX),
+	.HDMI_ARY(ARY),
+
+	.LED_USER(led_user),
+	.LED_POWER(led_power),
+	.LED_DISK(led_disk),
+
+	.AUDIO_L(audio_ls),
+	.AUDIO_R(audio_rs),
+	.AUDIO_S(audio_s)
+);
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////
+
+module sync_fix
+(
+	input clk,
+	
+	input sync_in,
+	output sync_out
+);
+
+assign sync_out = sync_in ^ pol;
+
+reg pol;
+always @(posedge clk) begin
+	integer pos = 0, neg = 0, cnt = 0;
+	reg s1,s2;
+
+	s1 <= sync_in;
+	s2 <= s1;
+
+	if(~s2 & s1) neg <= cnt;
+	if(s2 & ~s1) pos <= cnt;
+
+	cnt <= cnt + 1;
+	if(s2 != s1) cnt <= 0;
+
+	pol <= pos > neg;
+end
+
+endmodule
+
+/////////////////////////////////////////////////////////////////////
+
+module aud_mix_top
+(
+	input             clk,
+
+	input       [4:0] att,
+	input       [1:0] mix,
+	input             is_signed,
+
+	input      [15:0] core_audio,
+	input      [15:0] linux_audio,
+	input      [15:0] pre_in,
+
+	output reg [15:0] pre_out,
+	output reg [15:0] out
+);
+
+reg [15:0] ca;
+always @(posedge clk) begin
+	reg [15:0] d1,d2,d3;
+
+	d1 <= core_audio; d2<=d1; d3<=d2;
+	if(d2 == d3) ca <= d2;
+end
+
+always @(posedge clk) begin
+	reg signed [16:0] a1, a2, a3, a4;
+
+	a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]};
+	a2 <= a1 + {linux_audio[15],linux_audio};
+
+	pre_out <= a2[16:1];
+
+	case(mix)
+		0: a3 <= a2;
+		1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
+		2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
+		3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
+	endcase
+
+	if(att[4]) a4 <= 0;
+	else a4 <= a3 >>> att[3:0];
+
+	//clamping
+	out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
+end
+
+endmodule

sys/sysmem.sv

@@ -0,0 +1,429 @@
+`timescale 1 ps / 1 ps
+module sysmem_lite
+(
+	output         clock,
+	output         reset_out,
+
+	input          reset_hps_cold_req,
+	input          reset_hps_warm_req,
+	input          reset_core_req,
+
+	input          ram1_clk,
+	input   [28:0] ram1_address,
+	input    [7:0] ram1_burstcount,
+	output         ram1_waitrequest,
+	output  [63:0] ram1_readdata,
+	output         ram1_readdatavalid,
+	input          ram1_read,
+	input   [63:0] ram1_writedata,
+	input    [7:0] ram1_byteenable,
+	input          ram1_write,
+
+	input          ram2_clk,
+	input   [28:0] ram2_address,
+	input    [7:0] ram2_burstcount,
+	output         ram2_waitrequest,
+	output  [63:0] ram2_readdata,
+	output         ram2_readdatavalid,
+	input          ram2_read,
+	input   [63:0] ram2_writedata,
+	input    [7:0] ram2_byteenable,
+	input          ram2_write,
+
+	input          vbuf_clk,
+	input   [27:0] vbuf_address,
+	input    [7:0] vbuf_burstcount,
+	output         vbuf_waitrequest,
+	output [127:0] vbuf_readdata,
+	output         vbuf_readdatavalid,
+	input          vbuf_read,
+	input  [127:0] vbuf_writedata,
+	input   [15:0] vbuf_byteenable,
+	input          vbuf_write
+);
+
+assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
+
+sysmem_HPS_fpga_interfaces fpga_interfaces (
+	.f2h_cold_rst_req_n       (~reset_hps_cold_req),
+	.f2h_warm_rst_req_n       (~reset_hps_warm_req),
+	.h2f_user0_clk            (clock),
+	.h2f_rst_n                (hps_h2f_reset_n),
+	.f2h_sdram0_clk           (vbuf_clk),
+	.f2h_sdram0_ADDRESS       (vbuf_address),
+	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),
+	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),
+	.f2h_sdram0_READDATA      (vbuf_readdata),
+	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
+	.f2h_sdram0_READ          (vbuf_read),
+	.f2h_sdram0_WRITEDATA     (vbuf_writedata),
+	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),
+	.f2h_sdram0_WRITE         (vbuf_write),
+	.f2h_sdram1_clk           (ram1_clk),
+	.f2h_sdram1_ADDRESS       (ram1_address),
+	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),
+	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),
+	.f2h_sdram1_READDATA      (ram1_readdata),
+	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
+	.f2h_sdram1_READ          (ram1_read),
+	.f2h_sdram1_WRITEDATA     (ram1_writedata),
+	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),
+	.f2h_sdram1_WRITE         (ram1_write),
+	.f2h_sdram2_clk           (ram2_clk),
+	.f2h_sdram2_ADDRESS       (ram2_address),
+	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),
+	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),
+	.f2h_sdram2_READDATA      (ram2_readdata),
+	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
+	.f2h_sdram2_READ          (ram2_read),
+	.f2h_sdram2_WRITEDATA     (ram2_writedata),
+	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),
+	.f2h_sdram2_WRITE         (ram2_write)
+);
+
+wire hps_h2f_reset_n;
+
+reg init_reset_n = 0;
+always @(posedge clock) begin
+	integer timeout = 0;
+
+	if(timeout < 2000000) begin
+		init_reset_n <= 0;
+		timeout <= timeout + 1;
+	end
+	else init_reset_n <= 1;
+end
+
+endmodule
+
+
+module sysmem_HPS_fpga_interfaces
+(
+	// h2f_reset
+	output wire [1 - 1 : 0 ] h2f_rst_n
+
+	// f2h_cold_reset_req
+	,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
+
+	// f2h_warm_reset_req
+	,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
+
+	// h2f_user0_clock
+	,output wire [1 - 1 : 0 ] h2f_user0_clk
+
+	// f2h_sdram0_data
+	,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
+	,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram0_READ
+	,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
+	,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
+
+	// f2h_sdram0_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram0_clk
+
+	// f2h_sdram1_data
+	,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram1_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
+
+	// f2h_sdram1_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram1_clk
+
+	// f2h_sdram2_data
+	,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
+	,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
+	,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
+	,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
+	,input wire [1 - 1 : 0 ] f2h_sdram2_READ
+	,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
+	,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
+	,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
+
+	// f2h_sdram2_clock
+	,input wire [1 - 1 : 0 ] f2h_sdram2_clk
+);
+
+
+wire [29 - 1 : 0] intermediate;
+assign intermediate[0:0] = ~intermediate[1:1];
+assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
+assign intermediate[2:2] = intermediate[9:9];
+assign intermediate[3:3] = intermediate[9:9];
+assign intermediate[5:5] = intermediate[9:9];
+assign intermediate[6:6] = intermediate[9:9];
+assign intermediate[10:10] = intermediate[9:9];
+assign intermediate[11:11] = ~intermediate[12:12];
+assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
+assign intermediate[13:13] = intermediate[18:18];
+assign intermediate[15:15] = intermediate[18:18];
+assign intermediate[19:19] = intermediate[18:18];
+assign intermediate[20:20] = ~intermediate[21:21];
+assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
+assign intermediate[22:22] = intermediate[27:27];
+assign intermediate[24:24] = intermediate[27:27];
+assign intermediate[28:28] = intermediate[27:27];
+assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
+assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
+assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
+assign intermediate[4:4] = f2h_sdram0_READ[0:0];
+assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
+assign intermediate[9:9] = f2h_sdram0_clk[0:0];
+assign intermediate[14:14] = f2h_sdram1_READ[0:0];
+assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
+assign intermediate[18:18] = f2h_sdram1_clk[0:0];
+assign intermediate[23:23] = f2h_sdram2_READ[0:0];
+assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
+assign intermediate[27:27] = f2h_sdram2_clk[0:0];
+
+cyclonev_hps_interface_clocks_resets clocks_resets(
+ .f2h_warm_rst_req_n({
+    f2h_warm_rst_req_n[0:0] // 0:0
+  })
+,.f2h_pending_rst_ack({
+    1'b1 // 0:0
+  })
+,.f2h_dbg_rst_req_n({
+    1'b1 // 0:0
+  })
+,.h2f_rst_n({
+    h2f_rst_n[0:0] // 0:0
+  })
+,.f2h_cold_rst_req_n({
+    f2h_cold_rst_req_n[0:0] // 0:0
+  })
+,.h2f_user0_clk({
+    h2f_user0_clk[0:0] // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_dbg_apb debug_apb(
+ .DBG_APB_DISABLE({
+    1'b0 // 0:0
+  })
+,.P_CLK_EN({
+    1'b0 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_tpiu_trace tpiu(
+ .traceclk_ctl({
+    1'b1 // 0:0
+  })
+);
+
+
+cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
+ .boot_from_fpga_ready({
+    1'b0 // 0:0
+  })
+,.boot_from_fpga_on_failure({
+    1'b0 // 0:0
+  })
+,.bsel_en({
+    1'b0 // 0:0
+  })
+,.csel_en({
+    1'b0 // 0:0
+  })
+,.csel({
+    2'b01 // 1:0
+  })
+,.bsel({
+    3'b001 // 2:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2hps fpga2hps(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_hps2fpga hps2fpga(
+ .port_size_config({
+    2'b11 // 1:0
+  })
+);
+
+
+cyclonev_hps_interface_fpga2sdram f2sdram(
+ .cfg_rfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.cfg_wfifo_cport_map({
+    16'b0010000100000000 // 15:0
+  })
+,.rd_ready_3({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_2({
+    intermediate[28:28] // 0:0
+  })
+,.rd_ready_2({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_1({
+    intermediate[19:19] // 0:0
+  })
+,.rd_ready_1({
+    1'b1 // 0:0
+  })
+,.cmd_port_clk_0({
+    intermediate[10:10] // 0:0
+  })
+,.rd_ready_0({
+    1'b1 // 0:0
+  })
+,.wrack_ready_2({
+    1'b1 // 0:0
+  })
+,.wrack_ready_1({
+    1'b1 // 0:0
+  })
+,.wrack_ready_0({
+    1'b1 // 0:0
+  })
+,.cmd_ready_2({
+    intermediate[21:21] // 0:0
+  })
+,.cmd_ready_1({
+    intermediate[12:12] // 0:0
+  })
+,.cmd_ready_0({
+    intermediate[1:1] // 0:0
+  })
+,.cfg_port_width({
+    12'b000000010110 // 11:0
+  })
+,.rd_valid_3({
+    f2h_sdram2_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_2({
+    f2h_sdram1_READDATAVALID[0:0] // 0:0
+  })
+,.rd_valid_1({
+    f2h_sdram0_READDATAVALID[0:0] // 0:0
+  })
+,.rd_clk_3({
+    intermediate[22:22] // 0:0
+  })
+,.rd_data_3({
+    f2h_sdram2_READDATA[63:0] // 63:0
+  })
+,.rd_clk_2({
+    intermediate[13:13] // 0:0
+  })
+,.rd_data_2({
+    f2h_sdram1_READDATA[63:0] // 63:0
+  })
+,.rd_clk_1({
+    intermediate[3:3] // 0:0
+  })
+,.rd_data_1({
+    f2h_sdram0_READDATA[127:64] // 63:0
+  })
+,.rd_clk_0({
+    intermediate[2:2] // 0:0
+  })
+,.rd_data_0({
+    f2h_sdram0_READDATA[63:0] // 63:0
+  })
+,.cfg_axi_mm_select({
+    6'b000000 // 5:0
+  })
+,.cmd_valid_2({
+    intermediate[26:26] // 0:0
+  })
+,.cmd_valid_1({
+    intermediate[17:17] // 0:0
+  })
+,.cmd_valid_0({
+    intermediate[8:8] // 0:0
+  })
+,.cfg_cport_rfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_data_3({
+    2'b00 // 89:88
+   ,f2h_sdram2_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram2_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_2({
+    2'b00 // 89:88
+   ,f2h_sdram1_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram1_WRITEDATA[63:0] // 63:0
+  })
+,.wr_data_1({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[15:8] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[127:64] // 63:0
+  })
+,.cfg_cport_type({
+    12'b000000111111 // 11:0
+  })
+,.wr_data_0({
+    2'b00 // 89:88
+   ,f2h_sdram0_BYTEENABLE[7:0] // 87:80
+   ,16'b0000000000000000 // 79:64
+   ,f2h_sdram0_WRITEDATA[63:0] // 63:0
+  })
+,.cfg_cport_wfifo_map({
+    18'b000000000011010000 // 17:0
+  })
+,.wr_clk_3({
+    intermediate[24:24] // 0:0
+  })
+,.wr_clk_2({
+    intermediate[15:15] // 0:0
+  })
+,.wr_clk_1({
+    intermediate[6:6] // 0:0
+  })
+,.wr_clk_0({
+    intermediate[5:5] // 0:0
+  })
+,.cmd_data_2({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram2_ADDRESS[28:0] // 30:2
+   ,intermediate[25:25] // 1:1
+   ,intermediate[23:23] // 0:0
+  })
+,.cmd_data_1({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
+   ,3'b000 // 33:31
+   ,f2h_sdram1_ADDRESS[28:0] // 30:2
+   ,intermediate[16:16] // 1:1
+   ,intermediate[14:14] // 0:0
+  })
+,.cmd_data_0({
+    18'b000000000000000000 // 59:42
+   ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
+   ,4'b0000 // 33:30
+   ,f2h_sdram0_ADDRESS[27:0] // 29:2
+   ,intermediate[7:7] // 1:1
+   ,intermediate[4:4] // 0:0
+  })
+);
+
+endmodule

sys/vga_out.sv

@@ -0,0 +1,65 @@
+
+module vga_out
+(
+	input         ypbpr_full,
+	input         ypbpr_en,
+
+	input  [23:0] din,
+	output [23:0] dout
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+wire [5:0] red   = din[23:18];
+wire [5:0] green = din[15:10];
+wire [5:0] blue  = din[7:2];
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
+assign dout[15:8]  = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]), 2'b00} : din[15:8];
+assign dout[7:0]   = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
+
+
+endmodule

sys/video_cleaner.sv

@@ -0,0 +1,91 @@
+//
+//
+// Copyright (c) 2018 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module video_cleaner
+(
+	input            clk_vid,
+	input            ce_pix,
+
+	input      [7:0] R,
+	input      [7:0] G,
+	input      [7:0] B,
+
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output           VGA_DE,
+	
+	// optional aligned blank
+	output reg       HBlank_out,
+	output reg       VBlank_out
+);
+
+wire hs, vs;
+s_fix sync_v(clk_vid, HSync, hs);
+s_fix sync_h(clk_vid, VSync, vs);
+
+wire hbl = hs | HBlank;
+wire vbl = vs | VBlank;
+
+assign VGA_DE = ~(HBlank_out | VBlank_out);
+
+always @(posedge clk_vid) begin
+	if(ce_pix) begin
+		HBlank_out <= hbl;
+
+		VGA_VS <= vs;
+		VGA_HS <= hs;
+		VGA_R  <= R;
+		VGA_G  <= G;
+		VGA_B  <= B;
+
+		if(HBlank_out & ~hbl) VBlank_out <= vbl;
+	end
+end
+
+endmodule
+
+module s_fix
+(
+	input clk,
+	
+	input sync_in,
+	output sync_out
+);
+
+assign sync_out = sync_in ^ pol;
+
+reg pol;
+always @(posedge clk) begin
+	integer pos = 0, neg = 0, cnt = 0;
+	reg s1,s2;
+
+	s1 <= sync_in;
+	s2 <= s1;
+
+	if(~s2 & s1) neg <= cnt;
+	if(s2 & ~s1) pos <= cnt;
+
+	cnt <= cnt + 1;
+	if(s2 != s1) cnt <= 0;
+
+	pol <= pos > neg;
+end
+
+endmodule

sys/video_mixer.sv

@@ -0,0 +1,167 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 4 bits per component
+//              For half depth 8 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input            clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input            ce_pix,
+	output           ce_pix_out,
+
+	input            scandoubler,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input      [1:0] scanlines,
+
+	// High quality 2x scaling
+	input            hq2x,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// Positive pulses.
+	input            HSync,
+	input            VSync,
+	input            HBlank,
+	input            VBlank,
+
+	// video output signals
+	output reg [7:0] VGA_R,
+	output reg [7:0] VGA_G,
+	output reg [7:0] VGA_B,
+	output reg       VGA_VS,
+	output reg       VGA_HS,
+	output reg       VGA_DE
+);
+
+localparam DWIDTH = HALF_DEPTH ? 3 : 7;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.hb_in(HBlank),
+	.vb_in(VBlank),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.ce_pix_out(ce_pix_sd),
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.hb_out(hb_sd),
+	.vb_out(vb_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler ? R_sd : R);
+wire [DWIDTH:0] gt  = (scandoubler ? G_sd : G);
+wire [DWIDTH:0] bt  = (scandoubler ? B_sd : B);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [7:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [7:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [7:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [7:0] r  = rt;
+		wire [7:0] g  = gt;
+		wire [7:0] b  = bt;
+	end
+endgenerate
+
+wire hs = (scandoubler ? hs_sd : HSync);
+wire vs = (scandoubler ? vs_sd : VSync);
+
+assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
+
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire hde = scandoubler ? ~hb_sd : ~HBlank;
+wire vde = scandoubler ? ~vb_sd : ~VBlank;
+
+always @(posedge clk_sys) begin
+	reg old_hde;
+
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
+			VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
+			VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			VGA_R <= {1'b0, r[7:1]};
+			VGA_G <= {1'b0, g[7:1]};
+			VGA_B <= {1'b0, b[7:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			VGA_R <= {2'b00, r[7:2]};
+			VGA_G <= {2'b00, g[7:2]};
+			VGA_B <= {2'b00, b[7:2]};
+		end
+
+		default: begin
+			VGA_R <= r;
+			VGA_G <= g;
+			VGA_B <= b;
+		end
+	endcase
+
+	VGA_VS <= vs;
+	VGA_HS <= hs;
+
+	old_hde <= hde;
+	if(~old_hde && hde) VGA_DE <= vde;
+	if(old_hde && ~hde) VGA_DE <= 0;
+end
+
+endmodule