mirror of
https://github.com/MiSTer-devel/Arcade-Pacman_MiSTer.git
synced 2026-05-24 03:02:12 +00:00
Simplify input.
This commit is contained in:
sorgelig
@@ -161,8 +161,10 @@ wire [7:0] ioctl_dout;
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wire [10:0] ps2_key;
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wire [15:0] joy1;
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wire [15:0] joy2;
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wire [15:0] joy1 = mod_club ? joy1a : (joy1a | joy2a);
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wire [15:0] joy2 = mod_club ? joy2a : (joy1a | joy2a);
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wire [15:0] joy1a;
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wire [15:0] joy2a;
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wire [21:0] gamma_bus;
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@@ -186,8 +188,8 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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.ioctl_dout(ioctl_dout),
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.ioctl_index(ioctl_index),
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.joystick_0(joy1),
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.joystick_1(joy2),
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.joystick_0(joy1a),
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.joystick_1(joy2a),
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.ps2_key(ps2_key)
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);
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@@ -359,19 +361,16 @@ pacman pacman
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.O_AUDIO(audio),
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.in0_reg(~{1'b0,1'b0, m_coin, m_cheat}),
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.in1_reg(~{mod_gm ? m_fire_2 : status[12], m_start_2, m_start, mod_gm & m_fire, {m_down,m_right,m_left,m_up} | {m_down_2,m_right_2,m_left_2,m_up_2}}),
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.dipsw_reg(mod_crush ? m_dip_cr : mod_bird ? m_dip_b : mod_gm ? m_dip_gm : m_dip),
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.in0(~{1'b0, 1'b0, m_coin, m_cheat, m_down, m_right, m_left, m_up }),
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.in1(~{mod_gm ? m_fire_2 : status[12], m_start_2, m_start, mod_gm & m_fire, m_down_2,m_right_2,m_left_2,m_up_2}),
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.dipsw(mod_crush ? m_dip_cr : mod_bird ? m_dip_b : mod_gm ? m_dip_gm : m_dip),
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.mod_plus(mod_plus),
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.mod_bird(mod_bird),
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.mod_ms(mod_ms),
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.mod_mrtnt(mod_mrtnt),
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.in_a({m_down,m_right,m_left,m_up} | (mod_club ? 4'b0000 : {m_down_2,m_right_2,m_left_2,m_up_2})),
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.in_b(mod_club ? {m_down_2,m_right_2,m_left_2,m_up_2} : {m_down,m_right,m_left,m_up}),
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.RESET(RESET | status[0] | buttons[1]|ioctl_download),
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.RESET(RESET | status[0] | buttons[1] | ioctl_download),
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.CLK(clk_sys),
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.ENA_6(ce_6m)
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);
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@@ -64,18 +64,15 @@ port
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--
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O_AUDIO : out std_logic_vector(7 downto 0);
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--
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in0_reg : in std_logic_vector(3 downto 0);
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in1_reg : in std_logic_vector(7 downto 0);
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dipsw_reg : in std_logic_vector(7 downto 0);
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in0 : in std_logic_vector(7 downto 0);
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in1 : in std_logic_vector(7 downto 0);
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dipsw : in std_logic_vector(7 downto 0);
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--
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mod_plus : in std_logic;
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mod_bird : in std_logic;
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mod_mrtnt : in std_logic;
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mod_ms : in std_logic;
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--
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in_a : in std_logic_vector(3 downto 0);
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in_b : in std_logic_vector(3 downto 0);
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--
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dn_addr : in std_logic_vector(15 downto 0);
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dn_data : in std_logic_vector(7 downto 0);
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dn_wr : in std_logic;
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@@ -526,13 +523,13 @@ begin
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end if;
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end process;
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inj <= not in_a when control_reg(5 downto 4) = "01" else
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not in_b when control_reg(5 downto 4) = "10" else
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not (in_a or in_b);
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inj <= in0(3 downto 0) when control_reg(5 downto 4) = "01" else
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in1(3 downto 0) when control_reg(5 downto 4) = "10" else
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in0(3 downto 0) and in1(3 downto 0);
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p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l,
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iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data,
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rams_data_out, in0_reg, in1_reg, dipsw_reg, inj, iodec_dipsw2_l)
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rams_data_out, in0, in1, dipsw, inj, iodec_dipsw2_l)
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begin
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-- simplifed again
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if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then
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@@ -544,41 +541,40 @@ begin
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cpu_data_in <= rom_data;
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else
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cpu_data_in <= rams_data_out;
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if (iodec_in0_l = '0') then cpu_data_in <= in0_reg & inj; end if;
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if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if;
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if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if;
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if (iodec_in0_l = '0') then cpu_data_in <= in0(7 downto 4) & inj; end if;
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if (iodec_in1_l = '0') then cpu_data_in <= in1; end if;
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if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw; end if;
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if (iodec_dipsw2_l= '0') then cpu_data_in <= x"FF"; end if;
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end if;
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end if;
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end process;
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u_rams : work.dpram generic map (12,8)
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port map
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(
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clock_a => clk,
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enable_a => ena_6,
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wren_a => not sync_bus_r_w_l and not vram_l,
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address_a => ab(11 downto 0),
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data_a => cpu_data_out, -- cpu only source of ram data
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clock_b => clk,
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address_b => ab(11 downto 0),
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q_b => rams_data_out
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);
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u_program_rom: work.rom_descrambler
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port map(
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CLK => clk,
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MRTNT => mod_mrtnt,
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MSPACMAN => mod_ms,
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PLUS => mod_plus,
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cpu_m1_l => cpu_m1_l,
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addr => cpu_addr,
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data => rom_data,
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dn_addr => dn_addr,
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dn_data => dn_data,
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dn_wr => dn_wr
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);
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u_rams : work.dpram generic map (12,8)
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port map
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(
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clock_a => clk,
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enable_a => ena_6,
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wren_a => not sync_bus_r_w_l and not vram_l,
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address_a => ab(11 downto 0),
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data_a => cpu_data_out, -- cpu only source of ram data
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clock_b => clk,
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address_b => ab(11 downto 0),
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q_b => rams_data_out
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);
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u_program_rom: work.rom_descrambler
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port map(
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CLK => clk,
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MRTNT => mod_mrtnt,
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MSPACMAN => mod_ms,
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PLUS => mod_plus,
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cpu_m1_l => cpu_m1_l,
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addr => cpu_addr,
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data => rom_data,
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dn_addr => dn_addr,
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dn_data => dn_data,
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dn_wr => dn_wr
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);
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--
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-- video subsystem
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