Removed independent out of phase sprite clock

2026-05-17 03:02:06 +00:00 · 2023-03-25 17:16:33 -05:00
parent 848322f72c
commit beabfbb698
5 changed files with 46 additions and 167 deletions
--- a/Arcade-Exerion.sv
+++ b/Arcade-Exerion.sv
@@ -327,17 +327,7 @@ hps_io #(.CONF_STR(CONF_STR)) hps_io
 	.ioctl_index(ioctl_index),
 	.ioctl_wait(ioctl_wait),

-	//SD RAM implementation?
 	.sdram_sz(sdram_sz),
-	//.sd_lba(sd_lba),
-	//.sd_rd(sd_rd),
-	//.sd_wr(sd_wr),
-	//.sd_ack(sd_ack),
-	//.sd_buff_addr(sd_buff_addr),
-	//.sd_buff_dout(sd_buff_dout),
-	//.sd_buff_din(sd_buff_din),
-	//.sd_buff_wr(sd_buff_wr),
-
 	.joystick_0(joystick_0)
 );

@@ -352,10 +342,10 @@ wire clk_vid;//=clkm_20MHZ;
 pll pll(
 		.refclk(CLK_50M),  			// refclk.clk FPGA_CLK1_50
 		.rst(0),            			// reset.reset
-		.outclk_0(clkm_20MHZ),     // outclk0.clk
-		.outclk_1(clk_vid),        // outclk1.clk
-		.outclk_2(clk_53p28),			// outclk2.clk
-		.outclk_3(clkSP_20MHz)
+		.outclk_0(clkm_20MHZ),     // outclk0.clk = 20Mhz
+		.outclk_1(clk_vid),        // outclk1.clk = 40Mhz
+		.outclk_2(clk_53p28),		// outclk2.clk = 53.28Mhz
+		.outclk_3()
 );

 wire m_right  		= joystick_0[0];
@@ -374,7 +364,6 @@ wire m_pause  		= joystick_0[9];
 always @(posedge clk_vid) begin
 	reg [1:0] div;
 	div <= div + (forced_scandoubler ? 2'd1 : 2'd2);
-	//ce_pix <= !div;
 end

 ///////////////////   VIDEO   ////////////////////
@@ -384,7 +373,7 @@ wire hs, vs;
 wire [2:0] r;
 wire [2:0] g;
 wire [1:0] b;
-//wire [7:0] rgb = {r[2:0],g[2:0],b[1:0]};//23:0
+
 wire [7:0] rgb = {rgb_out[7:5],rgb_out[4:2],rgb_out[1:0]};//23:0

 wire no_rotate = status[2] | direct_video;
@@ -458,7 +447,6 @@ assign LED_USER = ioctl_download;

 exerion_fpga excore(
 	.clkm_20MHZ(clkm_20MHZ),
-	.clkSP_20MHz(clkSP_20MHz),
 	.clkaudio(clk_53p28),
 	.RED(r),
 	.GREEN(g),
--- a/rtl/excore.v
+++ b/rtl/excore.v
@@ -14,7 +14,6 @@

 module exerion_fpga(
 	input clkm_20MHZ,
-	input clkSP_20MHz,
 	input	clkaudio,
 	output [2:0] RED,     	//from fpga core to sv
 	output [2:0] GREEN,		//from fpga core to sv
@@ -32,7 +31,7 @@ module exerion_fpga(
 	input [24:0] dn_addr,
 	input 		 dn_wr,
 	input [7:0]  dn_data,
-	output [15:0] audio_l, //from jt49_1 .sound
+	output [15:0] audio_l,  //from jt49_1 .sound
 	output [15:0] audio_r,  //from jt49_2 .sound
 	input [15:0] hs_address,
 	output [7:0] hs_data_out,
@@ -43,8 +42,6 @@ module exerion_fpga(
 //pixel counters
 reg [8:0] pixH = 9'b000000000;
 reg [7:0] pixV = 8'b00000000;
-//reg [8:0] pixH = 9'b000000000;
-//reg [7:0] pixV = 8'b00000000;

 wire [8:0] rpixelbusH;
 wire [7:0] rpixelbusV;
@@ -67,8 +64,7 @@ wire 	ic2b_1q;
 wire 	ic2b_2nq;
 wire 	clk_phase2;

-wire clk1_10MHZ,clk2_6MHZ,clk2_6AMHZ,clk3_3MHZ,clk4_6BMHZ;
-wire spclk1_10MHZ,spclk2_6MHZ,spclk3_3MHZ,spclk4_6BMHZ;
+wire clk1_10MHZ,clk2_6MHZ,clk2_6AMHZ,clk3_3MHZ;

 wire PUR = 1'b1;
 wire H4CA;
@@ -91,64 +87,13 @@ wire [15:0] Z80B_addrbus;
 wire [7:0] Z80B_databus_in;
 wire [7:0] Z80B_databus_out;

-//duplicate clocks for each layer
-//tile & main CPU clock
+
+//clocks
 wire U2A_Aq,U2A_Anq,U2A_Aqi;
 wire U2A_Bq,U2A_Bnq,U2A_Bqi;
 wire U2B_Aq,U2B_Anq,U2B_Aqi;
 wire U2B_Bq,U2B_Bnq,U2B_Bqi;

-//background
-wire U3A_Aq,U3A_Anq,U3A_Aqi;
-wire U3A_Bq,U3A_Bnq,U3A_Bqi;
-wire U3B_Aq,U3B_Anq,U3B_Aqi;
-wire U3B_Bq,U3B_Bnq,U3B_Bqi;
-
-//sprites
-wire spU2A_Aq,spU2A_Anq,spU2A_Aqi;
-wire spU2A_Bq,spU2A_Bnq,spU2A_Bqi;
-wire spU2B_Aq,spU2B_Anq,spU2B_Aqi;
-
-/*ls107 spU2A_B(
-   .clear(PUR), 
-   .clk(clkSP_20MHz), 
-   .j(spU2A_Anq|!PUR), 
-   .k(spU2A_Anq|!PUR), 
-   .q(spU2A_Bq), 
-   .qnot(spU2A_Bnq),
-	.q_immediate(spU2A_Bqi)
-);
-
-ls107 spU2A_A(
-   .clear(PUR), 
-   .clk(clkSP_20MHz), 
-   .j(spU2A_Bq), 
-   .k(PUR), 
-   .q(spU2A_Aq), 
-   .qnot(spU2A_Anq),
-	.q_immediate(spU2A_Aqi)
-);
-
-
-ls107 spU2B_A(
-   .clear(PUR), 
-   .clk(clkSP_20MHz), 
-   .j(PUR), 
-   .k(PUR), 
-   .q(spU2B_Aq), 
-   .qnot(spU2B_Anq),
-	.q_immediate(spU2B_Aqi)
-);
-
-buf (spclk1_10MHZ,spU2B_Aq);
-not (spclk2_6MHZ,spU2A_Aq);
-buf (spclk4_6BMHZ,spU2A_Bq);
-*/
-
-buf (spclk1_10MHZ,U2B_Aq);
-not (spclk2_6MHZ,U2A_Aq);
-buf (spclk4_6BMHZ,U2A_Bq);
-
 ls107 U2A_B(
   .clear(PUR), 
   .clk(clkm_20MHZ), 
@@ -189,18 +134,14 @@ ls107 U2B_A(
 	.q_immediate(U2B_Aqi)
 );

-buf (clk1_10MHZ,U2B_Aq);
-not (clk2_6MHZ,U2A_Aq);
-buf (clk3_3MHZ,U2B_Bnq);
-buf (clk4_6BMHZ,U2A_Bq);
-
+buf (clk1_10MHZ,U2B_Aq);  	//10MHz Clock
+not (clk2_6MHZ,U2A_Aq);		//6.66Mhz Clock
+buf (clk3_3MHZ,U2B_Bnq);	//3.33Mhz Clock

 wire Z80_MREQ,Z80_WR,Z80_RD;
 wire Z80B_MREQ,Z80B_WR,Z80B_RD;
 reg Z80_DO_En;

-//wire clk2_6MHZ, clk3_3MHZ;
-//wire clk2_6MHZ_1,clk2_6MHZ_2;
 //coin input
 wire nCOIN;

@@ -598,7 +539,7 @@ wire [3:0] ZC;

 //select layer with priority

- always @(posedge spclk2_6MHZ) begin
+ always @(posedge clk2_6MHZ) begin
 	//equivalent of VID_B.  If the 5th bit is used the upper part of the pallet ROM is
 	//utilized and the sprite layer is selected.
 	sp_clr_addr <= (ZB[3:0]) 		? 	{1'b1,ZB[3:0]}	: 5'b00000;
@@ -633,8 +574,6 @@ prom6331_E1 UE1(
 	.q({BLUE,GREEN,RED})
 );

-reg rVGA_HS;
-reg rVGA_VS;
 wire rSSEL;

 wire r2UP; //flips the screen - removed logic to help with debugging
@@ -659,32 +598,11 @@ reg [7:0] Z80A_IO2;

 always @(posedge IO2) Z80A_IO2 = Z80A_databus_out;

-/*
-wire [8:0] pixHcntz;
-wire [7:0] pixVcntz;
-assign pixHcntz=pixH+9'd1;
-assign pixVcntz=pixV+8'd1;
-
-always @(posedge spclk2_6MHZ) begin
-
-	//simplified pixel clock counter. The horizontal counts from 88 to 511, the vertical counts from 0 to 255
-	if (pixH==9'b111111111) 
-	begin
-		pixH <= 9'b00101100z;
-		pixV <= pixVcntz;//pixVcnt+1;
-	end
-	else pixH <= pixHcntz;
-
-end
-*/
-
 reg spnH4CA,spnH8CA;
 assign pixHcntz=pixH+9'd1;
 assign pixVcntz=pixV+8'd1;

 always @(posedge clk2_6MHZ) begin
-
-	
 	//simplified pixel clock counter. The horizontal counts from 88 to 511, the vertical counts from 0 to 255
 	if (pixH==9'b111111111) 
 	begin
@@ -693,11 +611,8 @@ always @(posedge clk2_6MHZ) begin
 	end
 	else pixH <= pixHcntz;

-	rVGA_HS <= !U9R_Q5;							//horizontal sync
-	rVGA_VS <= ((!(&pixV[7:3]))|pixV[2]); 	//vertical sync
 	spnH4CA<=~&pixH[4:1];
 	spnH8CA<=~&pixH[8:5];
-	
 end

 assign	rSSEL = U9R_Q4|nVDSP;  //used to load the per line memory location for the background layer 
@@ -755,7 +670,7 @@ wire [7:0] sprom_data;
 eprom_5 prom_SPRITE
 (
 	.ADDR({CHDN,CHLF,sROM_A11,sROM_A10,sROM_A9,sum4,sum3,sum2,sum1,sROM_A4,sROM_A3,sROM_A2,sROM_A1,sROM_A0}),//
-	.CLK(clkm_20MHZ),//clkSP_20MHz
+	.CLK(clkm_20MHZ),//
 	.DATA(sprom_data),//
 	.ADDR_DL(dn_addr),
 	.CLK_DL(clkm_20MHZ),//
@@ -803,9 +718,9 @@ wire U9H_d;
 assign U9H_d = U11J_2|U11J_1;


-always @(posedge spclk1_10MHZ) U9H_A_nq <= 	~U9H_d;
+always @(posedge clk1_10MHZ) U9H_A_nq <= 	~U9H_d;

-always @(posedge spclk1_10MHZ) begin
+always @(posedge clk1_10MHZ) begin
 	spbitdata_11 <= (pixV[0]) ? 4'b0000 : U10H_data;
 	spbitdata_10 <= (pixV[0]) ? U10H_data :4'b0000 ;
 end
@@ -866,36 +781,18 @@ reg sp10_UD,sp10_nLD,sp10_CK,sp10_WE;
 reg sp11_UD,sp11_nLD,sp11_CK,sp11_WE;

 //sprite ram bit selection logic - U11E feeds the _10 bus
-//always @(posedge clkm_20MHZ) begin

-//	if (pixV[0]) 
-//	begin
 always @(*) begin
-		sp10_WE  <= pixV[0] ? (spclk1_10MHZ|U9H_A_nq|U9F_A_q) : spclk2_6MHZ;
-		sp10_CK  <= pixV[0] ? (spclk1_10MHZ|U9F_B_nq|U9F_A_q) : spclk2_6MHZ;
+		sp10_WE  <= pixV[0] ? (clk1_10MHZ|U9H_A_nq|U9F_A_q) : clk2_6MHZ;
+		sp10_CK  <= pixV[0] ? (clk1_10MHZ|U9F_B_nq|U9F_A_q) : clk2_6MHZ;
 		sp10_nLD <= pixV[0] ? U10nRCO : 1'b1;
-		sp11_WE  <= pixV[0] ? spclk2_6MHZ : (spclk1_10MHZ|U9H_A_nq|U9F_A_q);
-		sp11_CK  <= pixV[0] ? spclk2_6MHZ : (spclk1_10MHZ|U9F_B_nq|U9F_A_q);
+		sp11_WE  <= pixV[0] ? clk2_6MHZ : (clk1_10MHZ|U9H_A_nq|U9F_A_q);
+		sp11_CK  <= pixV[0] ? clk2_6MHZ : (clk1_10MHZ|U9F_B_nq|U9F_A_q);
 		sp11_nLD <= pixV[0] ? 1'b1 : U10nRCO;

 		sp10_UD  <= 1'b1; //( rpixelbusV[0])  ? 1'b1 : nr2UP;
 		sp11_UD  <= 1'b1; //(!rpixelbusV[0])  ? 1'b1 : nr2UP;		
 end
-//	end
-//	else
-//	begin
-//		sp10_WE  <= spclk2_6MHZ;
-//		sp10_CK  <= spclk2_6MHZ;
-//		sp10_nLD <= 1'b1;
-//		sp11_WE  <= (spclk1_10MHZ|U9H_A_nq|U9F_A_q);
-//		sp11_CK  <= (spclk1_10MHZ|U9F_B_nq|U9F_A_q);
-//		sp11_nLD <= U10nRCO;
-
-//		sp10_UD  <= 1'b1; //( rpixelbusV[0])  ? 1'b1 : nr2UP;
-//		sp11_UD  <= 1'b1; //(!rpixelbusV[0])  ? 1'b1 : nr2UP;			
-//	end
-//end
-

 reg [8:0] spramaddrb_10_cnt;
 reg [8:0] spramaddrb_10_up;
@@ -911,9 +808,9 @@ always @(posedge sp11_CK) spramaddrb_11_cnt = spramaddrb_11_up;
 wire [3:0] spram_out_10;
 wire [3:0] spram_out_11;

-always @(posedge spclk2_6MHZ) {ZB} <= (pixV[0]) ? {spram_out_11} : {spram_out_10}; //U9A
+always @(posedge clk2_6MHZ) {ZB} <= (pixV[0]) ? {spram_out_11} : {spram_out_10}; //U9A

-always @(negedge spclk1_10MHZ) begin
+always @(negedge clk1_10MHZ) begin
 	U10nRCO<=!(spramaddr_cnt[0]&spramaddr_cnt[1]&spramaddr_cnt[2]&spramaddr_cnt[3]);
 end

@@ -921,14 +818,14 @@ wire P4,P3,P2,P1;
 wire U10U_Q4,U10U_Q5,U10U_Q6,U10U_Q7;

 ls138x U10U( //#(.WIDTH_OUT(8), .DELAY_RISE(0), .DELAY_FALL(0)) 
-  .nE1(spclk1_10MHZ), //
+  .nE1(clk1_10MHZ), //
  .nE2(spramaddr_cnt[0]), //
  .E3(spramaddr_cnt[1]), //
  .A({1'b0,spramaddr_cnt[3:2]}), //
  .Y({U10U_Q7,U10U_Q6,U10U_Q5,U10U_Q4,P4,P3,P2,P1})
 );

-always @(posedge spclk1_10MHZ) begin
+always @(posedge clk1_10MHZ) begin

 //U11H     - 161 counter that increments on the 10Mhz clock and is reset to 0 by P4, this can be a simple add counter
 //U10J     - Takes the output of U11H and switches the output based on signal 'BIG2'
@@ -1405,8 +1302,7 @@ m2511_ram_4 sprites_11(
 );

 //  ****** FINAL 7-BIT ANALOGUE OUTPUT *******
-
-assign H_SYNC = rVGA_HS;
-assign V_SYNC = rVGA_VS;
+assign	H_SYNC = !U9R_Q5;								//horizontal sync
+assign	V_SYNC = ((!(&pixV[7:3]))|pixV[2]); 	//vertical sync

 endmodule
--- a/rtl/pll.qip
+++ b/rtl/pll.qip
@@ -35,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MTM=::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTkuOTY4::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Mjg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzIzODA2MTc0NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NzI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MjUxMTAwOTY4MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MTAuMDc5OTk5IE1Ieg==::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MTI1MDAw::UGhhc2UgU2hpZnQ="
@@ -55,9 +55,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NDAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MTA=::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::Mjg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MzIzODA2MTc0NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MzY=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MjUxMTAwOTY4MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
@@ -67,9 +67,9 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTMuMjg=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::Mjg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MzIzODA2MTc0NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::Mjc=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::OQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MjUxMTAwOTY4MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::OQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
@@ -265,8 +265,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTMuMjQ4MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MTkuOTY4MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::Mzg5NTEgcHM=::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
@@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTQsMTQsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDM2LDM2LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDE4LDE4LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDE0LDEzLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMzYsMzYsNTcsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxNDM3LjY5NiBNSHosMzIzODA2MTc0NCxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDEyLDEyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDYsNiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSw1LDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDc5LjIzMiBNSHosMjUxMTAwOTY4MCxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
--- a/rtl/pll.v
+++ b/rtl/pll.v
@@ -11,7 +11,6 @@ module pll (
 		output wire  outclk_0, // outclk0.clk
 		output wire  outclk_1, // outclk1.clk
 		output wire  outclk_2, // outclk2.clk
-		output wire  outclk_3, // outclk3.clk
 		output wire  locked    //  locked.export
 	);

@@ -21,7 +20,6 @@ module pll (
 		.outclk_0 (outclk_0), // outclk0.clk
 		.outclk_1 (outclk_1), // outclk1.clk
 		.outclk_2 (outclk_2), // outclk2.clk
-		.outclk_3 (outclk_3), // outclk3.clk
 		.locked   (locked)    //  locked.export
 	);

@@ -67,7 +65,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
 // Retrieval info: 	<generic name="gui_use_locked" value="true" />
 // Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
-// Retrieval info: 	<generic name="gui_number_of_clocks" value="4" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="3" />
 // Retrieval info: 	<generic name="gui_multiply_factor" value="13" />
 // Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
 // Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
--- a/rtl/pll/pll_0002.v
+++ b/rtl/pll/pll_0002.v
@@ -16,9 +16,6 @@ module  pll_0002(
 	// interface 'outclk2'
 	output wire outclk_2,

-	// interface 'outclk3'
-	output wire outclk_3,
-
 	// interface 'locked'
 	output wire locked
 );
@@ -27,7 +24,7 @@ module  pll_0002(
 		.fractional_vco_multiplier("true"),
 		.reference_clock_frequency("50.0 MHz"),
 		.operation_mode("direct"),
-		.number_of_clocks(4),
+		.number_of_clocks(3),
 		.output_clock_frequency0("19.968000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
@@ -37,8 +34,8 @@ module  pll_0002(
 		.output_clock_frequency2("53.248000 MHz"),
 		.phase_shift2("0 ps"),
 		.duty_cycle2(50),
-		.output_clock_frequency3("19.968000 MHz"),
-		.phase_shift3("38951 ps"),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
 		.duty_cycle3(50),
 		.output_clock_frequency4("0 MHz"),
 		.phase_shift4("0 ps"),
@@ -86,7 +83,7 @@ module  pll_0002(
 		.pll_subtype("General")
 	) altera_pll_i (
 		.rst	(rst),
-		.outclk	({outclk_3, outclk_2, outclk_1, outclk_0}),
+		.outclk	({outclk_2, outclk_1, outclk_0}),
 		.locked	(locked),
 		.fboutclk	( ),
 		.fbclk	(1'b0),