mirror of
https://github.com/MiSTer-devel/Arcade-Blockade_MiSTer.git
synced 2026-05-17 03:01:45 +00:00
@@ -57,6 +57,7 @@ module emu
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input [11:0] HDMI_WIDTH,
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input [11:0] HDMI_HEIGHT,
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output HDMI_FREEZE,
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output HDMI_BLACKOUT,
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`ifdef MISTER_FB
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// Use framebuffer in DDRAM
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@@ -187,6 +188,7 @@ assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign VGA_DISABLE = 0;
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assign HDMI_FREEZE = 0;
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assign HDMI_BLACKOUT = 0;
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assign AUDIO_S = 1;
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assign AUDIO_MIX = 0;
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BIN
releases/Arcade-Blockade_20250105.rbf
Normal file
BIN
releases/Arcade-Blockade_20250105.rbf
Normal file
Binary file not shown.
@@ -222,6 +222,7 @@ ENTITY ascal IS
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vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp
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vrr : IN std_logic := '0';
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vrrmax : IN natural RANGE 0 TO 4095 := 0;
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swblack : IN std_logic := '0'; -- will output 3 black frame on every resolution switch
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-- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp
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format : IN unsigned(1 DOWNTO 0) :="01";
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@@ -510,6 +511,7 @@ ARCHITECTURE rtl OF ascal IS
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SIGNAL o_divrun : std_logic;
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SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0);
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SIGNAL o_vacptl : unsigned(1 DOWNTO 0);
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signal o_newres : integer range 0 to 3;
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-----------------------------------------------------------------------------
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FUNCTION shift_ishift(shift : unsigned(0 TO 119);
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@@ -1890,6 +1892,14 @@ BEGIN
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o_ivsize<=i_vrsize; -- <ASYNC>
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o_hdown<=i_hdown; -- <ASYNC>
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o_vdown<=i_vdown; -- <ASYNC>
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IF (o_newres > 0) then
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o_newres <= o_newres- 1;
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END IF;
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END IF;
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IF (swblack = '1' and o_fb_ena = '0' and (o_ihsize /= i_hrsize or o_ivsize /= i_vrsize)) then
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o_newres <= 3;
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END IF;
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-- Simultaneous change of input and output framebuffers
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@@ -2219,6 +2229,9 @@ BEGIN
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hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8),
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b=>o_fb_pal_dr(7 DOWNTO 0));
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END IF;
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IF (o_newres > 0) then
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hpix_v := (others => (others => '0'));
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END IF;
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o_hpix0<=hpix_v;
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o_hpix1<=o_hpix0;
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o_hpix2<=o_hpix1;
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@@ -27,7 +27,7 @@
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// VDNUM 1..10
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// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
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//
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module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
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module hps_io #(parameter CONF_STR, CONF_STR_BRAM=0, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0, STRLEN=$size(CONF_STR)>>3)
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(
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input clk_sys,
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inout [48:0] HPS_BUS,
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@@ -39,7 +39,7 @@ module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1,
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output reg [31:0] joystick_3,
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output reg [31:0] joystick_4,
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output reg [31:0] joystick_5,
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// analog -127..+127, Y: [15:8], X: [7:0]
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output reg [15:0] joystick_l_analog_0,
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output reg [15:0] joystick_l_analog_1,
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@@ -232,7 +232,6 @@ video_calc video_calc
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/////////////////////////////////////////////////////////
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localparam STRLEN = $size(CONF_STR)>>3;
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localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1;
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wire [7:0] conf_byte;
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@@ -281,7 +280,7 @@ always@(posedge clk_sys) begin : uio_block
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stflg <= stflg + 1'd1;
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status_req <= status_in;
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end
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old_upload_req <= ioctl_upload_req;
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if(~old_upload_req & ioctl_upload_req) upload_req <= 1;
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@@ -523,7 +522,7 @@ always@(posedge clk_sys) begin : uio_block
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//menu mask
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'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
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//sdram size set
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'h31: if(byte_cnt == 1) sdram_sz <= io_din;
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@@ -630,7 +629,7 @@ always@(posedge clk_sys) begin : fio_block
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reg has_cmd;
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reg [26:0] addr;
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reg wr;
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ioctl_rd <= 0;
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ioctl_wr <= wr;
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wr <= 0;
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@@ -663,7 +662,7 @@ always@(posedge clk_sys) begin : fio_block
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FIO_FILE_TX:
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begin
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cnt <= cnt + 1'd1;
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case(cnt)
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case(cnt)
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0: if(io_din[7:0] == 8'hAA) begin
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ioctl_addr <= 0;
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ioctl_upload <= 1;
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@@ -1032,8 +1031,15 @@ module confstr_rom #(parameter CONF_STR, STRLEN)
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output reg [7:0] conf_byte
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);
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wire [7:0] rom[STRLEN];
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initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
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reg [7:0] rom[STRLEN];
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initial begin
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if( CONF_STR=="" )
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$readmemh("cfgstr.hex",rom);
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else
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for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
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end
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always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
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endmodule
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@@ -75,7 +75,7 @@ always @(posedge CLK) begin
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END <= 0;
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rd <= READ;
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len <= I2C_WLEN;
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if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
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if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b1, 3'b011, 9'b111111111};
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else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
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SD_COUNTER <= 0;
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end else begin
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@@ -58,10 +58,10 @@ localparam DW = WIDE ? 15 : 7;
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localparam SZ = OCTAL ? 8 : 1;
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localparam SW = SZ-1;
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wire [7:0] DATA_TOKEN_CMD25 = 8'hfc;
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wire [7:0] STOP_TRAN = 8'hfd;
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wire [7:0] DATA_TOKEN = 8'hfe;
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wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
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localparam DATA_TOKEN_CMD25 = 8'hfc;
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localparam STOP_TRAN = 8'hfd;
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localparam DATA_TOKEN = 8'hfe;
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localparam WRITE_DATA_RESPONSE = 8'he5;
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// number of bytes to wait after a command before sending the reply
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localparam NCR = 5+3; // 5 bytes are required (command length)
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@@ -128,12 +128,13 @@ module sys_top
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wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD;
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`ifndef MISTER_DUAL_SDRAM
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assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF;
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wire sd_cd = SDCD_SPDIF & ~SW[2]; // SW[2]=ON workaround for faulty boards without SD card detect pin.
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assign SD_CD = mcp_en ? mcp_sdcd : sd_cd;
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assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0]));
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assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ;
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assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK;
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assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI;
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assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
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assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | sd_cd) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
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`else
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assign SD_CD = mcp_sdcd;
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assign SD_MISO = mcp_sdcd | SD_SPI_MISO;
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@@ -183,10 +184,10 @@ wire io_dig = mcp_en ? mcp_mode : SW[3];
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assign LED_USER = VGA_TX_CLK;
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wire BTN_DIS = VGA_EN;
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`else
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wire BTN_RESET = SDRAM2_DQ[9];
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wire BTN_OSD = SDRAM2_DQ[13];
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wire BTN_USER = SDRAM2_DQ[11];
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wire BTN_DIS = SDRAM2_DQ[15];
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wire BTN_RESET = 1'b1;
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wire BTN_OSD = 1'b1;
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wire BTN_USER = 1'b1;
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wire BTN_DIS = 1'b1;
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`endif
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reg BTN_EN = 0;
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@@ -331,6 +332,7 @@ reg [11:0] vs_line = 0;
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reg scaler_out = 0;
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reg vrr_mode = 0;
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wire hdmi_blackout;
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reg [31:0] aflt_rate = 7056000;
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reg [39:0] acx = 4258969;
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@@ -752,6 +754,7 @@ wire freeze;
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.vmax (vmax),
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.vrr (vrr_mode),
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.vrrmax (HEIGHT + VBP + VS[11:0] + 12'd1),
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.swblack (hdmi_blackout),
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.mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}),
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.poly_clk (clk_sys),
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@@ -1734,6 +1737,7 @@ emu emu
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.HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width),
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.HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height),
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.HDMI_FREEZE(freeze),
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.HDMI_BLACKOUT(hdmi_blackout),
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.CLK_VIDEO(clk_vid),
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.CE_PIXEL(ce_pix),
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@@ -26,6 +26,10 @@ module video_cleaner
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//optional de
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input DE_in,
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//optional interlace support
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input interlace,
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input f1,
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// video output signals
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output reg [7:0] VGA_R,
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output reg [7:0] VGA_G,
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@@ -56,14 +60,19 @@ always @(posedge clk_vid) begin
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HBlank_out <= hbl;
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VGA_HS <= hs;
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if(~VGA_HS & hs) VGA_VS <= vs;
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VGA_R <= R;
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VGA_G <= G;
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VGA_B <= B;
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DE_out <= DE_in;
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if(HBlank_out & ~hbl) VBlank_out <= vbl;
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if (interlace & f1) begin
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VGA_VS <= vs;
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VBlank_out <= vbl;
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end else begin
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if(~VGA_HS & hs) VGA_VS <= vs;
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if(HBlank_out & ~hbl) VBlank_out <= vbl;
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end
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end
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end
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