Working controls!

2026-05-17 03:01:45 +00:00 · 2022-01-28 17:51:35 +00:00
parent debba00f31
commit 1bdd1cd68c
4 changed files with 74 additions and 75 deletions
--- a/Arcade-Blockade.sv
+++ b/Arcade-Blockade.sv
@@ -233,6 +233,7 @@ wire [31:0] status;
 wire  [1:0] buttons;
 wire        forced_scandoubler;
 wire        direct_video;
+wire [21:0] gamma_bus;

 wire        ioctl_download;
 wire        ioctl_upload;
@@ -244,10 +245,6 @@ wire  [7:0] ioctl_index;
 wire        ioctl_wait;

 wire [15:0] joystick_0, joystick_1;
-wire [15:0] joy = joystick_0 | joystick_1;
-
-wire [21:0] gamma_bus;
-

 hps_io #(.CONF_STR(CONF_STR)) hps_io
 (
@@ -277,23 +274,25 @@ hps_io #(.CONF_STR(CONF_STR)) hps_io
 );

 ///////////////////   CONTROLS   ////////////////////
-wire m_up     = joy[3];
-wire m_down   = joy[2];
-wire m_left   = joy[1];
-wire m_right  = joy[0];
-wire m_coin  = joy[4];
+wire p1_right = joystick_0[0];
+wire p1_left = joystick_0[1];
+wire p1_down = joystick_0[2];
+wire p1_up = joystick_0[3];
+wire p2_right = joystick_1[0];
+wire p2_left = joystick_1[1];
+wire p2_down = joystick_1[2];
+wire p2_up = joystick_1[3];
+wire btn_coin = joystick_0[4] || joystick_1[4];

 ///////////////////   INPUTS   ////////////////////
-wire [7:0] IN0 = 8'hFF;
-wire [7:0] IN1 = 8'hFF;
-wire [7:0] IN2 = 8'hFF;
-
+wire [7:0] IN0 = 8'hFF; // IN0 is unused in Blockade
+wire [7:0] IN1 = ~{btn_coin, 7'b0};
+wire [7:0] IN2 = ~{p2_left, p2_down, p2_right, p2_up, p1_left, p1_down, p1_right, p1_up};

 ///////////////////   VIDEO   ////////////////////
 reg ce_pix;
 wire hblank, vblank, hs, vs, hs_original, vs_original;
 wire r, g, b;
-
 wire [23:0] rgb = {{8{r}},{8{g}},{8{b}}};

 arcade_video #(256,24) arcade_video
--- a/rtl/blockade.v
+++ b/rtl/blockade.v
@@ -41,13 +41,12 @@ assign ce_pix = (vid_count == 2'd3);
 wire PHI_1 = phi_count[3:1] == 3'b000;
 wire PHI_2 = phi_count >= 4'd3 && phi_count <= 4'd8;

-// U9 D flip-flop
-reg u9_q;
-reg PHI_2_last;
-
 // U21 - Video RAM address select
 wire a12_n_a15 = ADDR[15] && ~ADDR[12];

+// U9 D flip-flop - Disables CPU using READY signal when attempting to write VRAM during vblank
+reg u9_q;
+reg PHI_2_last;
 always @(posedge clk) begin
 	if(reset)
 	begin
@@ -55,6 +54,7 @@ always @(posedge clk) begin
 	end
 	else
 	begin
+		PHI_2_last <= PHI_2;
 		if(PHI_2 && !PHI_2_last)
 		begin
 			if(VBLANK_N && a12_n_a15)
@@ -67,29 +67,30 @@ end

 // Address decode
 wire rom_cs = (!ADDR[15] && !ADDR[11] && !ADDR[10]);
-wire ram_cs = ADDR[15] && !ADDR[12];
+wire vram_cs = ADDR[15] && !ADDR[12];
 wire sram_cs = ADDR[15] && ADDR[12];

-wire ram_we = ram_cs && !WR_N;
+// VRAM and static RAM write enables
+wire vram_we = vram_cs && !WR_N;
 wire sram_we = sram_cs && !WR_N;

-wire [7:0] inp_data_out =	(ADDR[1:0] == 2'd0) ? in0 : // IN0
+// Input data selector
+wire [7:0] inp_data_out =	(ADDR[1:0] == 2'd0) ? in0 : // IN0 - Not connected in Blockade
 							(ADDR[1:0] == 2'd1) ? in1 : // IN1
 							(ADDR[1:0] == 2'd2) ? in2 : // IN2
 							8'h00;

-// CPU
+// CPU data selector
 wire [7:0] cpu_data_in = INP ? inp_data_out :
 						 rom_cs ? rom_data_out :
-						 ram_cs ? ram_data_out :
+						 vram_cs ? vram_data_out_cpu :
 						 sram_cs ? sram_data_out :
 						 8'h00;

-reg [7:0] cpu_data_out;
-
 wire [15:0] ADDR;
 wire [7:0] DATA;
 wire DBIN;
+reg [7:0] cpu_data_out;
 wire WR_N;
 wire SYNC /*verilator public_flat*/;
 wire HLD_A;
@@ -127,10 +128,11 @@ localparam HBLANK_START = 9'd255;
 localparam HSYNC_START = 9'd272;
 localparam HSYNC_END = 9'd300;
 localparam HRESET_LINE = 9'd329;
+localparam VSYNC_START = 9'd256;
+localparam VSYNC_END = 9'd258;
 localparam VBLANK_START = 9'd224;
-localparam VSYNC_START = 9'd254;
-localparam VRESET_LINE = 9'd261;
 localparam VBLANK_END = 9'd261;
+localparam VRESET_LINE = 9'd261;

 // Counters
 reg [8:0] hcnt;
@@ -155,12 +157,11 @@ wire s_128V = vcnt[7];
 wire s_256V = vcnt[8];

 // Signals
-reg HBLANK_N_last = 1'b1;
 reg HBLANK_N = 1'b1;
-reg HSYNC_N_last = 1'b1;
 reg HSYNC_N = 1'b1;
+reg HSYNC_N_last = 1'b1;
 wire VBLANK_N = ~(vcnt >= VBLANK_START);
-wire VSYNC_N = ~(vcnt >= VSYNC_START);
+wire VSYNC_N = ~(vcnt >= VSYNC_START && vcnt <= VSYNC_END);

 // Video read addresses
 reg [2:0] prom_col;
@@ -285,8 +286,8 @@ dpram #(10,4, "316-0004.u2.hex") rom_msb
 	.q_b()
 );

-// U38, U39, U40, U41, U42 - 2102 - Video RAM
-wire [7:0] ram_data_out;
+// U38, U39, U40, U41, U42 - 2102 - Video RAM (dual-ported for simplicity)
+wire [7:0] vram_data_out_cpu;
 wire [7:0] vram_data_out;
 dpram #(10,8) ram
 (
@@ -298,21 +299,19 @@ dpram #(10,8) ram

 	.clock_b(clk),
 	.address_b(ADDR[9:0]),
-	.wren_b(ram_we),
+	.wren_b(vram_we),
 	.data_b(cpu_data_out),
-	.q_b(ram_data_out)
+	.q_b(vram_data_out_cpu)
 );

 // U6, U7 - 2111 - Static RAM
 wire [7:0]	sram_data_out;
-wire [7:0]	sram_data_in = cpu_data_out;
-wire [7:0]  sram_addr = ADDR[7:0];
 spram #(8,8) sram
 (
 	.clk(clk),
-	.address(sram_addr),
+	.address(ADDR[7:0]),
 	.wren(sram_we),
-	.data(sram_data_in),
+	.data(cpu_data_out),
 	.q(sram_data_out)
 );

--- a/verilator/sim.v
+++ b/verilator/sim.v
@@ -5,7 +5,7 @@ module emu(

   input clk_sys /*verilator public_flat*/,
   input reset/*verilator public_flat*/,
-   input [11:0]  inputs/*verilator public_flat*/,
+   input [8:0]  inputs/*verilator public_flat*/,

   input [7:0] IN0,
   input [7:0] IN1,
@@ -42,14 +42,16 @@ module emu(
   assign VGA_G = {8{GREEN}};
   assign VGA_B = {8{BLUE}};

-   wire btn_start = inputs[6];
+   // Inputs
+   wire p1_right = inputs[0];
+   wire p1_left = inputs[1];
+   wire p1_down = inputs[2];
+   wire p1_up = inputs[3];
+   wire p2_right = inputs[4];
+   wire p2_left = inputs[5];
+   wire p2_down = inputs[6];
+   wire p2_up = inputs[7];
   wire btn_coin = inputs[8];
-   wire m_bomb = inputs[5];
-   wire m_fire = inputs[4];
-   wire m_right = inputs[0];
-   wire m_left = inputs[1];
-   wire m_down = inputs[2];
-   wire m_up = inputs[3];

   blockade blockade (
      .clk(clk_sys),
@@ -60,8 +62,8 @@ module emu(
      .b(BLUE),
      //.buttons(~{btn_coin, btn_start, m_bomb, m_fire, m_right, m_left, m_down, m_up}),
      .in0(IN0),
-      .in1(IN1),
-      .in2(IN2),
+      .in1(~{btn_coin, 7'b0}), // Coin + DIPS?
+      .in2(~{p2_left, p2_down, p2_right, p2_up, p1_left, p1_down, p1_right, p1_up}), // Controls
      .hsync(VGA_HS),
      .vsync(VGA_VS),
      .hblank(VGA_HB),
--- a/verilator/sim_main.cpp
+++ b/verilator/sim_main.cpp
@@ -56,18 +56,18 @@ SimBus bus(console);
 // Input handling
 // --------------
 SimInput input(12, console);
-const int input_right = 0;
-const int input_left = 1;
-const int input_down = 2;
-const int input_up = 3;
-const int input_fire1 = 4;
-const int input_fire2 = 5;
-const int input_start_1 = 6;
-const int input_start_2 = 7;
+
+const int input_p1_right = 0;
+const int input_p1_left = 1;
+const int input_p1_down = 2;
+const int input_p1_up = 3;
+
+const int input_p2_right = 4;
+const int input_p2_left = 5;
+const int input_p2_down = 6;
+const int input_p2_up = 7;
+
 const int input_coin_1 = 8;
-const int input_coin_2 = 9;
-const int input_coin_3 = 10;
-const int input_pause = 11;

 // Video
 // -----
@@ -408,22 +408,20 @@ int main(int argc, char** argv, char** env)
 	// Set up input module
 	input.Initialise();
 #ifdef WIN32
-	input.SetMapping(input_up, DIK_UP);
-	input.SetMapping(input_right, DIK_RIGHT);
-	input.SetMapping(input_down, DIK_DOWN);
-	input.SetMapping(input_left, DIK_LEFT);
-	input.SetMapping(input_fire1, DIK_LCONTROL);
-	input.SetMapping(input_fire2, DIK_LALT);
-	input.SetMapping(input_start_1, DIK_1);
+	input.SetMapping(input_p1_up, DIK_UP);
+	input.SetMapping(input_p1_right, DIK_RIGHT);
+	input.SetMapping(input_p1_down, DIK_DOWN);
+	input.SetMapping(input_p1_left, DIK_LEFT);
+	input.SetMapping(input_p2_up, DIK_W);
+	input.SetMapping(input_p2_right, DIK_D);
+	input.SetMapping(input_p2_down, DIK_S);
+	input.SetMapping(input_p2_left, DIK_A);
 	input.SetMapping(input_coin_1, DIK_5);
 #else
 	input.SetMapping(input_up, SDL_SCANCODE_UP);
 	input.SetMapping(input_right, SDL_SCANCODE_RIGHT);
 	input.SetMapping(input_down, SDL_SCANCODE_DOWN);
 	input.SetMapping(input_left, SDL_SCANCODE_LEFT);
-	input.SetMapping(input_fire1, SDL_SCANCODE_LCONTROL);
-	input.SetMapping(input_fire2, SDL_SCANCODE_LALT);
-	input.SetMapping(input_start_1, SDL_SCANCODE_1);
 	input.SetMapping(input_coin_1, SDL_SCANCODE_3);
 #endif
 	// Setup video output
@@ -512,10 +510,10 @@ int main(int argc, char** argv, char** env)
 		ImGui::Text("main_time: %d frame_count: %d sim FPS: %f", main_time, video.count_frame, video.stats_fps);

 #ifdef DEBUG_AUDIO
-		//float vol_l = ((signed short)(top->AUDIO_L) / 256.0f) / 256.0f;
-		//float vol_r = ((signed short)(top->AUDIO_R) / 256.0f) / 256.0f;
-		//ImGui::ProgressBar(vol_l + 0.5, ImVec2(200, 16), 0); ImGui::SameLine();
-		//ImGui::ProgressBar(vol_r + 0.5, ImVec2(200, 16), 0);
+		float vol_l = ((signed short)(top->AUDIO_L) / 256.0f) / 256.0f;
+		float vol_r = ((signed short)(top->AUDIO_R) / 256.0f) / 256.0f;
+		ImGui::ProgressBar(vol_l + 0.5, ImVec2(200, 16), 0); ImGui::SameLine();
+		ImGui::ProgressBar(vol_r + 0.5, ImVec2(200, 16), 0);
 #endif

 		// Draw VGA output
@@ -553,8 +551,9 @@ int main(int argc, char** argv, char** env)
 			}
 		}

-		top->IN0 = 255 ^ ((input.inputs[input_start_1]) << 7);
-		top->IN1 = 0b11111111;
+		//top->IN0 = input.inputs[input_start_1] ? 0 : 255;
+		//top->IN1 = input.inputs[input_start_1] ? 0 : 255;
+		/*top->IN1 = 0b11111111;*/
 		top->IN2 = 255;

 		// Run simulation