Updates for m68k architecture.
This commit is contained in:
Philip Smart
127
build.sh
127
build.sh
@@ -1,7 +1,7 @@
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#!/bin/bash
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#========================================================================================================
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# NAME
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# build.sh - Shell script to build a ZPU/K64F program or OS.
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# build.sh - Shell script to build a ZPU/K64F/M68K program or OS.
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#
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# SYNOPSIS
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# build.sh [-CIOoMBAsTZdxh]
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@@ -9,7 +9,7 @@
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# DESCRIPTION
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#
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# OPTIONS
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# -C <CPU> = Small, Medium, Flex, Evo, EvoMin, K64F - defaults to Evo.
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# -C <CPU> = Small, Medium, Flex, Evo, EvoMin, K64F, M68K - defaults to Evo.
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# -I <iocp ver> = 0 - Full, 1 - Medium, 2 - Minimum, 3 - Tiny (bootstrap only)
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# -O <os> = zputa, zos
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# -o <os ver> = 0 - Standalone, 1 - As app with IOCP Bootloader,
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@@ -48,6 +48,7 @@
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# v1.21 : Additional changes to manage heap.
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# v1.22 : Added code to build the libraries.
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# v1.23 : Added flags for Sharp MZ series specific build.
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# v1.24 : Added M68000 support
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#========================================================================================================
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# This source file is free software: you can redistribute it and#or modify
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# it under the terms of the GNU General Public License as published
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@@ -295,11 +296,13 @@ OSNAME=`echo ${OS} | tr 'A-Z' 'a-z'`
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# -C <CPU> = Small, Medium, Flex, Evo, K64F - defaults to Evo.
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# Check the CPU is correctly defined.
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if [ "${CPU}" != "SMALL" -a "${CPU}" != "MEDIUM" -a "${CPU}" != "FLEX" -a "${CPU}" != "EVO" -a "${CPU}" != "EVOMIN" -a "${CPU}" != "K64F" ]; then
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FatalUsage "Given <cpu> is not valid, must be one of 'Small', 'Medium', 'Flex', 'Evo', 'K64F'"
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if [ "${CPU}" != "SMALL" -a "${CPU}" != "MEDIUM" -a "${CPU}" != "FLEX" -a "${CPU}" != "EVO" -a "${CPU}" != "EVOMIN" -a "${CPU}" != "K64F" -a "${CPU}" != "M68K" ]; then
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FatalUsage "Given <cpu> is not valid, must be one of 'Small', 'Medium', 'Flex', 'Evo', 'K64F', 'M68K'"
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fi
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if [ ${CPU} = "K64F" ]; then
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CPUTYPE="__K64F__"
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elif [ ${CPU} = "M68K" ]; then
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CPUTYPE="__M68K__"
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else
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CPUTYPE="__ZPU__"
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fi
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@@ -310,14 +313,18 @@ if [ "${CPU}" = "K64F" -a "${OS_BASEADDR}" = "0x00001000" -a "${APP_BASEADDR}" =
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getHex 0x1fff0000 APP_BASEADDR;
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fi
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# Check IOCP_VERSION which has no meaning for the K64F processor.
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# Check IOCP_VERSION which has no meaning for the K64F/M68K processors.
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if [ "${CPU}" = "K64F" -a "${IOCP_VERSION}" != "3" ]; then
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Fatal "-I < iocp ver> has no meaning for the K64F, there is no version or indeed no need for IOCP on this processor."
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elif [ "${CPU}" = "M68K" -a "${IOCP_VERSION}" != "3" ]; then
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Fatal "-I < iocp ver> has no meaning for the M68K, there is no version or indeed no need for IOCP on this processor."
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fi
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# Check OSVER which has no meaning for the K64F processor.
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# Check OSVER which has no meaning for the K64F/M68K processors.
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if [ "${CPU}" = "K64F" -a "${OSVER}" != "2" ]; then
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Fatal "-o <os ver> has no meaning for the K64F, base is in Flash RAM and applications, if SD card enabled, are in RAM."
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elif [ "${CPU}" = "M68K" -a "${OSVER}" != "2" ]; then
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Fatal "-o <os ver> has no meaning for the M68K, base is in Flash RAM and applications, if SD card enabled, are in RAM."
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fi
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# Setup any specific build options.
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@@ -329,10 +336,10 @@ fi
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# Setup any specific build options.
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if [ ${SHARPMZ} -eq 1 ]; then
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if [ "${CPU}" != "EVO" -o "${OS}" != "ZOS" ]; then
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if [[ "${CPU}" != "EVO" && "${CPU}" != "M68K" ]] || [[ "${OS}" != "ZOS" ]]; then
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Fatal "-Z only valid for zOS build on ZPU hardware."
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fi
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if [ "${CPU}" = "EVO" -a "${OS}" = "ZOS" ]; then
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if [[ "${CPU}" = "EVO" || "${CPU}" = "M68K" ]] && [[ "${OS}" = "ZOS" ]]; then
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BUILDFLAGS="__SHARPMZ__=1"
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fi
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fi
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@@ -345,8 +352,12 @@ mkdir -p ${BUILDPATH}/build/SD
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# Build message according to CPU Type
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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Log "Building: ${OS}, OS_BASEADDR=${OS_BASEADDR}, APP_BASEADDR=${APP_BASEADDR} ..."
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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Log "Building: ${OS} ..."
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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Log "Building: ${OS} ..."
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else
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Fatal "Internal error, unrecognised CPUTYPE at Build Info"
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fi
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# Stack start address (at the moment) is top of BRAM less 8 bytes (2 words), standard for the ZPU. There is
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@@ -435,7 +446,7 @@ if [ "${CPUTYPE}" = "__K64F__" ]; then
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OS_BASEADDR=0x000000;
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OS_BOOTLEN=0x000000;
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else
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elif [ "${CPUTYPE}" = "__ZPU__" ]; then
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if [ ${OSVER} = 0 ]; then
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OSBUILDSTR="${OSNAME}_standalone_boot_in_bram"
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OS_BOOTADDR=0x000000;
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@@ -456,6 +467,12 @@ else
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else
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FatalUsage "Illegal OS Version."
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fi
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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#OSBUILDSTR="${OSNAME}_m68k"
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OSBUILDSTR="${OSNAME}_standalone_boot_in_bram"
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OS_BOOTADDR=0x000000;
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OS_BASEADDR=0x000000;
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OS_BOOTLEN=0x000000;
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fi
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# For the ZPU, the start of the Boot loader, OS and application can change so need to calculate the Boot start and len, OS start and len, application Start and len.
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@@ -499,7 +516,9 @@ if [ "${CPUTYPE}" = "__ZPU__" ]; then
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# Calculate the heap start and end.
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subHex ${APP_STACK_STARTADDR} 4 APP_HEAP_ENDADDR
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subHex ${APP_HEAP_ENDADDR} ${APP_HEAP_SIZE} APP_HEAP_STARTADDR
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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# For the K64F the OS location and size is the 512K Flash RAM, this can be changed if a bootloader is installed before zOS.
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OS_STARTADDR=0x00000000
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addHex ${OS_STARTADDR} 0x00080000 OS_LEN
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@@ -537,6 +556,51 @@ else
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#subHex ${APP_STACK_STARTADDR} ${APP_STARTADDR} APP_STACK_STARTADDR
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# subHex ${APP_HEAP_STARTADDR} ${APP_STARTADDR} APP_HEAP_STARTADDR
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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# Calculate the Start address of the OS. The OS has a Boot Address followed by a reserved space for microcode and hooks before the main OS code.
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addHex ${OS_BOOTLEN} ${OS_BASEADDR} OS_STARTADDR
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# Calculate the Start address of the Application. An Application has a Boot Address, a reserved space for OS Hooks and then the application start.
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addHex ${APP_BOOTLEN} ${APP_BASEADDR} APP_STARTADDR
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# Calculate the maximum Application length by subtracting the size of the BRAM - Application Start - Stack Space
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if [ "${APP_LEN}" = "" -a $(( 16#`echo ${APP_STARTADDR} | tr 'a-z' 'A-Z'|sed 's/0X//g'` )) -lt $(( 16#`echo ${BRAM_SIZE} | tr 'a-z' 'A-Z'|sed 's/0X//g'` )) ]; then
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subHex ${BRAM_SIZE} ${APP_STARTADDR} APP_LEN
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subHex ${APP_LEN} 0x20 APP_LEN
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# If the APPLEN isnt set, give it a meaningful default.
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elif [ $(( 16#`echo ${APP_LEN} | tr 'a-z' 'A-Z'|sed 's/0X//g'` )) -eq 0 ]; then
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APP_LEN=0x10000;
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fi
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# Calculate the start of the Operating system code as the first section from the boot address is reserved.
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addHex ${OS_BOOTADDR} ${OS_BOOTLEN} OS_STARTADDR
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# Calculate the length of the OS which is the start address of the App less the Boot address of the OS.
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subHex ${APP_BASEADDR} ${OS_BOOTADDR} OS_LEN
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subHex ${OS_LEN} ${OS_BOOTLEN} OS_LEN
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# Calculate the heap and stack vars.
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subHex ${BRAM_SIZE} 8 OS_STACK_ENDADDR
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subHex ${OS_STACK_ENDADDR} ${OS_STACK_SIZE} OS_STACK_STARTADDR
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subHex ${OS_STACK_STARTADDR} 4 OS_HEAP_ENDADDR
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subHex ${OS_HEAP_ENDADDR} ${OS_HEAP_SIZE} OS_HEAP_STARTADDR
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# Stack start address for the APP. Normally this isnt used as the stack from zOS/ZPUTA is maintained, but available incase of
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# need for a local stack.
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addHex ${APP_STARTADDR} ${APP_LEN} APP_ENDADDR
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#subHex ${APP_ENDADDR} ${OS_STACK_SIZE} APP_ENDADDR
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subHex ${APP_ENDADDR} 8 APP_STACK_ENDADDR
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subHex ${APP_STACK_ENDADDR} ${APP_STACK_SIZE} APP_STACK_STARTADDR
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# Calculate the heap start and end.
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subHex ${APP_STACK_STARTADDR} 4 APP_HEAP_ENDADDR
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subHex ${APP_HEAP_ENDADDR} ${APP_HEAP_SIZE} APP_HEAP_STARTADDR
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else
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Fatal "Internal error, unrecognised CPUTYPE at calcblock"
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fi
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Debug "OS_BASEADDR=${OS_BASEADDR}, OS_BOOTLEN=${OS_BOOTLEN}, OS_STARTADDR=${OS_STARTADDR}, OS_LEN=${OS_LEN}"
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@@ -552,8 +616,12 @@ if [ "${OS}" = "ZPUTA" ]; then
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Log "ZPUTA - ${OSBUILDSTR}"
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zputa_zpu.tmpl
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else
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elif [ "${CPUTYPE}" = "__ZPU__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zputa_k64f.tmpl
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zputa_m68k.tmpl
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else
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Fatal "Internal error, unrecognised CPUTYPE at zputa cfg"
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fi
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cat ${TMPLFILE} | sed -e "s/BOOTADDR/${OS_BOOTADDR}/g" \
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-e "s/BOOTLEN/${OS_BOOTLEN}/g" \
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@@ -578,9 +646,14 @@ if [ "${OS}" = "ZPUTA" ]; then
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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Log "make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}"
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make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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Log "make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}"
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make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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Log "make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}"
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make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} ${BUILDFLAGS}
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else
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Fatal "Internal error, unrecognised CPUTYPE at ZPUTA Make"
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fi
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if [ $? != 0 ]; then
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Fatal "Aborting, failed to build ZPUTA!"
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@@ -593,8 +666,12 @@ elif [ "${OS}" = "ZOS" ]; then
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Log "zOS - ${OSBUILDSTR}"
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zos_zpu.tmpl
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zos_k64f.tmpl
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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TMPLFILE=${BUILDPATH}/startup/zos_m68k.tmpl
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else
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Fatal "Internal error, unrecognised CPUTYPE at zos cfg"
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fi
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cat ${TMPLFILE} | sed -e "s/BOOTADDR/${OS_BOOTADDR}/g" \
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-e "s/BOOTLEN/${OS_BOOTLEN}/g" \
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@@ -618,9 +695,15 @@ elif [ "${OS}" = "ZOS" ]; then
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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Log "make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}"
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make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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Log "make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}"
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Log "make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}"
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make ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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Log "make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}"
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make ${OSBUILDSTR} ${CPUTYPE}=1 ${OSTYPE}=1 OS_BASEADDR=${OS_BOOTADDR} OS_APPADDR=${APP_BASEADDR} CPU=${CPU} HEAPADDR=${OS_HEAP_STARTADDR} HEAPSIZE=${OS_HEAP_SIZE} STACKADDR=${OS_STACK_STARTADDR} STACKENDADDR=${OS_STACK_ENDADDR} STACKSIZE=${OS_STACK_SIZE} ${BUILDFLAGS}
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else
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Fatal "Internal error, unrecognised CPUTYPE at ZOS Make"
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fi
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if [ $? != 0 ]; then
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Fatal "Aborting, failed to build zOS!"
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@@ -631,9 +714,14 @@ elif [ "${OS}" = "ZOS" ]; then
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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cp ${BUILDPATH}/zOS/${OSBUILDSTR}.bin ${BUILDPATH}/build/SD/${OS_SD_TARGET}
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cp ${BUILDPATH}/zOS/${OSBUILDSTR}.bin ${BUILDPATH}/build/SD/ZOS/ZOS.ROM
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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cp ${BUILDPATH}/zOS/main.bin ${BUILDPATH}/build/SD/${OS_SD_TARGET}
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cp ${BUILDPATH}/zOS/main.bin ${BUILDPATH}/build/SD/ZOS/ZOS.K64F.ROM
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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cp ${BUILDPATH}/zOS/main.bin ${BUILDPATH}/build/SD/${OS_SD_TARGET}
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cp ${BUILDPATH}/zOS/main.bin ${BUILDPATH}/build/SD/ZOS/ZOS.M68K.ROM
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else
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Fatal "Internal error, unrecognised CPUTYPE at ZOS Copy"
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fi
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fi
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@@ -644,9 +732,14 @@ fi
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if [ "${CPUTYPE}" = "__ZPU__" ]; then
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TMPLFILE=${BUILDPATH}/startup/app_${OSNAME}_zpu.tmpl
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LDFILE=${BUILDPATH}/startup/app_zpu_${OS_BOOTADDR}_${APP_BASEADDR}.ld
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else
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elif [ "${CPUTYPE}" = "__K64F__" ]; then
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TMPLFILE=${BUILDPATH}/startup/app_${OSNAME}_k64f.tmpl
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LDFILE=${BUILDPATH}/startup/app_k64f_${OS_BOOTADDR}_${APP_BASEADDR}.ld
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elif [ "${CPUTYPE}" = "__M68K__" ]; then
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TMPLFILE=${BUILDPATH}/startup/app_${OSNAME}_m68k.tmpl
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LDFILE=${BUILDPATH}/startup/app_m68k_${OS_BOOTADDR}_${APP_BASEADDR}.ld
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else
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Fatal "Internal error, unrecognised CPUTYPE at LD tmpl setup"
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fi
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cd ${BUILDPATH}/apps
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12
buildall
12
buildall
@@ -5,6 +5,11 @@
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# TARGET=MZ-80A
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ZPU_SHARPMZ_BUILD=1
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#ZPU_SHARPMZ_APPADDR=0x100000
|
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#ZPU_SHARPMZ_APPSIZE=0x70000
|
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#ZPU_SHARPMZ_HEAPSIZE=0x8000
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#ZPU_SHARPMZ_STACKSIZE=0x3D80
|
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|
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ZPU_SHARPMZ_APPADDR=0x100000
|
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ZPU_SHARPMZ_APPSIZE=0x70000
|
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ZPU_SHARPMZ_HEAPSIZE=0x8000
|
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@@ -26,7 +31,7 @@ rm -fr /dvlp/Projects/dev/github/zSoft/SD/K64F/*
|
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cd ${ROOT_DIR}/zSoft
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mkdir -p SD/SharpMZ
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mkdir -p SD/Dev
|
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mkdir -p SD/K64F
|
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mkdir -p SD/K64F/ZOS
|
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|
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if [ "${ZPU_SHARPMZ_BUILD}x" != "x" -a ${ZPU_SHARPMZ_BUILD} = 1 ]; then
|
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echo "Building ZPU for Sharp MZ"
|
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@@ -35,11 +40,14 @@ if [ "${ZPU_SHARPMZ_BUILD}x" != "x" -a ${ZPU_SHARPMZ_BUILD} = 1 ]; then
|
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echo "Error building Sharp MZ Distribution..."
|
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exit 1
|
||||
fi
|
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# Copy the BRAM ROM templates to the build area for the FPGA.
|
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cp rtl/TZSW_* ../tranZPUter/FPGA/SW700/v1.3/devices/sysbus/BRAM/
|
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# Copy the newly built files into the staging area ready for copying to an SD card.
|
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cp -r build/SD/* SD/SharpMZ/
|
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# The K64F needs a copy of the zOS ROM for the ZPU so that it can load it into the FPGA.
|
||||
cp build/SD/ZOS/* SD/K64F/ZOS/
|
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fi
|
||||
|
||||
|
||||
if [ "${ZPU_E115_BUILD}x" != "x" -a ${ZPU_E115_BUILD} = 1 ]; then
|
||||
echo "Building ZPU for Dev board"
|
||||
./build.sh -C EVO -O zos -o 0 -M 0x1FD80 -B 0x0000 -S ${ZPU_E115_STACKSIZE} -N ${ZPU_E115_HEAPSIZE} -A ${ZPU_E115_APPADDR} -a ${ZPU_E115_APPSIZE} -n 0x0000 -s 0x0000 -d
|
||||
|
||||
44
buildm68k.sh
Executable file
44
buildm68k.sh
Executable file
@@ -0,0 +1,44 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Not used: Target machine, used to select the right software for the SD card.
|
||||
# TARGET=MZ-700
|
||||
# TARGET=MZ-80A
|
||||
|
||||
M68K_SHARPMZ_BUILD=1
|
||||
M68K_SHARPMZ_APPADDR=0x100000
|
||||
M68K_SHARPMZ_APPSIZE=0x70000
|
||||
M68K_SHARPMZ_HEAPSIZE=0x8000
|
||||
M68K_SHARPMZ_STACKSIZE=0x3D80
|
||||
|
||||
|
||||
# NB: When setting this variable, see lower section creating the SD card image which uses a hard coded value and will need updating.
|
||||
ROOT_DIR=/dvlp/Projects/dev/github/
|
||||
# NB: This clean out is intentionally hard coded as -fr is dangerous, if a variable failed to be set if could see your source base wiped out.
|
||||
rm -fr /dvlp/Projects/dev/github/zSoft/SD/M68K/*
|
||||
|
||||
(
|
||||
# Ensure the zOS target directories exist.
|
||||
cd ${ROOT_DIR}/zSoft
|
||||
mkdir -p SD/SharpMZ
|
||||
mkdir -p SD/Dev
|
||||
mkdir -p SD/M68K/ZOS
|
||||
|
||||
if [ "${M68K_SHARPMZ_BUILD}x" != "x" -a ${M68K_SHARPMZ_BUILD} = 1 ]; then
|
||||
echo "Building M68K for Sharp MZ"
|
||||
./build.sh -C M68K -O zos -M 0x1FD80 -B 0x0000 -S ${M68K_SHARPMZ_STACKSIZE} -N ${M68K_SHARPMZ_HEAPSIZE} -A ${M68K_SHARPMZ_APPADDR} -a ${M68K_SHARPMZ_APPSIZE} -n 0x0000 -s 0x0000 -d -Z
|
||||
if [ $? != 0 ]; then
|
||||
echo "Error building Sharp MZ Distribution..."
|
||||
exit 1
|
||||
fi
|
||||
# Copy the BRAM ROM templates to the build area for the FPGA.
|
||||
# cp rtl/TZSW_* ../tranZPUter/FPGA/SW700/v1.3/devices/sysbus/BRAM/
|
||||
# Copy the newly built files into the staging area ready for copying to an SD card.
|
||||
# cp -r build/SD/* SD/SharpMZ/
|
||||
# The K64F needs a copy of the zOS ROM for the ZPU so that it can load it into the FPGA.
|
||||
# cp build/SD/ZOS/* SD/K64F/ZOS/
|
||||
fi
|
||||
|
||||
)
|
||||
if [ $? != 0 ]; then
|
||||
exit 1
|
||||
fi
|
||||
@@ -12,7 +12,10 @@
|
||||
#define int16_t __int16_t
|
||||
#define int8_t __int8_t
|
||||
#include "k64f_soc.h"
|
||||
#else
|
||||
#elif defined __ZPU__
|
||||
#include <stdint.h>
|
||||
#include "zpu_soc.h"
|
||||
#elif defined __M68K__
|
||||
#include <stdint.h>
|
||||
#include "zpu_soc.h"
|
||||
#endif
|
||||
@@ -31,8 +34,13 @@ void SetIntHandler(void(*handler)())
|
||||
{
|
||||
_inthandler_fptr=handler;
|
||||
}
|
||||
#elif defined __M68K__
|
||||
void SetIntHandler(void(*handler)())
|
||||
{
|
||||
return;
|
||||
}
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or M68K"
|
||||
#endif
|
||||
|
||||
#if !defined(FUNCTIONALITY) || FUNCTIONALITY <= 2
|
||||
@@ -50,8 +58,10 @@ void EnableInterrupt(uint32_t intrMask)
|
||||
INTERRUPT_CTRL(INTR0) = intrSetting;
|
||||
#elif defined __K64F__
|
||||
intrSetting = 0;
|
||||
#elif defined __M68K__
|
||||
intrSetting = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or M68K"
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -65,8 +75,9 @@ void DisableInterrupt(uint32_t intrMask)
|
||||
intrSetting &= ~intrMask;
|
||||
INTERRUPT_CTRL(INTR0) = intrSetting;
|
||||
#elif defined __K64F__
|
||||
#elif defined __M68K__
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or M68K"
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
269
common/m68k_soc.c
Normal file
269
common/m68k_soc.c
Normal file
@@ -0,0 +1,269 @@
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Name: m68k_soc.c
|
||||
// Created: January 2019
|
||||
// Author(s): Philip Smart
|
||||
// Description: M68000 System On a Chip utilities.
|
||||
// A set of utilities specific to interaction with the ZPU SoC hardware.
|
||||
//
|
||||
// Credits:
|
||||
// Copyright: (c) 2019-2021 Philip Smart <philip.smart@net2net.org>
|
||||
//
|
||||
// History: January 2019 - Initial script written.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// This source file is free software: you can redistribute it and#or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
//#include <stdlib.h>
|
||||
#include "uart.h"
|
||||
#include "m68k_soc.h"
|
||||
|
||||
// Global scope variables.
|
||||
#ifdef USE_BOOT_ROM
|
||||
SOC_CONFIG cfgSoC;
|
||||
#else
|
||||
SOC_CONFIG cfgSoC = { .addrInsnBRAM = INSN_BRAM_ADDR,
|
||||
.sizeInsnBRAM = INSN_BRAM_SIZE,
|
||||
.addrBRAM = BRAM_ADDR,
|
||||
.sizeBRAM = BRAM_SIZE,
|
||||
.addrRAM = RAM_ADDR,
|
||||
.sizeRAM = RAM_SIZE,
|
||||
.addrSDRAM = SDRAM_ADDR,
|
||||
.sizeSDRAM = SDRAM_SIZE,
|
||||
.addrWBSDRAM = WB_SDRAM_ADDR,
|
||||
.sizeWBSDRAM = WB_SDRAM_SIZE,
|
||||
.resetVector = CPU_RESET_ADDR,
|
||||
.cpuMemBaseAddr = CPU_MEM_START,
|
||||
.stackStartAddr = STACK_BRAM_ADDR,
|
||||
.m68kId = M68K_ID,
|
||||
.sysFreq = CLK_FREQ,
|
||||
.memFreq = CLK_FREQ,
|
||||
.wbMemFreq = CLK_FREQ,
|
||||
.implSoCCFG = 0,
|
||||
.implWB = WB_IMPL,
|
||||
.implWBSDRAM = WB_SDRAM_IMPL,
|
||||
.implWBI2C = WB_I2C_IMPL,
|
||||
.implInsnBRAM = INSN_BRAM_IMPL,
|
||||
.implBRAM = BRAM_IMPL,
|
||||
.implRAM = RAM_IMPL,
|
||||
.implSDRAM = SDRAM_IMPL,
|
||||
.implIOCTL = IOCTL_IMPL,
|
||||
.implPS2 = PS2_IMPL,
|
||||
.implSPI = SPI_IMPL,
|
||||
.implSD = SD_IMPL,
|
||||
.sdCardNo = SD_DEVICE_CNT,
|
||||
.implIntrCtl = INTRCTL_IMPL,
|
||||
.intrChannels = INTRCTL_CHANNELS,
|
||||
.implTimer1 = TIMER1_IMPL,
|
||||
.timer1No = TIMER1_TIMERS_CNT };
|
||||
#endif
|
||||
|
||||
|
||||
// Method to populate the Configuration structure, initially using in-built values from compile time
|
||||
// which are overriden with values stored in the SoC if available.
|
||||
void setupSoCConfig(void)
|
||||
{
|
||||
// If the SoC Configuration register is implemented in the SoC, overwrite the compiled constants with those in the chip register.
|
||||
if( IS_IMPL_SOCCFG )
|
||||
{
|
||||
cfgSoC.addrInsnBRAM = SOCCFG(SOCCFG_BRAMINSNADDR);
|
||||
cfgSoC.sizeInsnBRAM = SOCCFG(SOCCFG_BRAMINSNSIZE);
|
||||
cfgSoC.addrBRAM = SOCCFG(SOCCFG_BRAMADDR);
|
||||
cfgSoC.sizeBRAM = SOCCFG(SOCCFG_BRAMSIZE);
|
||||
cfgSoC.addrRAM = SOCCFG(SOCCFG_RAMADDR);
|
||||
cfgSoC.sizeRAM = SOCCFG(SOCCFG_RAMSIZE);
|
||||
cfgSoC.addrSDRAM = SOCCFG(SOCCFG_SDRAMADDR);
|
||||
cfgSoC.sizeSDRAM = SOCCFG(SOCCFG_SDRAMSIZE);
|
||||
cfgSoC.addrWBSDRAM = SOCCFG(SOCCFG_WBSDRAMADDR);
|
||||
cfgSoC.sizeWBSDRAM = SOCCFG(SOCCFG_WBSDRAMSIZE);
|
||||
cfgSoC.resetVector = SOCCFG(SOCCFG_CPURSTADDR);
|
||||
cfgSoC.cpuMemBaseAddr = SOCCFG(SOCCFG_CPUMEMSTART);
|
||||
cfgSoC.stackStartAddr = SOCCFG(SOCCFG_STACKSTART);
|
||||
cfgSoC.m68kId = SOCCFG(SOCCFG_M68K_ID);
|
||||
cfgSoC.sysFreq = SOCCFG(SOCCFG_SYSFREQ);
|
||||
cfgSoC.memFreq = SOCCFG(SOCCFG_MEMFREQ);
|
||||
cfgSoC.wbMemFreq = SOCCFG(SOCCFG_WBMEMFREQ);
|
||||
cfgSoC.implSoCCFG = 1;
|
||||
cfgSoC.implWB = IS_IMPL_WB != 0;
|
||||
cfgSoC.implWBSDRAM = IS_IMPL_WB_SDRAM != 0;
|
||||
cfgSoC.implWBI2C = IS_IMPL_WB_I2C != 0;
|
||||
cfgSoC.implInsnBRAM = IS_IMPL_INSN_BRAM != 0;
|
||||
cfgSoC.implBRAM = IS_IMPL_BRAM != 0;
|
||||
cfgSoC.implRAM = IS_IMPL_RAM != 0;
|
||||
cfgSoC.implSDRAM = IS_IMPL_SDRAM != 0;
|
||||
cfgSoC.implIOCTL = IS_IMPL_IOCTL != 0;
|
||||
cfgSoC.implPS2 = IS_IMPL_PS2 != 0;
|
||||
cfgSoC.implSPI = IS_IMPL_SPI != 0;
|
||||
cfgSoC.implSD = IS_IMPL_SD != 0;
|
||||
cfgSoC.sdCardNo = (uint8_t)(SOCCFG_SD_DEVICES);
|
||||
cfgSoC.implIntrCtl = IS_IMPL_INTRCTL != 0;
|
||||
cfgSoC.intrChannels = (uint8_t)(SOCCFG_INTRCTL_CHANNELS);
|
||||
cfgSoC.implTimer1 = IS_IMPL_TIMER1 != 0;
|
||||
cfgSoC.timer1No = (uint8_t)(SOCCFG_TIMER1_TIMERS);
|
||||
#ifndef USE_BOOT_ROM
|
||||
}
|
||||
#else
|
||||
} else
|
||||
{
|
||||
// Store builtin constants into structure which will be used when the SoC configuration module isnt implemented.
|
||||
cfgSoC.addrInsnBRAM = INSN_BRAM_ADDR;
|
||||
cfgSoC.sizeInsnBRAM = INSN_BRAM_SIZE;
|
||||
cfgSoC.addrBRAM = BRAM_ADDR;
|
||||
cfgSoC.sizeBRAM = BRAM_SIZE;
|
||||
cfgSoC.addrRAM = RAM_ADDR;
|
||||
cfgSoC.sizeRAM = RAM_SIZE;
|
||||
cfgSoC.addrSDRAM = SDRAM_ADDR;
|
||||
cfgSoC.sizeSDRAM = SDRAM_SIZE;
|
||||
cfgSoC.addrWBSDRAM = WB_SDRAM_ADDR;
|
||||
cfgSoC.sizeWBSDRAM = WB_SDRAM_SIZE;
|
||||
cfgSoC.resetVector = CPU_RESET_ADDR;
|
||||
cfgSoC.cpuMemBaseAddr = CPU_MEM_START;
|
||||
cfgSoC.stackStartAddr = STACK_BRAM_ADDR;
|
||||
cfgSoC.m68kId = M68K_ID;
|
||||
cfgSoC.sysFreq = CLK_FREQ;
|
||||
cfgSoC.memFreq = CLK_FREQ;
|
||||
cfgSoC.wbMemFreq = CLK_FREQ;
|
||||
cfgSoC.implSoCCFG = 0;
|
||||
cfgSoC.implWB = WB_IMPL;
|
||||
cfgSoC.implWBSDRAM = WB_SDRAM_IMPL;
|
||||
cfgSoC.implWBI2C = WB_I2C_IMPL;
|
||||
cfgSoC.implInsnBRAM = INSN_BRAM_IMPL;
|
||||
cfgSoC.implBRAM = BRAM_IMPL ;
|
||||
cfgSoC.implRAM = RAM_IMPL;
|
||||
cfgSoC.implSDRAM = SDRAM_IMPL;;
|
||||
cfgSoC.implIOCTL = IOCTL_IMPL;;
|
||||
cfgSoC.implPS2 = PS2_IMPL;
|
||||
cfgSoC.implSPI = SPI_IMPL;
|
||||
cfgSoC.implSD = IMPL_SD;
|
||||
cfgSoC.sdCardNo = SD_DEVICE_CNT;
|
||||
cfgSoC.implIntrCtl = INTRCTL_IMPL;
|
||||
cfgSoC.intrChannels = INTRCTL_CHANNELS;
|
||||
cfgSoC.implTimer1 = TIMER1_IMPL;
|
||||
cfgSoC.timer1No = TIMER1_TIMERS_CNT;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// Method to show the current configuration via the primary uart channel.
|
||||
//
|
||||
#if !defined(FUNCTIONALITY) || FUNCTIONALITY <= 1
|
||||
void showSoCConfig(void)
|
||||
{
|
||||
#if defined(__ZOS__) || defined(__ZPUTA__)
|
||||
printf("SoC Configuration");
|
||||
if(cfgSoC.implSoCCFG) { printf(" (from SoC config)"); }
|
||||
printf(":\nDevices implemented:\n");
|
||||
if(cfgSoC.implWBSDRAM) { printf(" WB SDRAM (%08X:%08X).\n", cfgSoC.addrWBSDRAM, cfgSoC.addrWBSDRAM + cfgSoC.sizeWBSDRAM); }
|
||||
if(cfgSoC.implSDRAM) { printf(" SDRAM (%08X:%08X).\n", cfgSoC.addrSDRAM, cfgSoC.addrSDRAM + cfgSoC.sizeSDRAM); }
|
||||
if(cfgSoC.implInsnBRAM) { printf(" INSN BRAM (%08X:%08X).\n", cfgSoC.addrInsnBRAM, cfgSoC.addrInsnBRAM + cfgSoC.sizeInsnBRAM); }
|
||||
if(cfgSoC.implBRAM) { printf(" BRAM (%08X:%08X).\n", cfgSoC.addrBRAM, cfgSoC.addrBRAM + cfgSoC.sizeBRAM); }
|
||||
if(cfgSoC.implRAM) { printf(" RAM (%08X:%08X).\n", cfgSoC.addrRAM, cfgSoC.addrRAM + cfgSoC.sizeRAM); }
|
||||
if(cfgSoC.implSD) { printf(" SD CARD (Devices =%02d).\n", (uint8_t)cfgSoC.sdCardNo); }
|
||||
if(cfgSoC.implTimer1) { printf(" TIMER1 (Timers =%02d).\n", (uint8_t)cfgSoC.timer1No); }
|
||||
if(cfgSoC.implIntrCtl) { printf(" INTR CTRL (Channels=%02d).\n", (uint8_t)cfgSoC.intrChannels); }
|
||||
if(cfgSoC.implWB) { printf(" WISHBONE BUS\n"); }
|
||||
if(cfgSoC.implWBI2C) { printf(" WB I2C\n"); }
|
||||
if(cfgSoC.implIOCTL) { printf(" IOCTL\n"); }
|
||||
if(cfgSoC.implPS2) { printf(" PS2\n"); }
|
||||
if(cfgSoC.implSPI) { printf(" SPI\n"); }
|
||||
printf("Addresses:\n");
|
||||
printf(" CPU Reset Vector Address = %08X\n", cfgSoC.resetVector);
|
||||
printf(" CPU Memory Start Address = %08X\n", cfgSoC.cpuMemBaseAddr);
|
||||
printf(" Stack Start Address = %08X\n", cfgSoC.stackStartAddr);
|
||||
printf("Misc:\n");
|
||||
printf(" M68K Id = %04X\n", cfgSoC.m68kId);
|
||||
printf(" System Clock Freq = %d.%04dMHz\n", (cfgSoC.sysFreq / 1000000), cfgSoC.sysFreq - ((cfgSoC.sysFreq / 1000000) * 1000000));
|
||||
if(cfgSoC.implSDRAM)
|
||||
printf(" SDRAM Clock Freq = %d.%04dMHz\n", (cfgSoC.memFreq / 1000000), cfgSoC.memFreq - ((cfgSoC.memFreq / 1000000) * 1000000));
|
||||
if(cfgSoC.implWBSDRAM)
|
||||
printf(" Wishbone SDRAM Clock Freq= %d.%04dMHz\n", (cfgSoC.wbMemFreq / 1000000), cfgSoC.wbMemFreq - ((cfgSoC.wbMemFreq / 1000000) * 1000000));
|
||||
#ifdef DRV_CFC
|
||||
printf(" CFC = %08X\n", DRV_CFC);
|
||||
#endif
|
||||
#ifdef DRV_MMC
|
||||
printf(" MMC = %08X\n", DRV_MMC);
|
||||
#endif
|
||||
//printf("\n");
|
||||
#else
|
||||
puts("SoC Configuration");
|
||||
if(cfgSoC.implSoCCFG) { puts(" (from SoC config)"); }
|
||||
puts(":\nDevices implemented:\n");
|
||||
if(cfgSoC.implWBSDRAM) { puts(" WB SDRAM ("); printdhex(cfgSoC.addrWBSDRAM); puts(":"); printdhex(cfgSoC.addrWBSDRAM + cfgSoC.sizeWBSDRAM); puts(").\n"); }
|
||||
if(cfgSoC.implSDRAM) { puts(" SDRAM ("); printdhex(cfgSoC.addrSDRAM); puts(":"); printdhex(cfgSoC.addrSDRAM + cfgSoC.sizeSDRAM); puts(").\n"); }
|
||||
if(cfgSoC.implInsnBRAM) { puts(" INSN BRAM ("); printdhex(cfgSoC.addrInsnBRAM); puts(":"); printdhex(cfgSoC.addrInsnBRAM + cfgSoC.sizeInsnBRAM); puts(").\n"); }
|
||||
if(cfgSoC.implBRAM) { puts(" BRAM ("); printdhex(cfgSoC.addrBRAM); puts(":"); printdhex(cfgSoC.addrBRAM + cfgSoC.sizeBRAM); puts(").\n"); }
|
||||
if(cfgSoC.implRAM) { puts(" RAM ("); printdhex(cfgSoC.addrRAM); puts(":"); printdhex(cfgSoC.addrRAM + cfgSoC.sizeRAM); puts(").\n"); }
|
||||
if(cfgSoC.implSD) { puts(" SD CARD (Devices ="); printhexbyte((uint8_t)cfgSoC.sdCardNo); puts(").\n"); }
|
||||
if(cfgSoC.implTimer1) { puts(" TIMER1 (Timers ="); printnibble( (uint8_t)cfgSoC.timer1No); puts(").\n"); }
|
||||
if(cfgSoC.implIntrCtl) { puts(" INTR CTRL (Channels="); printhexbyte((uint8_t)cfgSoC.intrChannels); puts(").\n"); }
|
||||
if(cfgSoC.implWB) { puts(" WISHBONE BUS\n"); }
|
||||
if(cfgSoC.implWB) { puts(" WB I2C\n"); }
|
||||
if(cfgSoC.implIOCTL) { puts(" IOCTL\n"); }
|
||||
if(cfgSoC.implPS2) { puts(" PS2\n"); }
|
||||
if(cfgSoC.implSPI) { puts(" SPI\n"); }
|
||||
puts("Addresses:\n");
|
||||
puts(" CPU Reset Vector Address = "); printdhex(cfgSoC.resetVector); puts("\n");
|
||||
puts(" CPU Memory Start Address = "); printdhex(cfgSoC.cpuMemBaseAddr); puts("\n");
|
||||
puts(" Stack Start Address = "); printdhex(cfgSoC.stackStartAddr); puts("\n");
|
||||
puts("Misc:\n");
|
||||
puts(" M68K Id = "); printhex((uint16_t)cfgSoC.m68kId); puts("\n");
|
||||
puts(" System Clock Freq = "); printdhex(cfgSoC.sysFreq); puts("\n");
|
||||
if(cfgSoC.implSDRAM)
|
||||
puts(" SDRAM Clock Freq = "); printdhex(cfgSoC.memFreq); puts("\n");
|
||||
if(cfgSoC.implWBSDRAM)
|
||||
puts(" Wishbone SDRAM Clock Freq= "); printdhex(cfgSoC.wbMemFreq); puts("\n");
|
||||
#ifdef DRV_CFC
|
||||
puts(" CFC = "); printdhex(DRV_CFC); puts("\n");
|
||||
#endif
|
||||
#ifdef DRV_MMC
|
||||
puts(" MMC = "); printdhex(DRV_MMC); puts("\n");
|
||||
#endif
|
||||
puts("\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
// Function to print out the M68000 Id in text form.
|
||||
void printM68KId(uint32_t m68kId)
|
||||
{
|
||||
switch((uint8_t)(m68kId >> 8))
|
||||
{
|
||||
case M68K_ID_M68008:
|
||||
printf("M68008");
|
||||
break;
|
||||
|
||||
case M68K_ID_M68000:
|
||||
printf("M68000");
|
||||
break;
|
||||
|
||||
case M68K_ID_M68020:
|
||||
printf("M68020");
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("Unknown");
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
12
common/ps2.c
12
common/ps2.c
@@ -12,9 +12,12 @@
|
||||
#define int16_t __int16_t
|
||||
#define int8_t __int8_t
|
||||
#include "k64f_soc.h"
|
||||
#else
|
||||
#elif defined __ZPU__
|
||||
#include <stdint.h>
|
||||
#include "zpu_soc.h"
|
||||
#elif defined __M68K__
|
||||
#include <stdint.h>
|
||||
#include "m68k_soc.h"
|
||||
#endif
|
||||
|
||||
#include "ps2.h"
|
||||
@@ -108,8 +111,13 @@ void PS2Handler()
|
||||
{
|
||||
EnableInterrupts();
|
||||
}
|
||||
#elif defined __M68K__
|
||||
void PS2Handler()
|
||||
{
|
||||
EnableInterrupts();
|
||||
}
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
void PS2Init()
|
||||
|
||||
@@ -49,20 +49,28 @@
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <../libraries/include/stdmisc.h>
|
||||
#else
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#elif defined __ZPU__
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdmisc.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#elif defined __M68K__
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
|
||||
#if defined __SD_CARD__
|
||||
#include <ff.h>
|
||||
#endif
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "utils.h"
|
||||
|
||||
#if defined __APP__
|
||||
|
||||
@@ -57,6 +57,14 @@ extern "C" {
|
||||
#include <ctype.h>
|
||||
#include <stdmisc.h>
|
||||
#include <string.h>
|
||||
#elif defined(__M68K__)
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "m68k_soc.h"
|
||||
//#include <stdlib.h>
|
||||
#include <ctype.h>
|
||||
#include <stdmisc.h>
|
||||
#include <string.h>
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#endif
|
||||
@@ -1941,10 +1949,13 @@ uint8_t mzSweepKeys(void)
|
||||
*(volatile uint8_t *)(MBADDR_8BIT_KEYPA) = strobe;
|
||||
|
||||
// Slight delay to allow for bounce.
|
||||
TIMER_MILLISECONDS_UP = 0; while(TIMER_MILLISECONDS_UP == 0);
|
||||
TIMER_MILLISECONDS_UP = 0; while(TIMER_MILLISECONDS_UP < 1);
|
||||
|
||||
// Read the scan lines.
|
||||
keyboard.scanbuf[0][strobe-0xF0] = (uint8_t)(*(volatile uint32_t *)(MBADDR_8BIT_KEYPB));
|
||||
// keyboard.scanbuf[0][strobe-0xF0] = (uint8_t)(*(volatile uint32_t *)(MBADDR_8BIT_KEYPB));
|
||||
//printf("R%02x ", (uint8_t)(*(volatile uint32_t *)(MBADDR_8BIT_KEYPB)));
|
||||
|
||||
}
|
||||
|
||||
// Now look for active keys.
|
||||
@@ -1984,6 +1995,7 @@ uint8_t mzSweepKeys(void)
|
||||
}
|
||||
keyboard.scanbuf[1][strobeIdx] = keyboard.scanbuf[0][strobeIdx];
|
||||
}
|
||||
//printf("\n");
|
||||
|
||||
// Check for modifiers.
|
||||
//
|
||||
@@ -2074,6 +2086,7 @@ int mzGetKey(uint8_t mode)
|
||||
retcode = keyboard.repeatKey;
|
||||
}
|
||||
}
|
||||
|
||||
// Process internal keys, dont return.
|
||||
//
|
||||
switch(retcode)
|
||||
|
||||
@@ -41,6 +41,7 @@ extern "C" {
|
||||
#include <WProgram.h>
|
||||
#endif
|
||||
#include "k64f_soc.h"
|
||||
#elif defined __M68K__
|
||||
#endif
|
||||
|
||||
#if defined(__SD_CARD__)
|
||||
@@ -387,8 +388,10 @@ FRESULT fileConcatenate(char *src1, char *src2, char *dst)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
dstSize = 0;
|
||||
for (;;) {
|
||||
@@ -423,8 +426,10 @@ FRESULT fileConcatenate(char *src1, char *src2, char *dst)
|
||||
printBytesPerSec(dstSize, perfTime - *G->millis, "copied");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(dstSize, perfTime - millis(), "copied");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(dstSize, TIMER_MILLISECONDS_UP, "copied");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : (fr1 ? fr1 : (fr2 ? fr2 : FR_OK)));
|
||||
@@ -464,8 +469,10 @@ FRESULT fileCopy(char *src, char *dst)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
dstSize = 0;
|
||||
for (;;) {
|
||||
@@ -489,8 +496,10 @@ FRESULT fileCopy(char *src, char *dst)
|
||||
printBytesPerSec(dstSize, perfTime - *G->millis, "copied");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(dstSize, perfTime - millis(), "copied");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(dstSize, TIMER_MILLISECONDS_UP, "copied");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : (fr1 ? fr1 : FR_OK));
|
||||
@@ -531,8 +540,10 @@ FRESULT fileXtract(char *src, char *dst, uint32_t startPos, uint32_t len)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
dstSize = 0;
|
||||
|
||||
@@ -565,8 +576,10 @@ FRESULT fileXtract(char *src, char *dst, uint32_t startPos, uint32_t len)
|
||||
printBytesPerSec(dstSize, perfTime - *G->millis, "copied");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(dstSize, perfTime - millis(), "copied");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(dstSize, TIMER_MILLISECONDS_UP, "copied");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : (fr1 ? fr1 : FR_OK));
|
||||
@@ -645,8 +658,10 @@ FRESULT fileLoad(char *src, uint32_t addr, uint8_t showStats)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
loadSize = 0;
|
||||
for (;;) {
|
||||
@@ -668,8 +683,10 @@ FRESULT fileLoad(char *src, uint32_t addr, uint8_t showStats)
|
||||
printBytesPerSec(loadSize, perfTime - *G->millis, "read");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(loadSize, perfTime - millis(), "read");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(loadSize, TIMER_MILLISECONDS_UP, "read");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : FR_OK);
|
||||
@@ -707,8 +724,10 @@ FRESULT fileSave(char *dst, uint32_t addr, uint32_t len)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
saveSize = 0;
|
||||
for (;;) {
|
||||
@@ -731,8 +750,10 @@ FRESULT fileSave(char *dst, uint32_t addr, uint32_t len)
|
||||
printBytesPerSec(saveSize, perfTime - *G->millis, "written");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(saveSize, perfTime - millis(), "written");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(saveSize, TIMER_MILLISECONDS_UP, "written");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : FR_OK);
|
||||
@@ -769,8 +790,10 @@ FRESULT fileDump(char *src, uint32_t width)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
loadSize = 0;
|
||||
for (;;) {
|
||||
@@ -794,8 +817,10 @@ FRESULT fileDump(char *src, uint32_t width)
|
||||
printBytesPerSec(loadSize, perfTime - *G->millis, "read");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(loadSize, perfTime - millis(), "read");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(loadSize, TIMER_MILLISECONDS_UP, "read");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : FR_OK);
|
||||
@@ -821,8 +846,10 @@ uint32_t fileExec(char *src, uint32_t addr, uint32_t execAddr, uint8_t execMode,
|
||||
uint32_t (*func)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t) = (uint32_t (*)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t))execAddr;
|
||||
#elif defined __ZPU__
|
||||
uint32_t (*func)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t, uint32_t) = (uint32_t (*)(uint32_t, uint32_t, uint32_t *, uint32_t, uint32_t, uint32_t))execAddr;
|
||||
#elif defined __M68K__
|
||||
uint32_t (*func)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t) = (uint32_t (*)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t))execAddr;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
void *gotoptr = (void *)execAddr;
|
||||
FRESULT fr0;
|
||||
@@ -838,13 +865,15 @@ uint32_t fileExec(char *src, uint32_t addr, uint32_t execAddr, uint8_t execMode,
|
||||
// Call the loaded program entry address, return expected.
|
||||
case EXEC_MODE_CALL:
|
||||
#if defined __ZPU__
|
||||
//printf("0=%08lx, 1=%08lx, 2=%08lx, _IOB=%08lx %08lx %08lx\n", __iob[0], __iob[1], __iob[2], (uint32_t)(__iob), (uint32_t *)__iob, __iob );
|
||||
//printf("ExecAddr=%08lx, execMode=%02x, param1=%08lx, param2=%08lx, G=%08lx, cfg=%08lx\n", execAddr, execMode, param1, param2, G, cfg);
|
||||
//printf("0=%08lx, 1=%08lx, 2=%08lx, _IOB=%08lx %08lx %08lx\n", __iob[0], __iob[1], __iob[2], (uint32_t)(__iob), (uint32_t *)__iob, __iob );
|
||||
//printf("ExecAddr=%08lx, execMode=%02x, param1=%08lx, param2=%08lx, G=%08lx, cfg=%08lx\n", execAddr, execMode, param1, param2, G, cfg);
|
||||
retCode = func(param1, param2, &_memreg, G, cfg, (uint32_t)__iob);
|
||||
#elif defined __K64F__
|
||||
retCode = func(param1, param2, G, cfg, (uint32_t)stdin, (uint32_t)stdout, (uint32_t)stderr);
|
||||
#elif defined __M68K__
|
||||
retCode = func(param1, param2, G, cfg, (uint32_t)stdin, (uint32_t)stdout, (uint32_t)stderr);
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
break;
|
||||
|
||||
@@ -888,8 +917,10 @@ FRESULT fileBlockRead(FIL *fp, uint32_t len)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
while (loadSize && !fr0) {
|
||||
if (loadSize >= blockLen) { sizeToRead = blockLen; loadSize -= blockLen; }
|
||||
@@ -910,8 +941,10 @@ FRESULT fileBlockRead(FIL *fp, uint32_t len)
|
||||
printBytesPerSec(loadSize, perfTime - *G->millis, "read");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(loadSize, perfTime - millis(), "read");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(loadSize, TIMER_MILLISECONDS_UP, "read");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : FR_OK);
|
||||
@@ -942,8 +975,10 @@ FRESULT fileBlockWrite(FIL *fp, uint32_t len)
|
||||
perfTime = *G->millis;
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
perfTime = millis();
|
||||
#elif defined __M68K__
|
||||
TIMER_MILLISECONDS_UP = 0;
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
while (saveSize && !fr0) {
|
||||
if (saveSize >= blockLen) { sizeToWrite = blockLen; saveSize -= blockLen; }
|
||||
@@ -963,8 +998,10 @@ FRESULT fileBlockWrite(FIL *fp, uint32_t len)
|
||||
printBytesPerSec(len, perfTime - *G->millis, "written");
|
||||
#elif defined __K64F__ && (defined (__ZPUTA__) || defined (__ZOS__))
|
||||
printBytesPerSec(len, perfTime - millis(), "written");
|
||||
#elif defined __M68K__
|
||||
printBytesPerSec(len, TIMER_MILLISECONDS_UP, "written");
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
return(fr0 ? fr0 : FR_OK);
|
||||
@@ -1231,14 +1268,21 @@ void printVersion(uint8_t showConfig)
|
||||
printf("\n** %s (", PROGRAM_NAME);
|
||||
printCPU();
|
||||
printf(" CPU) %s %s **\n\n", VERSION, VERSION_DATE);
|
||||
#elif defined __M68K__
|
||||
printf("** %s (", PROGRAM_NAME);
|
||||
printM68KId(cfgSoC.m68kId);
|
||||
printf(" CPU) %s %s **\n\n", VERSION, VERSION_DATE);
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
|
||||
// Show configuration if requested.
|
||||
if(showConfig)
|
||||
{
|
||||
showSoCConfig();
|
||||
printf("OS:\n");
|
||||
printf(" Base Address = %08lx\n", (uint32_t)OS_BASEADDR);
|
||||
printf(" App Address = %08lx\n", (uint32_t)OS_APPADDR);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
@@ -4488,13 +4488,17 @@ void processServiceRequest(void)
|
||||
// Raw read access to the SD card.
|
||||
//
|
||||
case TZSVC_CMD_SD_READSECTOR:
|
||||
//printf("Read Raw Start\n");
|
||||
status=svcReadSDRaw();
|
||||
//printf("Read Raw Exit\n");
|
||||
break;
|
||||
|
||||
// Raw write access to the SD card.
|
||||
//
|
||||
case TZSVC_CMD_SD_WRITESECTOR:
|
||||
//printf("Write Raw Start\n");
|
||||
status=svcWriteSDRaw();
|
||||
//printf("Write Raw Exit\n");
|
||||
break;
|
||||
|
||||
// Command to exit from TZFS and return machine to original mode.
|
||||
|
||||
@@ -8,8 +8,11 @@
|
||||
#elif defined(__ZPU__)
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#elif defined(__M68K__)
|
||||
#include <stdint.h>
|
||||
// #include <stdlib.h>
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or M68K"
|
||||
#endif
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
@@ -46,8 +46,13 @@
|
||||
#elif defined(__ZPU__)
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#elif defined(__M68K__)
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
// #include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or M68K"
|
||||
#endif
|
||||
|
||||
#include "umm_malloc_cfg.h" /* user-dependent */
|
||||
|
||||
@@ -39,7 +39,7 @@
|
||||
#include "usb_serial.h"
|
||||
#include "k64f_soc.h"
|
||||
#include <../libraries/include/stdmisc.h>
|
||||
#else
|
||||
#elif defined __ZPU__
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
@@ -49,6 +49,11 @@
|
||||
#if defined __SHARPMZ__
|
||||
#include "sharpmz.h"
|
||||
#endif
|
||||
#elif defined __M68K__
|
||||
#include <stdio.h>
|
||||
// #include <stdint.h>
|
||||
// #include <stdlib.h>
|
||||
#include <string.h>
|
||||
#endif
|
||||
|
||||
#if defined(__SD_CARD__)
|
||||
@@ -275,6 +280,7 @@ int8_t getKey(uint8_t mode)
|
||||
keyIn = getserial_nonblocking();
|
||||
}
|
||||
#endif
|
||||
#elif defined __M68K__
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#endif
|
||||
|
||||
@@ -201,7 +201,7 @@ void showSoCConfig(void)
|
||||
#ifdef DRV_MMC
|
||||
printf(" MMC = %08X\n", DRV_MMC);
|
||||
#endif
|
||||
printf("\n");
|
||||
//printf("\n");
|
||||
#else
|
||||
puts("SoC Configuration");
|
||||
if(cfgSoC.implSoCCFG) { puts(" (from SoC config)"); }
|
||||
|
||||
@@ -39,7 +39,7 @@ struct MasterBootRecord
|
||||
unsigned char bootcode[446]; // ignored
|
||||
struct PartitionEntry Partition[4]; // We copy these (and byteswap if need be)
|
||||
unsigned short Signature; // This lets us detect an MBR (and the need for byteswapping).
|
||||
} __attribute__ ((packed));
|
||||
} __attribute__((packed));
|
||||
|
||||
extern struct PartitionEntry partitions[4]; // FirstBlock and LastBlock will be byteswapped as necessary
|
||||
extern int partitioncount;
|
||||
@@ -72,7 +72,7 @@ typedef struct
|
||||
unsigned short ModifyDate; /* last update date */
|
||||
unsigned short StartCluster; /* starting cluster of file */
|
||||
unsigned long FileSize; /* size of file in bytes */
|
||||
} __attribute__ ((packed)) DIRENTRY;
|
||||
} __attribute__((packed)) DIRENTRY;
|
||||
|
||||
typedef union {
|
||||
unsigned short fat16[256];
|
||||
|
||||
518
include/m68k_soc.h
Normal file
518
include/m68k_soc.h
Normal file
@@ -0,0 +1,518 @@
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Name: m68k_soc.h
|
||||
// Created: January 2019
|
||||
// Author(s): Philip Smart
|
||||
// Description: M68K System On a Chip utilities.
|
||||
// A set of utilities specific to interaction with the M68000 SoC hardware.
|
||||
//
|
||||
// Credits:
|
||||
// Copyright: (c) 2019-2021 Philip Smart <philip.smart@net2net.org>
|
||||
//
|
||||
// History: January 2019 - Initial script written.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// This source file is free software: you can redistribute it and#or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef __M68KSOC_H__
|
||||
#define __M68KSOC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
typedef volatile unsigned int* register_t;
|
||||
#endif
|
||||
|
||||
// Macro to omit code if deemed optional and the compile time flag MINIMUM_FUNCTIONALITY is defined.
|
||||
#ifdef MINIMUM_FUNCTIONALITY
|
||||
#define OPTIONAL(a)
|
||||
#else
|
||||
#define OPTIONAL(a) a
|
||||
#endif
|
||||
|
||||
// System settings.
|
||||
#define CLK_FREQ 100000000UL // Default frequency used to configure SoC if not present.
|
||||
|
||||
// Memory sizes and devices implemented - these can be ignored if the SoC Configuration register is implemented as this provides the exact build configuration.
|
||||
#define M68K_ID 0x0000
|
||||
#define WB_IMPL 0
|
||||
#define WB_SDRAM_IMPL 0
|
||||
#define WB_I2C_IMPL 0
|
||||
#define BRAM_IMPL 1
|
||||
#define RAM_IMPL 1
|
||||
#define INSN_BRAM_IMPL 1
|
||||
#define SDRAM_IMPL 1
|
||||
#define IOCTL_IMPL 1
|
||||
#define PS2_IMPL 1
|
||||
#define SPI_IMPL 1
|
||||
#define SD_IMPL 1
|
||||
#define SD_DEVICE_CNT 1
|
||||
#define INTRCTL_IMPL 1
|
||||
#define INTRCTL_CHANNELS 16
|
||||
#define TIMER1_IMPL 1
|
||||
#define TIMER1_TIMERS_CNT 1
|
||||
#define SDRAM_ADDR 0x00010000
|
||||
#define SDRAM_SIZE 0x00810000
|
||||
#define WB_SDRAM_ADDR 0x01000000
|
||||
#define WB_SDRAM_SIZE 0x017FFFFF
|
||||
#define BRAM_ADDR 0x00000000
|
||||
#define BRAM_SIZE 0x00007FFF
|
||||
#define INSN_BRAM_ADDR 0x00000000
|
||||
#define INSN_BRAM_SIZE 0x00007FFF
|
||||
#define RAM_ADDR 0x00010000
|
||||
#define RAM_SIZE 0x00007FFF
|
||||
#define STACK_BRAM_ADDR 0x00007800
|
||||
#define STACK_BRAM_SIZE 0x000007FF
|
||||
#define CPU_RESET_ADDR 0x00000000
|
||||
#define CPU_MEM_START 0x00000000
|
||||
#define BRAM_APP_START_ADDR 0x2000
|
||||
|
||||
//
|
||||
#define SPIISBLOCKING 1
|
||||
#define BIT(x) (1<<(x))
|
||||
#define MEMIO32 *(volatile unsigned int *)
|
||||
|
||||
// M68000 Id definitions.
|
||||
//
|
||||
#define M68K_ID_M68008 0x01
|
||||
#define M68K_ID_M68000 0x02
|
||||
#define M68K_ID_M68020 0x03
|
||||
|
||||
// IO base address.
|
||||
//#define IO_ADDR_PERIPHERALS 0xFFFFF000
|
||||
#define IO_ADDR_PERIPHERALS 0x0F00000
|
||||
#define IO_ADDR_WB_PERIPHERALS 0x1F00000
|
||||
|
||||
// Baud rate computation for UART
|
||||
#define BAUDRATEGEN(b,x,y) (((UART_SYSCLK(b)/(x))) << 16) | (((UART_SYSCLK(b)/(y))))
|
||||
|
||||
// ----------------------------------
|
||||
// CPU Bus I/O Peripheral definition.
|
||||
// ----------------------------------
|
||||
|
||||
// TCPU Processor Controller.
|
||||
//
|
||||
#define TCPU_BASE IO_ADDR_PERIPHERALS + 0x700
|
||||
#define ADDR_REGISTER 0x00
|
||||
#define DATA_REGISTER 0x04
|
||||
#define TCPU_ADDR (MEMIO32 (TCPU_BASE + ADDR_REGISTER))
|
||||
#define TCPU_DATA (MEMIO32 (TCPU_BASE + DATA_REGISTER))
|
||||
|
||||
// IO Processor Controller.
|
||||
#define IOCTL_BASE IO_ADDR_PERIPHERALS + 0x800
|
||||
#define CMDADDR_REGISTER 0x00
|
||||
#define DATA_REGISTER 0x04
|
||||
#define CHRCOLS_REGISTER 0x08
|
||||
#define CGADDR_REGISTER 0x0C
|
||||
#define IOCTL_CMDADDR (MEMIO32 (IOCTL_BASE + CMDADDR_REGISTER))
|
||||
#define IOCTL_DOUT (MEMIO32 (IOCTL_BASE + DATA_REGISTER))
|
||||
#define IOCTL_DIN (MEMIO32 (IOCTL_BASE + DATA_REGISTER))
|
||||
#define IOCTL_CHRCOLS (MEMIO32 (IOCTL_BASE + CHRCOLS_REGISTER))
|
||||
#define IOCTL_CGADDR (MEMIO32 (IOCTL_BASE + CGADDR_REGISTER))
|
||||
|
||||
// SD Card Controller.
|
||||
#define SD_BASE IO_ADDR_PERIPHERALS + 0x900
|
||||
#define SD0 0
|
||||
#define SD1 1
|
||||
#define SD2 2
|
||||
#define SD3 3
|
||||
#define SD_SPACING 0x10
|
||||
#define SD_ADDR_REGISTER 0x00
|
||||
#define SD_DATA_REGISTER 0x04
|
||||
#define SD_STATUS_REGISTER 0x0c
|
||||
#define SD_CMD_REGISTER 0x0c
|
||||
#define SD_CMD_RESET 0x00000001
|
||||
#define SD_CMD_WRITE 0x00000002
|
||||
#define SD_CMD_READ 0x00000004
|
||||
#define SD_CMD_CARDTYPE 0x00000008
|
||||
#define SD_CMD_CARDTYPE_SD 0x00000008
|
||||
#define SD_CMD_CARDTYPE_SDHC 0x00000088
|
||||
#define SD_STATUS_CONTINUE 0x00000001
|
||||
#define SD_STATUS_BUSY 0x00000002
|
||||
#define SD_STATUS_HNDSHK_OUT 0x00000004
|
||||
#define SD_STATUS_HNDSHK_IN 0x00000008
|
||||
#define SD_STATUS_DATA_REQ 0x00000010
|
||||
#define SD_STATUS_DATA_VALID 0x00000020
|
||||
#define SD_STATUS_OVERRUN 0x00000040
|
||||
#define SD_STATUS_IDLESTATE 0x00010000
|
||||
#define SD_STATUS_ERASERESET 0x00020000
|
||||
#define SD_STATUS_ILLEGALCMD 0x00040000
|
||||
#define SD_STATUS_CRCERROR 0x00080000
|
||||
#define SD_STATUS_ERASESEQ 0x00100000
|
||||
#define SD_STATUS_ADDRERR 0x00200000
|
||||
#define SD_STATUS_PARAMERR 0x00400000
|
||||
#define SD_STATUS_ERROR 0xFFFF0000
|
||||
#define SD(x, y) (MEMIO32 (SD_BASE+(x*SD_SPACING) + y))
|
||||
#define SD_ADDR(x) (MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_ADDR_REGISTER))
|
||||
#define SD_DATA(x) (MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_DATA_REGISTER))
|
||||
#define SD_CMD(x) (MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_CMD_REGISTER))
|
||||
#define SD_STATUS(x) (MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_STATUS_REGISTER))
|
||||
#define IS_SD_BUSY(x) ((MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_STATUS_REGISTER)) & SD_STATUS_BUSY) >> 1
|
||||
#define IS_SD_ERROR(x) ((MEMIO32 (SD_BASE+(x*SD_SPACING) + SD_STATUS_REGISTER)) & SD_STATUS_ERROR) >> 16
|
||||
|
||||
// UART definitions.
|
||||
#define UART_BASE IO_ADDR_PERIPHERALS + 0xA00
|
||||
#define UART0 0
|
||||
#define UART1 1
|
||||
#define UART_SPACING 0x10 // Address spacing between UART modules.
|
||||
// UART Registers and macros to read/write them.
|
||||
#define UART_DATA_REGISTER 0x00
|
||||
#define UART_CTRL_REGISTER 0x04
|
||||
#define UART_STATUS_REGISTER 0x04
|
||||
#define UART_FIFO_REGISTER 0x08
|
||||
#define UART_BAUDRATE_REGISTER 0x0C
|
||||
#define UART_SYSCLK_REGISTER 0x0C
|
||||
#define UART_DATA(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_DATA_REGISTER))
|
||||
#define UART_STATUS(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_STATUS_REGISTER))
|
||||
#define UART_FIFO_STATUS(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_FIFO_REGISTER))
|
||||
#define UART_CTRL(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_CTRL_REGISTER))
|
||||
#define UART_BRGEN(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_BAUDRATE_REGISTER))
|
||||
#define UART_SYSCLK(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_SYSCLK_REGISTER))
|
||||
// UART Status flags.
|
||||
#define UART_RX_FIFO_EMPTY 0x00000001
|
||||
#define UART_RX_FIFO_FULL 0x00000002
|
||||
#define UART_RX_DATA_READY 0x00000004
|
||||
#define UART_RX_OVERRUN 0x00000008
|
||||
#define UART_RX_INTERRUPT 0x00000010
|
||||
#define UART_RX_FIFO_ENABLED 0x00000020
|
||||
#define UART_RX_ENABLED 0x00000040
|
||||
#define UART_RX_IN_RESET 0x00000080
|
||||
#define UART_TX_FIFO_EMPTY 0x00010000
|
||||
#define UART_TX_FIFO_FULL 0x00020000
|
||||
#define UART_TX_BUSY 0x00040000
|
||||
#define UART_TX_DATA_LOADED 0x00080000
|
||||
#define UART_TX_OVERRUN 0x00100000
|
||||
#define UART_TX_INTERRUPT 0x00200000
|
||||
#define UART_TX_FIFO_ENABLED 0x00400000
|
||||
#define UART_TX_ENABLED 0x00800000
|
||||
#define UART_TX_IN_RESET 0x01000000
|
||||
// UART Control flags.
|
||||
#define UART_RX_ENABLE 0x00000001
|
||||
#define UART_RX_FIFO_ENABLE 0x00000002
|
||||
#define UART_RX_RESET 0x00000004
|
||||
#define UART_TX_ENABLE 0x00010000
|
||||
#define UART_TX_FIFO_ENABLE 0x00020000
|
||||
#define UART_TX_RESET 0x00040000
|
||||
// UART macros to test 32bit status register value.
|
||||
#define UART_IS_TX_FIFO_ENABLED(x) ((x & UART_TX_FIFO_ENABLED) != 0)
|
||||
#define UART_IS_TX_FIFO_DISABLED(x) ((x & UART_TX_FIFO_ENABLED) == 0)
|
||||
#define UART_IS_TX_FIFO_FULL(x) ((x & UART_TX_FIFO_FULL) != 0)
|
||||
#define UART_IS_TX_BUSY(x) ((x & UART_TX_BUSY) != 0)
|
||||
#define UART_IS_TX_DATA_LOADED(x) ((x & UART_TX_DATA_LOADED) != 0)
|
||||
#define UART_IS_RX_FIFO_ENABLED(x) ((x & UART_RX_FIFO_ENABLED) != 0)
|
||||
#define UART_IS_RX_FIFO_DISABLED(x) ((x & UART_RX_FIFO_ENABLED) == 0)
|
||||
#define UART_IS_RX_FIFO_EMPTY(x) ((x & UART_RX_FIFO_EMPTY) != 0)
|
||||
#define UART_IS_RX_DATA_READY(x) ((x & UART_RX_DATA_READY) != 0)
|
||||
// UART macros to test for a specific flag.
|
||||
#define UART_STATUS_RX_FIFO_EMPTY(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_FIFO_EMPTY
|
||||
#define UART_STATUS_RX_FIFO_FULL(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_FIFO_FULL
|
||||
#define UART_STATUS_RX_DATA_READY(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_DATA_READY
|
||||
#define UART_STATUS_RX_OVERRUN(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_OVERRUN
|
||||
#define UART_STATUS_RX_INTR(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_INTERRUPT
|
||||
#define UART_STATUS_RX_FIFO_ENABLED(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_FIFO_ENABLED
|
||||
#define UART_STATUS_RX_ENABLED(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_RX_ENABLED
|
||||
#define UART_STATUS_RX_IN_RESET(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_RX_REGISTER)) & UART_IN_RESET
|
||||
#define UART_STATUS_TX_FIFO_EMPTY(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_FIFO_EMPTY
|
||||
#define UART_STATUS_TX_FIFO_FULL(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_FIFO_FULL
|
||||
#define UART_STATUS_TX_BUSY(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_BUSY
|
||||
#define UART_STATUS_TX_DATA_LOADED(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_DATA_LOADED
|
||||
#define UART_STATUS_TX_OVERRUN(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_OVERRUN
|
||||
#define UART_STATUS_TX_INTR(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_INTERRUPT
|
||||
#define UART_STATUS_TX_FIFO_ENABLED(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_FIFO_ENABLED
|
||||
#define UART_STATUS_TX_ENABLED(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_TX_ENABLED
|
||||
#define UART_STATUS_TX_IN_RESET(x) (MEMIO32 (UART_BASE+(x*UART_SPACING)+UART_TX_REGISTER)) & UART_IN_RESET
|
||||
|
||||
// Interrupt Controller.
|
||||
#define INTERRUPT_BASE IO_ADDR_PERIPHERALS + 0xB00
|
||||
#define INTR0 0
|
||||
#define INTERRUPT_SPACING 0x10
|
||||
#define INTERRUPT_STATUS_REGISTER 0x0
|
||||
#define INTERRUPT_CTRL_REGISTER 0x4
|
||||
#define INTERRUPT(x,y) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING)+y))
|
||||
#define INTERRUPT_STATUS(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING)+INTERRUPT_STATUS_REGISTER))
|
||||
#define INTERRUPT_CTRL(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING)+INTERRUPT_CTRL_REGISTER))
|
||||
// Interrupt bit locations.
|
||||
#define INTR_TIMER 0x00000002
|
||||
#define INTR_PS2 0x00000004
|
||||
#define INTR_IOCTL_RD 0x00000008
|
||||
#define INTR_IOCTL_WR 0x00000010
|
||||
#define INTR_UART0_RX 0x00000020
|
||||
#define INTR_UART0_TX 0x00000040
|
||||
#define INTR_UART1_RX 0x00000080
|
||||
#define INTR_UART1_TX 0x00000100
|
||||
// Macros to test a specific interrupt, ignoring others.
|
||||
#define INTR_TEST_TIMER(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_TIMER
|
||||
#define INTR_TEST_PS2(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_PS2
|
||||
#define INTR_TEST_IOCTL_RD(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_IOCTL_RD
|
||||
#define INTR_TEST_IOCTL_WR(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_IOCTL_WR
|
||||
#define INTR_TEST_UART0_RX(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_UART0_RX
|
||||
#define INTR_TEST_UART0_TX(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_UART0_TX
|
||||
#define INTR_TEST_UART1_RX(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_UART1_RX
|
||||
#define INTR_TEST_UART1_TX(x) (MEMIO32 (INTERRUPT_BASE+(x*INTERRUPT_SPACING))) & INTR_UART1_TX
|
||||
// Macros to test a variable for a specific interrupt.
|
||||
#define INTR_IS_TIMER(x) (x) & INTR_TIMER
|
||||
#define INTR_IS_PS2(x) (x) & INTR_PS2
|
||||
#define INTR_IS_IOCTL_RD(x) (x) & INTR_IOCTL_RD
|
||||
#define INTR_IS_IOCTL_WR(x) (x) & INTR_IOCTL_WR
|
||||
#define INTR_IS_UART0_RX(x) (x) & INTR_UART0_RX
|
||||
#define INTR_IS_UART0_TX(x) (x) & INTR_UART0_TX
|
||||
#define INTR_IS_UART1_RX(x) (x) & INTR_UART1_RX
|
||||
#define INTR_IS_UART1_TX(x) (x) & INTR_UART1_TX
|
||||
|
||||
// Timer.
|
||||
// TIMER0 -> An RTC down to microsecond resolution and 3 delay counters, 1x uS and 1x mS down counters and 1x mS up counter.
|
||||
// TIMER1-> are standard timers.
|
||||
#define TIMER_BASE IO_ADDR_PERIPHERALS + 0xC00
|
||||
#define TIMER_SPACING 0x40
|
||||
#define TIMER0 0
|
||||
#define TIMER1 1
|
||||
#define TIMER_ENABLE_REG 0x00
|
||||
#define TIMER_INDEX_REG 0x04
|
||||
#define TIMER_COUNTER_REG 0x08
|
||||
#define TIMER_MICROSEC_DOWN_REG 0x00
|
||||
#define TIMER_MILLISEC_DOWN_REG 0x04
|
||||
#define TIMER_MILLISEC_UP_REG 0x08
|
||||
#define TIMER_SECONDS_DOWN_REG 0x0C
|
||||
#define RTC_CTRL_HALT 0x00000001
|
||||
#define RTC_CONTROL_REG 0x1C
|
||||
#define RTC_MILLISECONDS_EPOCH_REG 0x1C
|
||||
#define RTC_MICROSECONDS_REG 0x20
|
||||
#define RTC_MILLISECONDS_REG 0x24
|
||||
#define RTC_SECOND_REG 0x28
|
||||
#define RTC_MINUTE_REG 0x2C
|
||||
#define RTC_HOUR_REG 0x30
|
||||
#define RTC_DAY_REG 0x34
|
||||
#define RTC_MONTH_REG 0x38
|
||||
#define RTC_YEAR_REG 0x3C
|
||||
#define TIMER(x, y) (MEMIO32 (TIMER_BASE+(x*TIMER_SPACING) + y))
|
||||
#define TIMER_ENABLE(x) (MEMIO32 (TIMER_BASE+(x*TIMER_SPACING) + TIMER_ENABLE_REG))
|
||||
#define TIMER_INDEX(x) (MEMIO32 (TIMER_BASE+(x*TIMER_SPACING) + TIMER_INDEX_REG))
|
||||
#define TIMER_COUNTER(x) (MEMIO32 (TIMER_BASE+(x*TIMER_SPACING) + TIMER_COUNTER_REG))
|
||||
#define TIMER_MICROSECONDS_DOWN (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + TIMER_MICROSEC_DOWN_REG))
|
||||
#define TIMER_MILLISECONDS_DOWN (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + TIMER_MILLISEC_DOWN_REG))
|
||||
#define TIMER_MILLISECONDS_UP (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + TIMER_MILLISEC_UP_REG))
|
||||
#define TIMER_SECONDS_DOWN (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + TIMER_SECONDS_DOWN_REG))
|
||||
#define RTC_CONTROL (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_CONTROL_REG))
|
||||
#define RTC_MICROSECONDS (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_MICROSECONDS_REG))
|
||||
#define RTC_MILLISECONDS_EPOCH (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_MILLISECONDS_EPOCH_REG))
|
||||
#define RTC_MILLISECONDS (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_MILLISECONDS_REG))
|
||||
#define RTC_SECOND (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_SECOND_REG))
|
||||
#define RTC_MINUTE (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_MINUTE_REG))
|
||||
#define RTC_HOUR (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_HOUR_REG))
|
||||
#define RTC_DAY (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_DAY_REG))
|
||||
#define RTC_MONTH (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_MONTH_REG))
|
||||
#define RTC_YEAR (MEMIO32 (TIMER_BASE+(TIMER0*TIMER_SPACING) + RTC_YEAR_REG))
|
||||
|
||||
// SPI Controller.
|
||||
#define SPI_BASE IO_ADDR_PERIPHERALS + 0xD00
|
||||
#define SPI0 0
|
||||
#define SPI1 1
|
||||
#define SPI2 2
|
||||
#define SPI3 3
|
||||
#define SPI_SPACING 0x10
|
||||
#define CS_REGISTER 0x00
|
||||
#define DATA_REGISTER 0x04
|
||||
#define PUMP_REGISTER 0x08
|
||||
#define SPI(x, y) (MEMIO32 (SPI_BASE+(x*SPI_SPACING) + y))
|
||||
#define SPI_CS(x) (MEMIO32 (SPI_BASE+(x*SPI_SPACING) + CS_REGISTER)) /* CS bits are write-only, but bit 15 reads as the SPI busy signal */
|
||||
#define SPI_DATA(x) (MEMIO32 (SPI_BASE+(x*SPI_SPACING) + DATA_REGISTER)) /* Blocks on both reads and writes, making BUSY signal redundant. */
|
||||
#define SPI_PUMP(x) (MEMIO32 (SPI_BASE+(x*SPI_SPACING) + PUMP_REGISTER)) /* Push 16-bits through SPI in one instruction */
|
||||
#define SPI_SET_CS(x,y) {while((SPI_CS(x)&(1<<SPI_BUSY))); SPI_CS(x)=(y);}
|
||||
#define SPI_CS_SD 0
|
||||
#define SPI_FAST 8
|
||||
#define SPI_BUSY 15
|
||||
|
||||
// PS2
|
||||
#define PS2_BASE IO_ADDR_PERIPHERALS + 0xE00
|
||||
#define PS2_0 0
|
||||
#define PS2_1 1
|
||||
#define PS2_SPACING 0x10
|
||||
#define PS2_KEYBOARD_REGISTER 0
|
||||
#define PS2_MOUSE_REGISTER 0x4
|
||||
#define PS2(x, y) (MEMIO32 (PS2_BASE+(x*0x10) + y))
|
||||
#define PS2_KEYBOARD(x) (MEMIO32 (PS2_BASE+(x*0x10) + PS2_KEYBOARD_REGISTER))
|
||||
#define PS2_MOUSE(x) (MEMIO32 (PS2_BASE+(x*0x10) + PS2_MOUSE_REGISTER))
|
||||
#define BIT_PS2_RECV 11
|
||||
#define BIT_PS2_CTS 10
|
||||
|
||||
// SoC Configuration registers.
|
||||
#define SOCCFG_BASE IO_ADDR_PERIPHERALS + 0xF00
|
||||
// Registers
|
||||
#define SOCCFG_M68K_ID 0x00 // ID of the instantiated M68000
|
||||
#define SOCCFG_SYSFREQ 0x04 // System Clock Frequency in MHz x 10 (ie. 100MHz = 1000)
|
||||
#define SOCCFG_MEMFREQ 0x08 // Sysbus SDRAM Clock Frequency in MHz x 10 (ie. 100MHz = 1000)
|
||||
#define SOCCFG_WBMEMFREQ 0x0c // Wishbone SDRAM Clock Frequency in MHz x 10 (ie. 100MHz = 1000)
|
||||
#define SOCCFG_DEVIMPL 0x10 // Bit map of devices implemented in SOC.
|
||||
#define SOCCFG_BRAMADDR 0x14 // Address of Block RAM.
|
||||
#define SOCCFG_BRAMSIZE 0x18 // Size of Block RAM.
|
||||
#define SOCCFG_RAMADDR 0x1c // Address of RAM (additional BRAM, DRAM etc).
|
||||
#define SOCCFG_RAMSIZE 0x20 // Size of RAM.
|
||||
#define SOCCFG_BRAMINSNADDR 0x24 // Address of dedicated instruction Block RAM.
|
||||
#define SOCCFG_BRAMINSNSIZE 0x28 // Size of dedicated instruction Block RAM.
|
||||
#define SOCCFG_SDRAMADDR 0x2c // Address of SDRAM.
|
||||
#define SOCCFG_SDRAMSIZE 0x30 // Size of SDRAM.
|
||||
#define SOCCFG_WBSDRAMADDR 0x34 // Address of Wishbone SDRAM.
|
||||
#define SOCCFG_WBSDRAMSIZE 0x38 // Size of Wishbone SDRAM.
|
||||
#define SOCCFG_CPURSTADDR 0x3c // Address CPU executes after a RESET.
|
||||
#define SOCCFG_CPUMEMSTART 0x40 // Start address of Memory containing BIOS/Microcode for CPU.
|
||||
#define SOCCFG_STACKSTART 0x44 // Start address of Memory for Stack use.
|
||||
// Implementation bits.
|
||||
#define IMPL_WB 0x00400000
|
||||
#define IMPL_WB_SDRAM 0x00200000
|
||||
#define IMPL_WB_I2C 0x00100000
|
||||
#define IMPL_BRAM 0x00080000
|
||||
#define IMPL_RAM 0x00040000
|
||||
#define IMPL_INSN_BRAM 0x00020000
|
||||
#define IMPL_SDRAM 0x00010000
|
||||
#define IMPL_IOCTL 0x00008000
|
||||
#define IMPL_PS2 0x00004000
|
||||
#define IMPL_SPI 0x00002000
|
||||
#define IMPL_SD 0x00001000
|
||||
#define IMPL_SD_DEVICE_CNT 0x00000C00
|
||||
#define IMPL_INTRCTL 0x00000200
|
||||
#define IMPL_INTRCTL_CNT 0x000001F0
|
||||
#define IMPL_TIMER1 0x00000008
|
||||
#define IMPL_TIMER1_TIMER_CNT 0x00000007
|
||||
#define IMPL_SOCCFG 0x0000000a
|
||||
// Test macros
|
||||
#define IS_IMPL_WB ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_WB) >> 22
|
||||
#define IS_IMPL_WB_SDRAM ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_WB_SDRAM) >> 21
|
||||
#define IS_IMPL_WB_I2C ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_WB_I2C) >> 20
|
||||
#define IS_IMPL_BRAM ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_BRAM) >> 19
|
||||
#define IS_IMPL_RAM ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_RAM) >> 18
|
||||
#define IS_IMPL_INSN_BRAM ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_INSN_BRAM) >> 17
|
||||
#define IS_IMPL_SDRAM ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_SDRAM) >> 16
|
||||
#define IS_IMPL_IOCTL ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_IOCTL) >> 15
|
||||
#define IS_IMPL_PS2 ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_PS2) >> 14
|
||||
#define IS_IMPL_SPI ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_SPI) >> 13
|
||||
#define IS_IMPL_SD ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_SD) >> 12
|
||||
#define SOCCFG_SD_DEVICES ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_SD_DEVICE_CNT) >> 10
|
||||
#define IS_IMPL_INTRCTL ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_INTRCTL) >> 9
|
||||
#define SOCCFG_INTRCTL_CHANNELS ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_INTRCTL_CNT) >> 4
|
||||
#define IS_IMPL_TIMER1 ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_TIMER1) >> 3
|
||||
#define SOCCFG_TIMER1_TIMERS ((MEMIO32 (SOCCFG_BASE + SOCCFG_DEVIMPL)) & IMPL_TIMER1_TIMER_CNT)
|
||||
#define IS_IMPL_SOCCFG (MEMIO32 (SOCCFG_BASE + SOCCFG_M68K_ID)) >> 28 & IMPL_SOCCFG
|
||||
#define SOCCFG(x) (MEMIO32 (SOCCFG_BASE + x))
|
||||
|
||||
// -------------------------------
|
||||
// Wishbone Peripheral definition.
|
||||
// -------------------------------
|
||||
|
||||
// I2C Master Controller.
|
||||
#define I2C_BASE IO_ADDR_WB_PERIPHERALS + 0x000
|
||||
#define I2C0 0
|
||||
#define I2C1 1
|
||||
#define I2C2 2
|
||||
#define I2C3 3
|
||||
#define I2C_SPACING 0x10
|
||||
#define I2C_PRE_LOW_REGISTER 0x00 // Low byte clock prescaler register
|
||||
#define I2C_PRE_HI_REGISTER 0x01 // High byte clock prescaler register
|
||||
#define I2C_CTRL_REGISTER 0x02 // Control register
|
||||
#define I2C_TX_REGISTER 0x03 // Transmit byte register
|
||||
#define I2C_CMD_REGISTER 0x04 // Command register
|
||||
#define I2C_RX_REGISTER 0x03 // Receive byte register
|
||||
#define I2C_STATUS_REGISTER 0x04 // Status register
|
||||
#define I2C(x, y) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + y))
|
||||
#define I2C_PRE_LOW(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_PRE_LOW_REGISTER))
|
||||
#define I2C_PRE_HI(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_PRE_HI_REGISTER))
|
||||
#define I2C_CTRL(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_CTRL_REGISTER))
|
||||
#define I2C_TX(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_TX_REGISTER))
|
||||
#define I2C_CMD(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_CMD_REGISTER))
|
||||
#define I2C_RX(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_RX_REGISTER))
|
||||
#define I2C_STATUS(x) (MEMIO32 (I2C_BASE+(x*I2C_SPACING) + I2C_STATUS_REGISTER))
|
||||
#define I2C_EN (1<<7) // Core enable bit:
|
||||
// 1 - core is enabled
|
||||
// 0 - core is disabled
|
||||
#define OC_I2C_IEN (1<<6) // Interrupt enable bit
|
||||
// 1 - Interrupt enabled
|
||||
// 0 - Interrupt disabled
|
||||
// Other bits in CR are reserved
|
||||
#define I2C_STA (1<<7) // Generate (repeated) start condition
|
||||
#define I2C_STO (1<<6) // Generate stop condition
|
||||
#define I2C_RD (1<<5) // Read from slave
|
||||
#define I2C_WR (1<<4) // Write to slave
|
||||
#define I2C_ACK (1<<3) // Acknowledge from slave
|
||||
// 1 - ACK
|
||||
// 0 - NACK
|
||||
#define I2C_IACK (1<<0) // Interrupt acknowledge
|
||||
#define I2C_RXACK (1<<7) // ACK received from slave
|
||||
// 1 - ACK
|
||||
// 0 - NACK
|
||||
#define I2C_BUSY (1<<6) // Busy bit
|
||||
#define I2C_TIP (1<<1) // Transfer in progress
|
||||
#define I2C_IF (1<<0) // Interrupt flag
|
||||
#define I2C_IS_SET(reg,bitmask) ((reg)&(bitmask))
|
||||
#define I2C_IS_CLEAR(reg,bitmask) (!(I2C_IS_SET(reg,bitmask)))
|
||||
#define I2C_BITSET(reg,bitmask) ((reg)|(bitmask))
|
||||
#define I2C_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask)))
|
||||
#define I2C_BITTOGGLE(reg,bitmask) ((reg)^(bitmask))
|
||||
#define I2C_REGMOVE(reg,value) ((reg)=(value))
|
||||
|
||||
// State definitions.
|
||||
#define INPUT 1
|
||||
#define OUTPUT 0
|
||||
#define HIGH 1
|
||||
#define LOW 0
|
||||
|
||||
// Prototypes.
|
||||
void setupSoCConfig(void);
|
||||
void showSoCConfig(void);
|
||||
void printM68KId(uint32_t);
|
||||
|
||||
// Configuration values.
|
||||
typedef struct
|
||||
{
|
||||
uint32_t addrInsnBRAM;
|
||||
uint32_t sizeInsnBRAM;
|
||||
uint32_t addrBRAM;
|
||||
uint32_t sizeBRAM;
|
||||
uint32_t addrRAM;
|
||||
uint32_t sizeRAM;
|
||||
uint32_t addrSDRAM;
|
||||
uint32_t sizeSDRAM;
|
||||
uint32_t addrWBSDRAM;
|
||||
uint32_t sizeWBSDRAM;
|
||||
uint32_t resetVector;
|
||||
uint32_t cpuMemBaseAddr;
|
||||
uint32_t stackStartAddr;
|
||||
uint16_t m68kId;
|
||||
uint32_t sysFreq;
|
||||
uint32_t memFreq;
|
||||
uint32_t wbMemFreq;
|
||||
uint8_t implSoCCFG;
|
||||
uint8_t implWB;
|
||||
uint8_t implWBSDRAM;
|
||||
uint8_t implWBI2C;
|
||||
uint8_t implInsnBRAM;
|
||||
uint8_t implBRAM;
|
||||
uint8_t implRAM;
|
||||
uint8_t implSDRAM;
|
||||
uint8_t implIOCTL;
|
||||
uint8_t implPS2;
|
||||
uint8_t implSPI;
|
||||
uint8_t implSD;
|
||||
uint8_t sdCardNo;
|
||||
uint8_t implIntrCtl;
|
||||
uint8_t intrChannels;
|
||||
uint8_t implTimer1;
|
||||
uint8_t timer1No;
|
||||
} SOC_CONFIG;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -481,7 +481,7 @@ static t_helpstruct helpTable[] = {
|
||||
{ CMD_MEM_CLEAR, "<start> <end> [<word>]", "Clear memory" },
|
||||
{ CMD_MEM_COPY, "<start> <end> <dst addr>", "Copy memory" },
|
||||
{ CMD_MEM_DIFF, "<start> <end> <cmp addr>", "Compare memory" },
|
||||
{ CMD_MEM_DUMP, "[<start> [<end>] [<size>]]", "Dump memory" },
|
||||
{ CMD_MEM_DUMP, "[<start> [<len>] [<width>]]", "Dump memory" },
|
||||
{ CMD_MEM_EDIT_BYTES, "<addr> <byte> [...]", "Edit memory (Bytes)" },
|
||||
{ CMD_MEM_EDIT_HWORD, "<addr> <h-word> [...]", "Edit memory (H-Word)" },
|
||||
{ CMD_MEM_EDIT_WORD, "<addr> <word> [...]", "Edit memory (Word)" },
|
||||
|
||||
@@ -27,16 +27,23 @@
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#########################################################################################################
|
||||
ifeq ($(__ZPU__),)
|
||||
BASEDIR = $(CURDIR)/..
|
||||
TOOLSPATH = $(BASEDIR)/tools
|
||||
COMPILERPATH = $(TOOLSPATH)/arm/bin
|
||||
BASE = $(abspath $(COMPILERPATH))/arm-none-eabi
|
||||
else
|
||||
ifeq ($(__ZPU__),1)
|
||||
BASEDIR = $(CURDIR)/..
|
||||
TOOLSPATH = /opt/zpu
|
||||
COMPILERPATH = $(TOOLSPATH)/bin
|
||||
BASE = zpu-elf
|
||||
else ifeq ($(__K64F__),1)
|
||||
BASEDIR = $(CURDIR)/..
|
||||
TOOLSPATH = $(BASEDIR)/tools
|
||||
COMPILERPATH = $(TOOLSPATH)/arm/bin
|
||||
BASE = $(abspath $(COMPILERPATH))/arm-none-eabi
|
||||
else ifeq ($(__M68K__),1)
|
||||
BASEDIR = $(CURDIR)/..
|
||||
TOOLSPATH = /usr
|
||||
COMPILERPATH = $(TOOLSPATH)/bin
|
||||
BASE = m68k-linux-gnu
|
||||
else
|
||||
$(error Undefined CPU architecture.)
|
||||
endif
|
||||
CC = $(BASE)-gcc
|
||||
CXX = $(BASE)-g++
|
||||
@@ -134,14 +141,17 @@ ZPUOPTS += -mmult \
|
||||
|
||||
# Build time flags dependent on CPU target.
|
||||
CFLAGS = -I. -I$(UMLIBC_DIR)/include -I$(COMMON_DIR) -I$(INCLUDE_DIR) -I$(TEENSY35_DIR)
|
||||
ifeq ($(__ZPU__),)
|
||||
CFLAGS += -D__K64F__
|
||||
CFLAGS += -fno-builtin -mlong-calls -mthumb -MMD -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
else
|
||||
ifeq ($(__ZPU__),1)
|
||||
CFLAGS += -D__ZPU__
|
||||
CFLAGS += -O3
|
||||
CFLAGS += $(ZPUOPTS)
|
||||
CFLAGS += --std=gnu99 # Use C99 + GNU extensions to provide anonymous unions.
|
||||
else ifeq ($(__K64F__),1)
|
||||
CFLAGS += -D__K64F__
|
||||
CFLAGS += -fno-builtin -mlong-calls -mthumb -MMD -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
else ifeq ($(__M68K__),1)
|
||||
CFLAGS += -D__M68K__
|
||||
CFLAGS += -fno-builtin -g --std=gnu99
|
||||
endif
|
||||
|
||||
# Linker flags.
|
||||
@@ -149,10 +159,12 @@ LDFLAGS = -static
|
||||
|
||||
# Library name is suffixed by CPU.
|
||||
#
|
||||
ifeq ($(__ZPU__),)
|
||||
LIBTRG = -k64f
|
||||
else
|
||||
ifeq ($(__ZPU__),1)
|
||||
LIBTRG = -zpu
|
||||
else ifeq ($(__K64F__),1)
|
||||
LIBTRG = -k64f
|
||||
else ifeq ($(__M68K__),1)
|
||||
LIBTRG = -m68k
|
||||
endif
|
||||
|
||||
|
||||
|
||||
@@ -115,10 +115,10 @@ typedef unsigned long long int uint64_t;
|
||||
|
||||
typedef int int8_t __attribute__((__mode__(__QI__)));
|
||||
typedef unsigned int uint8_t __attribute__((__mode__(__QI__)));
|
||||
typedef int int16_t __attribute__ ((__mode__ (__HI__)));
|
||||
typedef unsigned int uint16_t __attribute__ ((__mode__ (__HI__)));
|
||||
typedef int int32_t __attribute__ ((__mode__ (__SI__)));
|
||||
typedef unsigned int uint32_t __attribute__ ((__mode__ (__SI__)));
|
||||
typedef int int16_t __attribute__((__mode__ (__HI__)));
|
||||
typedef unsigned int uint16_t __attribute__((__mode__ (__HI__)));
|
||||
typedef int int32_t __attribute__((__mode__ (__SI__)));
|
||||
typedef unsigned int uint32_t __attribute__((__mode__ (__SI__)));
|
||||
typedef int int64_t __attribute__((__mode__(__DI__)));
|
||||
typedef unsigned int uint64_t __attribute__((__mode__(__DI__)));
|
||||
|
||||
|
||||
@@ -97,6 +97,17 @@ typedef int (*__compar_fn_t)(const void *, const void *);
|
||||
|
||||
#endif
|
||||
|
||||
#if __GNUC__ > 5
|
||||
__inline__ void abort(void) __ATTR_NORETURN__;
|
||||
|
||||
/** The abort() function causes abnormal program termination to occur.
|
||||
In the limited AVR environment, execution is effectively halted
|
||||
by entering an infinite loop. */
|
||||
__inline__ void abort(void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
#else
|
||||
extern __inline__ void abort(void) __ATTR_NORETURN__;
|
||||
|
||||
/** The abort() function causes abnormal program termination to occur.
|
||||
@@ -107,6 +118,7 @@ abort(void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** The abs() function computes the absolute value of the integer \c i.
|
||||
\note The abs() and labs() functions are builtins of gcc.
|
||||
@@ -252,12 +264,19 @@ extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base);
|
||||
|
||||
\code strtol(nptr, (char **)NULL, 10); \endcode
|
||||
*/
|
||||
extern __inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
extern __inline__ long
|
||||
atol(const char *__nptr)
|
||||
#if __GNUC__ > 5
|
||||
__inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
__inline__ long atol(const char *__nptr)
|
||||
{
|
||||
return strtol(__nptr, (char **) 0, 10);
|
||||
}
|
||||
#else
|
||||
extern __inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
extern __inline__ long atol(const char *__nptr)
|
||||
{
|
||||
return strtol(__nptr, (char **) 0, 10);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
The atoi() function converts the initial portion of the string
|
||||
|
||||
Binary file not shown.
BIN
libraries/lib/libimath2-m68k.a
Normal file
BIN
libraries/lib/libimath2-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
libraries/lib/libumansi-m68k.a
Normal file
BIN
libraries/lib/libumansi-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
libraries/lib/libummath-m68k.a
Normal file
BIN
libraries/lib/libummath-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
libraries/lib/libummathf-m68k.a
Normal file
BIN
libraries/lib/libummathf-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
libraries/lib/libummisc-m68k.a
Normal file
BIN
libraries/lib/libummisc-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
libraries/lib/libumstdio-m68k.a
Normal file
BIN
libraries/lib/libumstdio-m68k.a
Normal file
Binary file not shown.
Binary file not shown.
@@ -115,10 +115,10 @@ typedef unsigned long long int uint64_t;
|
||||
|
||||
typedef int int8_t __attribute__((__mode__(__QI__)));
|
||||
typedef unsigned int uint8_t __attribute__((__mode__(__QI__)));
|
||||
typedef int int16_t __attribute__ ((__mode__ (__HI__)));
|
||||
typedef unsigned int uint16_t __attribute__ ((__mode__ (__HI__)));
|
||||
typedef int int32_t __attribute__ ((__mode__ (__SI__)));
|
||||
typedef unsigned int uint32_t __attribute__ ((__mode__ (__SI__)));
|
||||
typedef int int16_t __attribute__((__mode__ (__HI__)));
|
||||
typedef unsigned int uint16_t __attribute__((__mode__ (__HI__)));
|
||||
typedef int int32_t __attribute__((__mode__ (__SI__)));
|
||||
typedef unsigned int uint32_t __attribute__((__mode__ (__SI__)));
|
||||
typedef int int64_t __attribute__((__mode__(__DI__)));
|
||||
typedef unsigned int uint64_t __attribute__((__mode__(__DI__)));
|
||||
|
||||
|
||||
@@ -97,6 +97,17 @@ typedef int (*__compar_fn_t)(const void *, const void *);
|
||||
|
||||
#endif
|
||||
|
||||
#if __GNUC__ > 5
|
||||
__inline__ void abort(void) __ATTR_NORETURN__;
|
||||
|
||||
/** The abort() function causes abnormal program termination to occur.
|
||||
In the limited AVR environment, execution is effectively halted
|
||||
by entering an infinite loop. */
|
||||
__inline__ void abort(void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
#else
|
||||
extern __inline__ void abort(void) __ATTR_NORETURN__;
|
||||
|
||||
/** The abort() function causes abnormal program termination to occur.
|
||||
@@ -107,6 +118,7 @@ abort(void)
|
||||
{
|
||||
for (;;);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** The abs() function computes the absolute value of the integer \c i.
|
||||
\note The abs() and labs() functions are builtins of gcc.
|
||||
@@ -252,12 +264,19 @@ extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base);
|
||||
|
||||
\code strtol(nptr, (char **)NULL, 10); \endcode
|
||||
*/
|
||||
extern __inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
extern __inline__ long
|
||||
atol(const char *__nptr)
|
||||
#if __GNUC__ > 5
|
||||
__inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
__inline__ long atol(const char *__nptr)
|
||||
{
|
||||
return strtol(__nptr, (char **) 0, 10);
|
||||
}
|
||||
#else
|
||||
extern __inline__ long atol(const char *__nptr) __ATTR_PURE__;
|
||||
extern __inline__ long atol(const char *__nptr)
|
||||
{
|
||||
return strtol(__nptr, (char **) 0, 10);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
The atoi() function converts the initial portion of the string
|
||||
|
||||
27949
rtl/IOCP_zOS_BootROM.vhd
27949
rtl/IOCP_zOS_BootROM.vhd
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
27949
rtl/zOS_BootROM.vhd
27949
rtl/zOS_BootROM.vhd
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
103766
rtl/zOS_DualPortBootBRAM.vhd
103766
rtl/zOS_DualPortBootBRAM.vhd
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -34,6 +34,7 @@ MEMORY
|
||||
{
|
||||
BOOT (rx) : ORIGIN = BOOTADDR, LENGTH = BOOTLEN /* Boot section which shouldnt exist in an app, so a link trap as warning */
|
||||
CODE (rx) : ORIGIN = APPSTART, LENGTH = APPLEN /* Up to the end of the RAM first less stack space */
|
||||
BSS (rx) : ORIGIN = 0x130000, LENGTH = 0x4000
|
||||
HEAP (rx) : ORIGIN = APP_HEAP_STARTADDR, LENGTH = APP_HEAP_SIZE /* Allocated heap space within the application. */
|
||||
STACK (rx) : ORIGIN = APP_STACK_STARTADDR, LENGTH = APP_STACK_SIZE /* Allocated stack space within the application. */
|
||||
}
|
||||
@@ -97,9 +98,11 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
__data_end__ = . ;
|
||||
} >CODE
|
||||
_dataend = . ;
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
_bssstart = . ;
|
||||
.bss :
|
||||
{
|
||||
__bss_start = . ;
|
||||
@@ -110,8 +113,8 @@ SECTIONS
|
||||
_ebss = .;
|
||||
__bss_end__ = . ;
|
||||
_end = . ;
|
||||
} >CODE
|
||||
_dataend = . ;
|
||||
} >BSS
|
||||
_bssend = . ;
|
||||
|
||||
/* Variable expanded by build.sh */
|
||||
.heap APP_HEAP_STARTADDR:
|
||||
|
||||
@@ -1,130 +0,0 @@
|
||||
/********************************************************************************************************
|
||||
*
|
||||
* Name: zos_zpu.tmpl
|
||||
* Created: April 2020
|
||||
* Author(s): Philip Smart
|
||||
* Description: zOS linker map.
|
||||
* This is the linker map for the zOS operating firmware on the ZPU. It defines
|
||||
* where the firmware is loaded, size and location. This will be adapted depending
|
||||
* upon wether the IOCP bootloader is used or zOS runs as the sole bootloader and
|
||||
operating system.
|
||||
*
|
||||
* Credits:
|
||||
* Copyright: (c) 2019-20 Philip Smart <philip.smart@net2net.org>
|
||||
*
|
||||
* History: April 2020 - Initial script based on ZPU linker script.
|
||||
*
|
||||
********************************************************************************************************
|
||||
* This source file is free software: you can redistribute it and#or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This source file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http:#www.gnu.org;licenses;>.
|
||||
********************************************************************************************************/
|
||||
|
||||
/* Memory Definitions for a ZPU application running within BlockRAM/RAM tagged as ROM.*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
BOOT (rx) : ORIGIN = 0x00001000, LENGTH = 0x000200 /* Boot section which shouldnt exist in an app, so a link trap as warning */
|
||||
CODE (rx) : ORIGIN = 0x00001200, LENGTH = 0x0000AE00 /* Up to the end of the RAM first less stack space */
|
||||
}
|
||||
|
||||
/* Section Definitions */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* first section is .fixed_vectors which is used for startup code */
|
||||
. = 0x00001000;
|
||||
_ramstart = . ;
|
||||
__boot_start__ = . ;
|
||||
.fixed_vectors :
|
||||
{
|
||||
KEEP(*(.fixed_vectors)) /* Seed section - allows -gc-sections */
|
||||
}>BOOT
|
||||
__boot_end__ = . ;
|
||||
|
||||
/* Remaining code sections */
|
||||
. = ALIGN(4);
|
||||
__text_start__ = . ;
|
||||
.text :
|
||||
{
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
. = ALIGN(4);
|
||||
__ctors_start__ = . ;
|
||||
KEEP(*(.ctors))
|
||||
KEEP(*(.ctors.*))
|
||||
__ctors_end__ = . ;
|
||||
. = ALIGN(4);
|
||||
__dtors_start__ = . ;
|
||||
KEEP(*(.dtors))
|
||||
KEEP(*(.dtors.*))
|
||||
__dtors_end__ = . ;
|
||||
} >CODE
|
||||
__text_end__ = . ;
|
||||
|
||||
/* .rodata section which is used for read-only data (constants) */
|
||||
. = ALIGN(4);
|
||||
__rodata_start__ = . ;
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
} >CODE
|
||||
. = ALIGN(4);
|
||||
__rodata_end__ = . ;
|
||||
_ramend = . ;
|
||||
|
||||
/* .data section which is used for initialized data. */
|
||||
. = ALIGN(4);
|
||||
_datastart = . ;
|
||||
.data :
|
||||
{
|
||||
_data = . ;
|
||||
__data_start__ = . ;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
SORT(CONSTRUCTORS)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = . ;
|
||||
} >CODE
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
__bss_start = . ;
|
||||
__bss_start__ = . ;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
__bss_end__ = . ;
|
||||
_end = . ;
|
||||
} >CODE
|
||||
_dataend = . ;
|
||||
|
||||
__HeapBase = .;
|
||||
__HeapLimit = 0x0000DFF8 - 0x400;
|
||||
|
||||
/* Top of stack pointer, used for sbrk validation. */
|
||||
_stack = 0x0000DFF8;
|
||||
|
||||
/* Debug information */
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.comment : { *(.comment) }
|
||||
}
|
||||
|
||||
11
zOS/Makefile
11
zOS/Makefile
@@ -11,11 +11,12 @@
|
||||
## as part of the tranZPUter SW project.
|
||||
##
|
||||
## Credits:
|
||||
## Copyright: (c) 2019-2020 Philip Smart <philip.smart@net2net.org>
|
||||
## Copyright: (c) 2019-2021 Philip Smart <philip.smart@net2net.org>
|
||||
##
|
||||
## History: July 2019 - Initial Makefile created for template use.
|
||||
## April 2020 - Split from the latest ZPUTA and added K64F logic to support the
|
||||
## tranZPUter SW board.
|
||||
## April 2020 - Split from the latest ZPUTA and added K64F logic to support the
|
||||
## tranZPUter SW board.
|
||||
## April 2021 - Added M68000
|
||||
##
|
||||
## Notes: Optional component enables:
|
||||
## USELOADB - The Byte write command is implemented in hw#sw so use it.
|
||||
@@ -42,6 +43,8 @@ ifeq ($(__K64F__),1)
|
||||
include $(ZOS_DIR)/Makefile.k64f
|
||||
else ifeq ($(__ZPU__),1)
|
||||
include $(ZOS_DIR)/Makefile.zpu
|
||||
else ifeq ($(__M68K__),1)
|
||||
include $(ZOS_DIR)/Makefile.m68k
|
||||
else
|
||||
$(error Please run using __K64F__=1 or __ZPU__=1 according to target processor)
|
||||
$(error Please run using __K64F__=1, __ZPU__=1 or __M68K__=1 according to target processor)
|
||||
endif
|
||||
|
||||
367
zOS/Makefile.m68k
Normal file
367
zOS/Makefile.m68k
Normal file
@@ -0,0 +1,367 @@
|
||||
########################################################################################################
|
||||
##
|
||||
## Name: Makefile.m68k
|
||||
## Created: January 2019
|
||||
## Author(s): Philip Smart
|
||||
## Description: zOS - zpu Operating System
|
||||
## This makefile builds the zOS application the purpose of which is to provide test,
|
||||
## monitoring tools and an execution environment for applications for the M68000 and
|
||||
## devices within the SoC.
|
||||
## zOS more recently upgraded to handle the K64F and embedded M68000 on the
|
||||
## tranZPUter SW-700 v1.3a board.
|
||||
##
|
||||
## Credits:
|
||||
## Copyright: (c) 2019-2021 Philip Smart <philip.smart@net2net.org>
|
||||
##
|
||||
## History: January 2019 - Initial script written for the STORM processor then changed to the ZPU.
|
||||
## April 2020 - Split from the latest ZPUTA and added K64F logic to support the
|
||||
## tranZPUter SW board.
|
||||
## December 2020 - Additions to support zOS running as host on Sharp MZ hardware.
|
||||
##
|
||||
## Notes: Optional component enables:
|
||||
## USELOADB - The Byte write command is implemented in hw#sw so use it.
|
||||
## USE_BOOT_ROM - The target is ROM so dont use initialised data.
|
||||
## MINIMUM_FUNTIONALITY - Minimise functionality to limit code size.
|
||||
## __SD_CARD__ - Add the SDCard logic.
|
||||
##
|
||||
#########################################################################################################
|
||||
## This source file is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published
|
||||
## by the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This source file is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#########################################################################################################
|
||||
BASE = m68k-linux-gnu
|
||||
CC = $(BASE)-gcc
|
||||
CXX = $(BASE)-g++
|
||||
LD = $(BASE)-gcc
|
||||
AS = $(BASE)-as
|
||||
CP = $(BASE)-objcopy
|
||||
DUMP = $(BASE)-objdump
|
||||
|
||||
# Addresses where the zOS base program loads and where apps load and execute.
|
||||
# With IOCP. These are defaults as they should be overriden by caller.
|
||||
ifeq ($(OS_BASEADDR),)
|
||||
OS_BASEADDR = 0x01000
|
||||
endif
|
||||
ifeq ($(OS_APPADDR),)
|
||||
OS_APPADDR = 0x0C000
|
||||
endif
|
||||
|
||||
BASEDIR = $(CURDIR)/..
|
||||
SWDIR = $(BASEDIR)/
|
||||
ROMGEN = $(SWDIR)/tools/zpugen
|
||||
IOCPDIR = $(SWDIR)/iocp
|
||||
|
||||
# we use startup assembly and linkers from here
|
||||
STARTUP_DIR = $(SWDIR)/startup
|
||||
|
||||
# we fetch RAM prologue / epilogue from here
|
||||
RTL_DIR = $(BASEDIR)/rtl
|
||||
|
||||
# we use printf from here
|
||||
COMMON_DIR = $(SWDIR)/common
|
||||
UMM_DIR = $(SWDIR)/common/umm
|
||||
FATFS_DIR = $(SWDIR)/common/FatFS
|
||||
PFS_DIR = $(SWDIR)/common/PetitFS
|
||||
INCLUDE_DIR = $(SWDIR)/include
|
||||
LIB_DIR = $(SWDIR)/libraries/lib
|
||||
LIB_INCLUDE_DIR = $(SWDIR)/libraries/include
|
||||
|
||||
# Linker mapping file spec file.
|
||||
LINKMAPBOOTSTANDALONE = $(STARTUP_DIR)/zos_standalone_boot_in_bram.ld
|
||||
LINKMAPBOOTIOCP = $(STARTUP_DIR)/zos_with_iocp_in_bram.ld
|
||||
LINKMAPBOOTTINYIOCP = $(STARTUP_DIR)/zos_with_tiny_iocp_in_bram.ld
|
||||
LINKMAPRAM = $(STARTUP_DIR)/zos_as_app_in_ram.ld
|
||||
|
||||
# Working directory to build object files.
|
||||
BUILD_DIR = $(abspath $(CURDIR)/build)
|
||||
|
||||
# Startup files, RAM has no microcode, ROM has microcode.
|
||||
RAMSTARTUP_SRC = $(STARTUP_DIR)/ramcrt0.s
|
||||
RAMSTARTUP_OBJ = #$(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(RAMSTARTUP_SRC))
|
||||
ROMSTARTUP_SRC = $(STARTUP_DIR)/zosromcrt0.s
|
||||
ROMSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(ROMSTARTUP_SRC))
|
||||
|
||||
# List of source files for the OS.
|
||||
COMMON_SRC = $(COMMON_DIR)/utils.c $(COMMON_DIR)/uart.c $(COMMON_DIR)/m68k_soc.c $(COMMON_DIR)/interrupts.c $(COMMON_DIR)/ps2.c $(COMMON_DIR)/readline.c
|
||||
COMMON_SRC += #$(COMMON_DIR)/xprintf.c $(COMMON_DIR)/spi.c
|
||||
#COMMON_SRC += $(COMMON_DIR)/divsi3.c $(COMMON_DIR)/udivsi3.c $(COMMON_DIR)/modsi3.c $(COMMON_DIR)/umodsi3.c
|
||||
UMM_C_SRC = #$(UMM_DIR)/umm_malloc.c
|
||||
FATFS_SRC = $(FATFS_DIR)/sdmmc_zpu.c $(FATFS_DIR)/ff.c $(FATFS_DIR)/ffunicode.c
|
||||
PFS_SRC = $(PFS_DIR)/sdmmc_zpu.c $(PFS_DIR)/pff.c
|
||||
MAIN_SRC = $(CURDIR)/src/zOS.cpp
|
||||
ifeq ($(__SHARPMZ__),1)
|
||||
COMMON_SRC += $(COMMON_DIR)/sharpmz.c
|
||||
endif
|
||||
|
||||
# Expand to targets.
|
||||
SOURCES := $(MAIN_SRC:.cpp=.o) $(COMMON_SRC:.c=.o) $(UMM_C_SRC:.c=.o) $(FATFS_SRC:.c=.o)
|
||||
OBJS := $(foreach src,$(SOURCES), $(BUILD_DIR)/$(src))
|
||||
|
||||
|
||||
# Versions to build.
|
||||
MAIN_PRJ_TO_BOOT= zos_standalone_boot_in_bram
|
||||
MAIN_PRJ_IN_BOOT= zos_with_iocp_in_bram
|
||||
MAIN_PRJ_TINY_BOOT=zos_with_tiny_iocp_in_bram
|
||||
MAIN_PRJ_RAM = zos_as_app_in_ram
|
||||
|
||||
CFLAGS = -I. -I$(COMMON_DIR) -I$(FATFS_DIR) -I$(DHRY_DIR) -I$(CORE_DIR) -I$(INCLUDE_DIR) -I$(LIB_INCLUDE_DIR)
|
||||
CFLAGS += -nostartfiles -nostdlib -c -O3 -ffunction-sections -fdata-sections
|
||||
CFLAGS += -DOS_BASEADDR=$(OS_BASEADDR) -DOS_APPADDR=$(OS_APPADDR)
|
||||
CFLAGS += -D__M68K__ -D__ZOS__
|
||||
CFLAGS += -DUMM_BEST_FIT -DUMM_INFO -DUMM_DBG_LOG_LEVEL=0
|
||||
CFLAGS += --std=gnu99 # Use C99 + GNU extensions to provide anonymous unions.
|
||||
#
|
||||
# Allow local overrides to the HEAPADDR for certain applications.
|
||||
ifeq (,$(findstring __HEAPADDR__,$(CFLAGS)))
|
||||
ifeq ($(HEAPADDR),)
|
||||
CFLAGS += -D__HEAPADDR__=0xE000
|
||||
else
|
||||
CFLAGS += -D__HEAPADDR__=$(HEAPADDR)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Allow local overrides to the HEAPSIZE for certain applications.
|
||||
ifeq (,$(findstring __HEAPSIZE__,$(CFLAGS)))
|
||||
ifeq ($(HEAPSIZE),)
|
||||
CFLAGS += -D__HEAPSIZE__=0x1000
|
||||
else
|
||||
CFLAGS += -D__HEAPSIZE__=$(HEAPSIZE)
|
||||
endif
|
||||
endif
|
||||
ifeq ($(__SHARPMZ__),1)
|
||||
CFLAGS += -D__SHARPMZ__
|
||||
endif
|
||||
#
|
||||
# Enable debug output.
|
||||
OFLAGS += -DDEBUG
|
||||
# Assume loadb as implemented in hardware or software (time penalty).
|
||||
OFLAGS += -DUSELOADB
|
||||
# Dont allow an initialised DATA segment so binary can be located in ROM.
|
||||
#OFLAGS += -DUSE_BOOT_ROM
|
||||
# Remove functionality to create a minimal system for limited space.
|
||||
#OFLAGS += -DMINIMUM_FUNCTIONALITY
|
||||
|
||||
#
|
||||
# Enable SD Card functionality
|
||||
OFLAGS += -D__SD_CARD__
|
||||
FLAGS_STR = -DFLAGS_STR="$(CFLAGS)"
|
||||
LFLAGS = -nostartfiles -nostdlib -Wl,--gc-sections -Wl,--relax -O3 -L$(LIB_DIR) --std=gnu99 -D__M68K__
|
||||
LIBS = -lumstdio-m68k -lumansi-m68k -limath2-m68k -lummisc-m68k
|
||||
|
||||
# compiler options for C++ only
|
||||
CXXFLAGS = -std=gnu++98 -felide-constructors -fno-exceptions -fno-rtti
|
||||
#CXXFLAGS = -std=gnu++14 -felide-constructors -fno-exceptions -fno-rtti
|
||||
|
||||
#
|
||||
# Assembler flags.
|
||||
ASFLAGS = -I. -I$(COMMON_DIR) -I$(INCLUDE_DIR) -I$(STARTUP_DIR) --defsym OS_BASEADDR=$(OS_BASEADDR) --defsym OS_APPADDR=$(OS_APPADDR)
|
||||
#
|
||||
|
||||
# Our target.
|
||||
all: $(BUILD_DIR) $(MAIN_PRJ_TO_BOOT) $(ROMGEN) # $(MAIN_PRJ_IN_BOOT) $(MAIN_PRJ_TINY_BOOT) $(MAIN_PRJ_RAM) $(ROMGEN)
|
||||
#
|
||||
$(MAIN_PRJ_TO_BOOT): $(BUILD_DIR) $(MAIN_PRJ_TO_BOOT).bin $(MAIN_PRJ_TO_BOOT).srec $(MAIN_PRJ_TO_BOOT).rpt $(MAIN_PRJ_TO_BOOT).lss $(MAIN_PRJ_TO_BOOT).dmp $(MAIN_PRJ_TO_BOOT)_BOOTROM.vhd $(MAIN_PRJ_TO_BOOT)_COMBINEDBOOTROM.vhd $(MAIN_PRJ_TO_BOOT)_BOOTBRAM.vhd
|
||||
#
|
||||
$(MAIN_PRJ_IN_BOOT): $(BUILD_DIR) $(MAIN_PRJ_IN_BOOT).bin $(MAIN_PRJ_IN_BOOT).srec $(MAIN_PRJ_IN_BOOT).rpt $(MAIN_PRJ_IN_BOOT).lss $(MAIN_PRJ_IN_BOOT).dmp $(MAIN_PRJ_IN_BOOT)_BOOTROM.vhd $(MAIN_PRJ_IN_BOOT)_COMBINEDBOOTBRAM.vhd
|
||||
#
|
||||
$(MAIN_PRJ_TINY_BOOT): $(BUILD_DIR) $(MAIN_PRJ_TINY_BOOT).bin $(MAIN_PRJ_TINY_BOOT).rpt $(MAIN_PRJ_TINY_BOOT).lss $(MAIN_PRJ_TINY_BOOT).dmp
|
||||
#
|
||||
$(MAIN_PRJ_RAM): $(BUILD_DIR) $(MAIN_PRJ_RAM).bin $(MAIN_PRJ_RAM).srec $(MAIN_PRJ_RAM).rpt $(MAIN_PRJ_RAM).lss $(MAIN_PRJ_RAM).dmp $(MAIN_PRJ_RAM)_APPRAM.vhd $(MAIN_PRJ_RAM)_COMBINEDAPPRAM.vhd
|
||||
|
||||
clean:
|
||||
rm -fr $(BUILD_DIR)/*
|
||||
rm -f $(BUILD_DIR)/*.o *.hex *.lss *.elf *.map *.lst *.srec $(MAIN_PRJ_TO_BOOT) $(MAIN_PRJ_IN_BOOT).rom $(MAIN_PRJ_TINY_BOOT).rom $(MAIN_PRJ_RAM) *~ */*.o *.bin *.srec *.dmp *.vhd *.rpt
|
||||
|
||||
|
||||
# Convert ELF binary to bin file.
|
||||
%.bin: %.elf
|
||||
@$(CP) -O binary $< $@
|
||||
|
||||
# Convert ELF to srec format for serial upload.
|
||||
%.srec: %.elf
|
||||
@$(CP) -O srec $< $@
|
||||
|
||||
%.rpt: %.elf
|
||||
@echo ""
|
||||
@echo >$@ -n "Start of code:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ _ramstart
|
||||
@echo >>$@ -n " BOOT start:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ __boot_start__
|
||||
@echo >>$@ -n " end: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __boot_end__
|
||||
@echo >>$@ -n " TEXT start:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ __text_start__
|
||||
@echo >>$@ -n " end: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __text_end__
|
||||
@echo >>$@ -n " RODATA start:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ __rodata_start__
|
||||
@echo >>$@ -n " end: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __rodata_end__
|
||||
@echo >>$@ -n "End of code:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ _ramend
|
||||
@echo >>$@ -n "Start of data:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ _datastart
|
||||
@echo >>$@ -n " DATA start: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __data_start__
|
||||
@echo >>$@ -n " end: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __data_end__
|
||||
@echo >>$@ -n " BSS start: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __bss_start__
|
||||
@echo >>$@ -n " end: \t"
|
||||
@$(DUMP) -x $< | grep >>$@ __bss_end__
|
||||
@echo >>$@ -n "End of data:\t"
|
||||
@$(DUMP) -x $< | grep >>$@ _dataend
|
||||
@cat $@
|
||||
|
||||
%.dmp: %.elf
|
||||
@$(DUMP) -x $< >>$@
|
||||
|
||||
# Create extended listing file from ELF output file.
|
||||
# testing: option -C
|
||||
%.lss: %.elf
|
||||
@echo
|
||||
@$(DUMP) -h -S -C $< > $@
|
||||
|
||||
$(ROMGEN): $(SWDIR)/tools/src/zpugen.c
|
||||
gcc -o $(SWDIR)/tools/zpugen $(SWDIR)/tools/src/zpugen.c
|
||||
|
||||
# Put the boot code and app code into a ROM compatible with the Small, Medium and Flex CPUś
|
||||
%_BOOTROM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/dualportram/BootROM/' >zOS_BootROM.vhd <$(RTL_DIR)/rom_prologue.vhd
|
||||
@$(ROMGEN) 32 $*.bin 0 > ROMCODE.dat
|
||||
@cat ROMCODE.dat $(RTL_DIR)/rom_epilogue.vhd >> zOS_BootROM.vhd
|
||||
@cp zOS_BootROM.vhd $(RTL_DIR)/
|
||||
@rm ROMCOD*.dat zOS_BootROM.vhd
|
||||
@echo "zOS_BootROM.vhd updated."
|
||||
|
||||
%_COMBINEDBOOTROM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/dualportram/BootROM/' >IOCP_zOS_BootROM.vhd <$(RTL_DIR)/rom_prologue.vhd
|
||||
@$(ROMGEN) 32 $(IOCPDIR)/iocp.bin 0 > ROMCODE.dat
|
||||
@$(ROMGEN) 32 $*.bin 2048 > APPCODE.dat
|
||||
@cat ROMCODE.dat APPCODE.dat $(RTL_DIR)/rom_epilogue.vhd >> IOCP_zOS_BootROM.vhd
|
||||
@cp IOCP_zOS_BootROM.vhd $(RTL_DIR)/
|
||||
@rm ROMCOD*.dat APPCODE*.dat IOCP_zOS_BootROM.vhd
|
||||
@echo "IOCP_zOS_BootROM.vhd updated."
|
||||
|
||||
# Put the boot code into a BRAM used for boot code.
|
||||
%_BOOTBRAM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/byteaddr_dp_32bit_bram/DualPortBootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_dp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BA 32 $*.bin /tmp/zpu_work.tmp 0 > zOS_DualPortBootBRAM.vhd
|
||||
@cp zOS_DualPortBootBRAM.vhd $(RTL_DIR)/
|
||||
@sed 's/byteaddr_dp_3264bit_bram/DualPort3264BootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_dp_3264bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BA 64 $*.bin /tmp/zpu_work.tmp 0 > zOS_DualPort3264BootBRAM.vhd
|
||||
@cp zOS_DualPort3264BootBRAM.vhd $(RTL_DIR)/
|
||||
@sed 's/zpu_soc_pkg/softZPU_pkg/' > $(RTL_DIR)/TZSW_DualPortBootBRAM.vhd < zOS_DualPortBootBRAM.vhd
|
||||
@sed 's/zpu_soc_pkg/softZPU_pkg/' > $(RTL_DIR)/TZSW_DualPort3264BootBRAM.vhd < zOS_DualPort3264BootBRAM.vhd
|
||||
@sed 's/byteaddr_sp_32bit_bram/SinglePortBootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_sp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BA 32 $*.bin /tmp/zpu_work.tmp 0 > zOS_SinglePortBootBRAM.vhd
|
||||
@rm -f /tmp/zpu_work.tmp
|
||||
@cp zOS_SinglePortBootBRAM.vhd $(RTL_DIR)/
|
||||
@sed 's/zpu_soc_pkg/softZPU_pkg/' > $(RTL_DIR)/TZSW_SinglePortBootBRAM.vhd < zOS_SinglePortBootBRAM.vhd
|
||||
@rm zOS_DualPortBootBRAM.vhd zOS_DualPort3264BootBRAM.vhd zOS_SinglePortBootBRAM.vhd
|
||||
@echo "zOS_DualPortBootBRAM.vhd, zOS_DualPort3264BootBRAM.vhd and zOS_SinglePortBootBRAM updated."
|
||||
@echo ""
|
||||
|
||||
# Put the boot code and app code into a BRAM used for both boot code and application, ie. one block of BRAM.
|
||||
%_COMBINEDBOOTBRAM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/byteaddr_dp_32bit_bram/DualPortBootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_dp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BC 32 $(IOCPDIR)/iocp.bin 0 $*.bin 2048 /tmp/zpu_work.tmp > IOCP_zOS_DualPortBootBRAM.vhd
|
||||
@sed 's/byteaddr_dp_3264bit_bram/DualPort3264BootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_dp_3264bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BC 64 $(IOCPDIR)/iocp.bin 0 $*.bin 2048 /tmp/zpu_work.tmp > IOCP_zOS_DualPort3264BootBRAM.vhd
|
||||
@rm -f /tmp/zpu_work.tmp
|
||||
@cp IOCP_zOS_DualPortBootBRAM.vhd $(RTL_DIR)/
|
||||
@cp IOCP_zOS_DualPort3264BootBRAM.vhd $(RTL_DIR)/
|
||||
@sed 's/byteaddr_sp_32bit_bram/SinglePortBootBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_sp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BC 32 $(IOCPDIR)/iocp.bin 0 $*.bin 2048 /tmp/zpu_work.tmp > IOCP_zOS_SinglePortBootBRAM.vhd
|
||||
@rm -f /tmp/zpu_work.tmp
|
||||
@cp IOCP_zOS_SinglePortBootBRAM.vhd $(RTL_DIR)/
|
||||
@rm IOCP_zOS_DualPortBootBRAM.vhd IOCP_zOS_DualPort3264BootBRAM.vhd IOCP_zOS_SinglePortBootBRAM.vhd
|
||||
@echo "IOCP_zOS_DualPortBootBRAM.vhd, IOCP_zOS_DualPort3264BootBRAM.vhd and IOCP_zOS_SinglePortBootBRAM updated."
|
||||
@echo ""
|
||||
|
||||
# Put the app code into a seperate BRAM instantiation file, used when a 2nd block of App BRAM is created seperate to the boot BRAM and requires to be preloaded.
|
||||
%_APPRAM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/byteaddr_sp_32bit_bram/SinglePortBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_sp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BA 32 $*.bin /tmp/zpu_work.tmp 0 > zOS_SinglePortBRAM.vhd
|
||||
@rm -f /tmp/zpu_work.tmp
|
||||
@cp zOS_SinglePortBRAM.vhd $(RTL_DIR)/
|
||||
@sed 's/zpu_soc_pkg/softZPU_pkg/' > $(RTL_DIR)/TZSW_SinglePortBRAM.vhd < zOS_SinglePortBRAM.vhd
|
||||
@rm zOS_SinglePortBRAM.vhd
|
||||
@echo "zOS_SinglePortBRAM updated."
|
||||
|
||||
%_COMBINEDAPPRAM.vhd: %.bin $(ROMGEN)
|
||||
@sed 's/byteaddr_sp_32bit_bram/SinglePortBRAM/' >/tmp/zpu_work.tmp <$(RTL_DIR)/byteaddr_sp_32bit_bram_tmpl.vhd
|
||||
@$(ROMGEN) BA 32 $*.bin /tmp/zpu_work.tmp 0 > IOCP_zOS_SinglePortBRAM.vhd
|
||||
@rm -f /tmp/zpu_work.tmp
|
||||
@cp IOCP_zOS_SinglePortBRAM.vhd $(RTL_DIR)/
|
||||
@rm IOCP_zOS_SinglePortBRAM.vhd
|
||||
@echo "IOCP_zOS_SinglePortBRAM updated."
|
||||
|
||||
# Link - this produces an ELF binary.
|
||||
#$(MAIN_PRJ_TO_BOOT).elf: $(ROMSTARTUP_OBJ) $(OBJS)
|
||||
$(MAIN_PRJ_TO_BOOT).elf: $(OBJS)
|
||||
$(LD) $(LFLAGS) -T $(LINKMAPBOOTSTANDALONE) -o $@ $+ $(LIBS)
|
||||
|
||||
$(MAIN_PRJ_IN_BOOT).elf: $(RAMSTARTUP_OBJ) $(OBJS)
|
||||
$(LD) $(LFLAGS) -T $(LINKMAPBOOTIOCP) -o $@ $+ $(LIBS)
|
||||
|
||||
$(MAIN_PRJ_TINY_BOOT).elf: $(RAMSTARTUP_OBJ) $(OBJS)
|
||||
$(LD) $(LFLAGS) -T $(LINKMAPBOOTTINYIOCP) -o $@ $+ $(LIBS)
|
||||
|
||||
$(MAIN_PRJ_RAM).elf: $(RAMSTARTUP_OBJ) $(OBJS)
|
||||
$(LD) $(LFLAGS) -T $(LINKMAPRAM) -o $@ $+ $(LIBS)
|
||||
|
||||
$(BUILD_DIR)/%.o: %.c Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CC) $(CFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: %.cpp Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CXX) $(CFLAGS) $(CXXFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/src/%.o: %.cpp Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CXX) $(CFLAGS) $(CXXFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: $(COMMON_DIR)/%.c Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CC) $(CFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: $(DHRY_DIR)/%.c Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CC) $(CFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
#$(BUILD_DIR)/%.o: $(CORE_DIR)/%.c Makefile
|
||||
# @mkdir -p "$(dir $@)"
|
||||
# $(CC) $(CFLAGS) $(OFLAGS) $(FLAGS_STR) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: $(FATFS_DIR)/%.c Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CC) $(CFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: $(PFS_DIR)/%.c Makefile
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(CC) $(CFLAGS) $(OFLAGS) -o $@ -c $<
|
||||
|
||||
$(BUILD_DIR)/%.o: %.s
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(AS) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
|
||||
@mkdir -p "$(dir $@)"
|
||||
$(AS) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(BUILD_DIR):
|
||||
mkdir -p $(BUILD_DIR)
|
||||
|
||||
# compiler generated dependency info
|
||||
-include $(OBJS:.o=.d)
|
||||
@@ -26,6 +26,7 @@
|
||||
// the MZ-800. Bug found which was introduced in December where the
|
||||
// Z80 direction wasnt always set correctly resulting in some strange
|
||||
// and hard to debug behaviour.
|
||||
// May 2021 - Preparations to add the M68000 architecture.
|
||||
//
|
||||
// Notes: See Makefile to enable/disable conditional components
|
||||
// USELOADB - The Byte write command is implemented in hw/sw so use it.
|
||||
@@ -65,7 +66,7 @@
|
||||
#include <../libraries/include/stdmisc.h>
|
||||
#include <TeensyThreads.h>
|
||||
|
||||
#else // __ZPU__
|
||||
#elif defined __ZPU__
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
@@ -82,12 +83,21 @@
|
||||
// void *sys_realloc(void *, size_t); // Reallocate a block of memory managed by the OS.
|
||||
// void *sys_calloc(size_t, size_t); // Allocate and zero a block of memory managed by the OS.
|
||||
// void sys_free(void *); // Free memory managed by the OS.
|
||||
#elif defined __M68K__
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <../libraries/include/stdmisc.h>
|
||||
#include "m68k_soc.h"
|
||||
#endif
|
||||
|
||||
#include "interrupts.h"
|
||||
#include "ff.h" /* Declarations of FatFs API */
|
||||
#include "diskio.h"
|
||||
#if defined __K64F__ || defined __ZPU__
|
||||
#include <fcntl.h>
|
||||
#endif
|
||||
#include <sys/stat.h>
|
||||
#include "utils.h"
|
||||
#include "readline.h"
|
||||
@@ -110,7 +120,7 @@
|
||||
#endif
|
||||
|
||||
// Version info.
|
||||
#define VERSION "v1.2"
|
||||
#define VERSION "v1.2a"
|
||||
#define VERSION_DATE "17/04/2021"
|
||||
#define PROGRAM_NAME "zOS"
|
||||
|
||||
@@ -245,8 +255,10 @@ uint8_t getCommandLine(char *buf, uint8_t bufSize)
|
||||
#if defined BUILTIN_READLINE
|
||||
#if defined __ZPU__
|
||||
readline((uint8_t *)buf, bufSize, HISTORY_FILE_ZPU);
|
||||
#else
|
||||
#elif defined __K64F__
|
||||
readline((uint8_t *)buf, bufSize, HISTORY_FILE_K64F);
|
||||
#elif defined __M68K__
|
||||
readline((uint8_t *)buf, bufSize, HISTORY_FILE_M68K);
|
||||
#endif
|
||||
#else
|
||||
ptr = buf;
|
||||
@@ -491,8 +503,15 @@ int cmdProcessor(void)
|
||||
else if(cfgSoC.implFRAMNV) { p1 = cfgSoC.addrFRAMNV; }
|
||||
else if(cfgSoC.implFRAMNVC) { p1 = cfgSoC.addrFRAMNVC; }
|
||||
else { p1 = cfgSoC.stackStartAddr - 512; }
|
||||
#elif defined __M68K__
|
||||
if(cfgSoC.implInsnBRAM) { p1 = cfgSoC.addrInsnBRAM; }
|
||||
else if(cfgSoC.implBRAM) { p1 = cfgSoC.addrBRAM; }
|
||||
else if(cfgSoC.implRAM) { p1 = cfgSoC.addrRAM; }
|
||||
else if(cfgSoC.implSDRAM) { p1 = cfgSoC.addrSDRAM; }
|
||||
else if(cfgSoC.implWBSDRAM) { p1 = cfgSoC.addrWBSDRAM; }
|
||||
else { p1 = cfgSoC.stackStartAddr - 512; }
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
}
|
||||
if (!xatoi(&ptr, &p2))
|
||||
@@ -510,8 +529,15 @@ int cmdProcessor(void)
|
||||
else if(cfgSoC.implFRAMNV) { p2 = cfgSoC.sizeFRAMNV; }
|
||||
else if(cfgSoC.implFRAMNVC) { p2 = cfgSoC.sizeFRAMNVC; }
|
||||
else { p2 = cfgSoC.stackStartAddr + 8; }
|
||||
#elif defined __M68K__
|
||||
if(cfgSoC.implInsnBRAM) { p2 = cfgSoC.sizeInsnBRAM; }
|
||||
else if(cfgSoC.implBRAM) { p2 = cfgSoC.sizeBRAM; }
|
||||
else if(cfgSoC.implRAM) { p2 = cfgSoC.sizeRAM; }
|
||||
else if(cfgSoC.implSDRAM) { p2 = cfgSoC.sizeSDRAM; }
|
||||
else if(cfgSoC.implWBSDRAM) { p2 = cfgSoC.sizeWBSDRAM; }
|
||||
else { p2 = cfgSoC.stackStartAddr + 8; }
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
}
|
||||
if (!xatoi(&ptr, &p3) || (p3 != 8 && p3 != 16 && p3 != 32))
|
||||
@@ -630,8 +656,15 @@ int cmdProcessor(void)
|
||||
else if(cfgSoC.implFRAMNV) { p1 = cfgSoC.addrFRAMNV; }
|
||||
else if(cfgSoC.implFRAMNVC) { p1 = cfgSoC.addrFRAMNVC; }
|
||||
else { p1 = cfgSoC.stackStartAddr - 512; }
|
||||
#elif defined __M68K__
|
||||
if(cfgSoC.implInsnBRAM) { p1 = cfgSoC.addrInsnBRAM; }
|
||||
else if(cfgSoC.implBRAM) { p1 = cfgSoC.addrBRAM; }
|
||||
else if(cfgSoC.implRAM) { p1 = cfgSoC.addrRAM; }
|
||||
else if(cfgSoC.implSDRAM) { p1 = cfgSoC.addrSDRAM; }
|
||||
else if(cfgSoC.implWBSDRAM) { p1 = cfgSoC.addrWBSDRAM; }
|
||||
else { p1 = cfgSoC.stackStartAddr - 512; }
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
}
|
||||
if (!xatoi(&ptr, &p2))
|
||||
@@ -649,8 +682,15 @@ int cmdProcessor(void)
|
||||
else if(cfgSoC.implFRAMNV) { p2 = cfgSoC.sizeFRAMNV; }
|
||||
else if(cfgSoC.implFRAMNVC) { p2 = cfgSoC.sizeFRAMNVC; }
|
||||
else { p2 = cfgSoC.stackStartAddr + 8; }
|
||||
#elif defined __M68K__
|
||||
if(cfgSoC.implInsnBRAM) { p2 = cfgSoC.sizeInsnBRAM; }
|
||||
else if(cfgSoC.implBRAM) { p2 = cfgSoC.sizeBRAM; }
|
||||
else if(cfgSoC.implRAM) { p2 = cfgSoC.sizeRAM; }
|
||||
else if(cfgSoC.implSDRAM) { p2 = cfgSoC.sizeSDRAM; }
|
||||
else if(cfgSoC.implWBSDRAM) { p2 = cfgSoC.sizeWBSDRAM; }
|
||||
else { p2 = cfgSoC.stackStartAddr + 8; }
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
}
|
||||
if (!xatoi(&ptr, &p3))
|
||||
@@ -735,10 +775,12 @@ int cmdProcessor(void)
|
||||
showSoCConfig();
|
||||
break;
|
||||
|
||||
#if defined __ZPU__ || defined __K64F__
|
||||
// Test point - add code here when a test is needed on a kernel element then invoke after boot.
|
||||
case CMD_MISC_TEST:
|
||||
testRoutine();
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if defined(__SD_CARD__)
|
||||
// CMD_FS_CAT <name> - cat/output file
|
||||
@@ -874,7 +916,7 @@ int cmdProcessor(void)
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
// Locals.
|
||||
#if defined __ZPU__
|
||||
#if defined __ZPU__ || defined __M68K__
|
||||
FILE osIO;
|
||||
#endif
|
||||
|
||||
@@ -919,9 +961,12 @@ int main(int argc, char **argv)
|
||||
// Initialise and clear screen.
|
||||
mzInit();
|
||||
|
||||
#else
|
||||
#elif defined __ZPU__
|
||||
fdev_setup_stream(&osIO, uart_putchar, uart_getchar, _FDEV_SETUP_RW);
|
||||
stdout = stdin = stderr = &osIO;
|
||||
|
||||
#elif defined __M68K__
|
||||
|
||||
#endif
|
||||
|
||||
// Setup the configuration using the SoC configuration register if implemented otherwise the compiled internals.
|
||||
|
||||
@@ -71,11 +71,14 @@ extern "C" {
|
||||
#define APP_CMD_EXTENSION "ZPU"
|
||||
#elif defined __K64F__
|
||||
#define APP_CMD_EXTENSION "K64"
|
||||
#elif defined __M68K__
|
||||
#define APP_CMD_EXTENSION "M68"
|
||||
#else
|
||||
#error "Target CPU not defined, use __ZPU__ or __K64F__"
|
||||
#error "Target CPU not defined, use __ZPU__, __K64F__ or __M68K__"
|
||||
#endif
|
||||
#define HISTORY_FILE_ZPU "zOS_zpu.hst"
|
||||
#define HISTORY_FILE_K64F "zOS_k64f.hst"
|
||||
#define HISTORY_FILE_M68K "zOS_m68k.hst"
|
||||
#define AUTOEXEC_FILE "autoexec.bat"
|
||||
#define APP_CMD_LOAD_ADDR OS_APPADDR
|
||||
#define APP_CMD_EXEC_ADDR OS_APPADDR
|
||||
|
||||
Reference in New Issue
Block a user