sunxi: Add a33 dram init code
Based on Allwinner dram init code from the a33 bsp: https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c Initial u-boot port by Vishnu Patekar, major cleanup / rewrite by Hans de Goede. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Vishnu Patekar
committed by
Hans de Goede
Hans de Goede
parent
886a7b45ef
commit
ffc0ae0c70
363
arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
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363
arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c
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@@ -0,0 +1,363 @@
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/*
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* Sun8i a33 platform dram controller init.
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/prcm.h>
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/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
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#define DRAM_CLK_MUL 2
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#define DRAM_CLK_DIV 4
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#define DRAM_SIGMA_DELTA_ENABLE 1
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#define DRAM_ODT_EN 0
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struct dram_para {
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u8 cs1;
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u8 seq;
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u8 bank;
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u8 rank;
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u8 rows;
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u8 bus_width;
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u16 page_size;
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};
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static void mctl_set_cr(struct dram_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
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MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
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(para->seq ? MCTL_CR_SEQUENCE : 0) |
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((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
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MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
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MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
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&mctl_com->cr);
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}
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static void auto_detect_dram_size(struct dram_para *para)
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{
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u8 orig_rank = para->rank;
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int rows, columns;
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/* Row detect */
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para->page_size = 512;
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para->seq = 1;
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para->rows = 16;
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para->rank = 1;
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mctl_set_cr(para);
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for (rows = 11 ; rows < 16 ; rows++) {
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if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
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break;
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}
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/* Column (page size) detect */
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para->rows = 11;
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para->page_size = 8192;
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mctl_set_cr(para);
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for (columns = 9 ; columns < 13 ; columns++) {
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if (mctl_mem_matches(1 << columns))
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break;
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}
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para->seq = 0;
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para->rank = orig_rank;
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para->rows = rows;
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para->page_size = 1 << columns;
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mctl_set_cr(para);
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}
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq =
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CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
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return (ctrl_freq * nanoseconds + 999) / 1000;
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}
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static void auto_set_timing_para(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u32 reg_val;
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u8 tccd = 2;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(10), 4);
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u8 trcd = ns_to_t(15);
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u8 trc = ns_to_t(53);
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u8 txp = max(ns_to_t(8), 3);
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u8 twtr = max(ns_to_t(8), 4);
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u8 trtp = max(ns_to_t(8), 4);
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u8 twr = max(ns_to_t(15), 3);
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u8 trp = ns_to_t(15);
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u8 tras = ns_to_t(38);
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u16 trefi = ns_to_t(7800) / 32;
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u16 trfc = ns_to_t(350);
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/* Fixed timing parameters */
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u8 tmrw = 0;
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u8 tmrd = 4;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 4;
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u8 trasmax = 24;
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u8 tcl = 6; /* CL 12 */
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u8 tcwl = 4; /* CWL 8 */
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u8 t_rdata_en = 4;
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u8 wr_latency = 2;
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
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/* Set work mode register */
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mctl_set_cr(para);
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/* Set mode register */
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writel(MCTL_MR0, &mctl_ctl->mr0);
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writel(MCTL_MR1, &mctl_ctl->mr1);
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writel(MCTL_MR2, &mctl_ctl->mr2);
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writel(MCTL_MR3, &mctl_ctl->mr3);
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/* Set dram timing */
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reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
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writel(reg_val, &mctl_ctl->dramtmg0);
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reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
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writel(reg_val, &mctl_ctl->dramtmg1);
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reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
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writel(reg_val, &mctl_ctl->dramtmg2);
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reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
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writel(reg_val, &mctl_ctl->dramtmg3);
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reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
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writel(reg_val, &mctl_ctl->dramtmg4);
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reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
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writel(reg_val, &mctl_ctl->dramtmg5);
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/* Set two rank timing and exit self-refresh timing */
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reg_val = readl(&mctl_ctl->dramtmg8);
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reg_val &= ~(0xff << 8);
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reg_val &= ~(0xff << 0);
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reg_val |= (0x33 << 8);
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reg_val |= (0x8 << 0);
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writel(reg_val, &mctl_ctl->dramtmg8);
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/* Set phy interface time */
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reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
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| (wr_latency << 0);
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/* PHY interface write latency and read latency configure */
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writel(reg_val, &mctl_ctl->pitmg0);
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/* Set phy time PTR0-2 use default */
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writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
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writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
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/* Set refresh timing */
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reg_val = (trefi << 16) | (trfc << 0);
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writel(reg_val, &mctl_ctl->rfshtmg);
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}
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static void mctl_set_pir(u32 val)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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writel(val, &mctl_ctl->pir);
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mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
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}
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static void mctl_data_train_cfg(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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if (para->rank == 2)
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clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
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else
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clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
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}
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static int mctl_train_dram(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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mctl_data_train_cfg(para);
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mctl_set_pir(0x1f3);
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return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
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}
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static int mctl_channel_init(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
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u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
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auto_set_timing_para(para);
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/* Disable dram VTC */
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clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
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/* Set ODT */
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if ((CONFIG_DRAM_CLK > 400) && DRAM_ODT_EN) {
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setbits_le32(DXnGCR0(0), 0x3 << 9);
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setbits_le32(DXnGCR0(1), 0x3 << 9);
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} else {
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clrbits_le32(DXnGCR0(0), 0x3 << 9);
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clrbits_le32(DXnGCR0(1), 0x3 << 9);
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}
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/* set PLL configuration */
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if (CONFIG_DRAM_CLK >= 480)
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setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
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else
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setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
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/* Auto detect dram config, set 2 rank and 16bit bus-width */
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para->cs1 = 0;
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para->rank = 2;
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para->bus_width = 16;
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mctl_set_cr(para);
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/* Open DQS gating */
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clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
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clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
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mctl_data_train_cfg(para);
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/* ZQ calibration */
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writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
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/* CA calibration */
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mctl_set_pir(0x00000003);
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/* More ZQ calibration */
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writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
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writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
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/* DQS gate training */
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if (mctl_train_dram(para) != 0) {
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low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
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high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
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if (low_data_lines_status == 0x3)
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return -EIO;
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/* DRAM has only one rank */
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para->rank = 1;
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mctl_set_cr(para);
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if (low_data_lines_status == high_data_lines_status)
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goto done; /* 16 bit bus, 1 rank */
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if (!(low_data_lines_status & high_data_lines_status)) {
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/* Retry 16 bit bus-width with CS1 set */
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para->cs1 = 1;
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mctl_set_cr(para);
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if (mctl_train_dram(para) == 0)
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goto done;
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}
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/* Try 8 bit bus-width */
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writel(0x0, DXnGCR0(1)); /* Disable high DQ */
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para->cs1 = 0;
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para->bus_width = 8;
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mctl_set_cr(para);
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if (mctl_train_dram(para) != 0)
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return -EIO;
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}
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done:
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/* Check the dramc status */
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mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
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/* Close DQS gating */
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setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
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/* Enable master access */
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writel(0xffffffff, &mctl_com->maer);
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return 0;
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}
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static void mctl_sys_init(struct dram_para *para)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
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CCM_DRAMPLL_CFG_SRC_PLL11);
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clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
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DRAM_SIGMA_DELTA_ENABLE);
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clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
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CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
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CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
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mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
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setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
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/* Set dram master access priority */
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writel(0x0, &mctl_com->mapr);
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writel(0x0f802f01, &mctl_ctl->sched);
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writel(0x0000400f, &mctl_ctl->clken); /* normal */
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udelay(250);
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}
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unsigned long sunxi_dram_init(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct dram_para para = {
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.cs1 = 0,
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.bank = 1,
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.rank = 1,
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.rows = 15,
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.bus_width = 16,
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.page_size = 2048,
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};
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mctl_sys_init(¶);
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if (mctl_channel_init(¶) != 0)
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return 0;
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auto_detect_dram_size(¶);
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/* Enable master software clk */
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writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
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/* Set DRAM ODT MAP */
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if (para.rank == 2)
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writel(0x00000303, &mctl_ctl->odtmap);
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else
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writel(0x00000201, &mctl_ctl->odtmap);
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return para.page_size * (para.bus_width / 8) *
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(1 << (para.bank + para.rank + para.rows));
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}
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@@ -20,6 +20,8 @@
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#include <asm/arch/dram_sun6i.h>
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#elif defined(CONFIG_MACH_SUN8I_A23)
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#include <asm/arch/dram_sun8i_a23.h>
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#elif defined(CONFIG_MACH_SUN8I_A33)
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#include <asm/arch/dram_sun8i_a33.h>
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#else
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#include <asm/arch/dram_sun4i.h>
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#endif
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179
arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
Normal file
179
arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
Normal file
@@ -0,0 +1,179 @@
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/*
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* Sun8i platform dram controller register and constant defines
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_SUN8I_A33_H
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#define _SUNXI_DRAM_SUN8I_A33_H
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x00 */
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u32 ccr; /* 0x04 controller configuration register */
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u32 dbgcr; /* 0x08 */
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u8 res0[0x4]; /* 0x0c */
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u32 mcr0_0; /* 0x10 */
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u32 mcr1_0; /* 0x14 */
|
||||
u32 mcr0_1; /* 0x18 */
|
||||
u32 mcr1_1; /* 0x1c */
|
||||
u32 mcr0_2; /* 0x20 */
|
||||
u32 mcr1_2; /* 0x24 */
|
||||
u32 mcr0_3; /* 0x28 */
|
||||
u32 mcr1_3; /* 0x2c */
|
||||
u32 mcr0_4; /* 0x30 */
|
||||
u32 mcr1_4; /* 0x34 */
|
||||
u32 mcr0_5; /* 0x38 */
|
||||
u32 mcr1_5; /* 0x3c */
|
||||
u32 mcr0_6; /* 0x40 */
|
||||
u32 mcr1_6; /* 0x44 */
|
||||
u32 mcr0_7; /* 0x48 */
|
||||
u32 mcr1_7; /* 0x4c */
|
||||
u32 mcr0_8; /* 0x50 */
|
||||
u32 mcr1_8; /* 0x54 */
|
||||
u32 mcr0_9; /* 0x58 */
|
||||
u32 mcr1_9; /* 0x5c */
|
||||
u32 mcr0_10; /* 0x60 */
|
||||
u32 mcr1_10; /* 0x64 */
|
||||
u32 mcr0_11; /* 0x68 */
|
||||
u32 mcr1_11; /* 0x6c */
|
||||
u32 mcr0_12; /* 0x70 */
|
||||
u32 mcr1_12; /* 0x74 */
|
||||
u32 mcr0_13; /* 0x78 */
|
||||
u32 mcr1_13; /* 0x7c */
|
||||
u32 mcr0_14; /* 0x80 */
|
||||
u32 mcr1_14; /* 0x84 */
|
||||
u32 mcr0_15; /* 0x88 */
|
||||
u32 mcr1_15; /* 0x8c */
|
||||
u32 bwcr; /* 0x90 */
|
||||
u32 maer; /* 0x94 */
|
||||
u32 mapr; /* 0x98 */
|
||||
u32 mcgcr; /* 0x9c */
|
||||
u32 bwctr; /* 0xa0 */
|
||||
u8 res2[0x8]; /* 0xa4 */
|
||||
u32 swoffr; /* 0xac */
|
||||
u8 res3[0x10]; /* 0xb0 */
|
||||
u32 swonr; /* 0xc0 */
|
||||
u8 res4[0x3c]; /* 0xc4 */
|
||||
u32 mdfscr; /* 0x100 */
|
||||
u32 mdfsmer; /* 0x104 */
|
||||
};
|
||||
|
||||
struct sunxi_mctl_ctl_reg {
|
||||
u32 pir; /* 0x00 */
|
||||
u32 pwrctl; /* 0x04 */
|
||||
u32 mrctrl0; /* 0x08 */
|
||||
u32 clken; /* 0x0c */
|
||||
u32 pgsr0; /* 0x10 */
|
||||
u32 pgsr1; /* 0x14 */
|
||||
u32 statr; /* 0x18 */
|
||||
u8 res1[0x14]; /* 0x1c */
|
||||
u32 mr0; /* 0x30 */
|
||||
u32 mr1; /* 0x34 */
|
||||
u32 mr2; /* 0x38 */
|
||||
u32 mr3; /* 0x3c */
|
||||
u32 pllgcr; /* 0x40 */
|
||||
u32 ptr0; /* 0x44 */
|
||||
u32 ptr1; /* 0x48 */
|
||||
u32 ptr2; /* 0x4c */
|
||||
u32 ptr3; /* 0x50 */
|
||||
u32 ptr4; /* 0x54 */
|
||||
u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
|
||||
u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
|
||||
u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
|
||||
u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
|
||||
u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
|
||||
u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
|
||||
u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
|
||||
u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
|
||||
u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
|
||||
u32 odtcfg; /* 0x7c */
|
||||
u32 pitmg0; /* 0x80 */
|
||||
u32 pitmg1; /* 0x84 */
|
||||
u8 res2[0x4]; /* 0x88 */
|
||||
u32 rfshctl0; /* 0x8c */
|
||||
u32 rfshtmg; /* 0x90 */
|
||||
u32 rfshctl1; /* 0x94 */
|
||||
u32 pwrtmg; /* 0x98 */
|
||||
u8 res3[0x20]; /* 0x9c */
|
||||
u32 dqsgmr; /* 0xbc */
|
||||
u32 dtcr; /* 0xc0 */
|
||||
u32 dtar0; /* 0xc4 */
|
||||
u32 dtar1; /* 0xc8 */
|
||||
u32 dtar2; /* 0xcc */
|
||||
u32 dtar3; /* 0xd0 */
|
||||
u32 dtdr0; /* 0xd4 */
|
||||
u32 dtdr1; /* 0xd8 */
|
||||
u32 dtmr0; /* 0xdc */
|
||||
u32 dtmr1; /* 0xe0 */
|
||||
u32 dtbmr; /* 0xe4 */
|
||||
u32 catr0; /* 0xe8 */
|
||||
u32 catr1; /* 0xec */
|
||||
u32 dtedr0; /* 0xf0 */
|
||||
u32 dtedr1; /* 0xf4 */
|
||||
u8 res4[0x8]; /* 0xf8 */
|
||||
u32 pgcr0; /* 0x100 */
|
||||
u32 pgcr1; /* 0x104 */
|
||||
u32 pgcr2; /* 0x108 */
|
||||
u8 res5[0x4]; /* 0x10c */
|
||||
u32 iovcr0; /* 0x110 */
|
||||
u32 iovcr1; /* 0x114 */
|
||||
u32 dqsdr; /* 0x118 */
|
||||
u32 dxccr; /* 0x11c */
|
||||
u32 odtmap; /* 0x120 */
|
||||
u32 zqctl0; /* 0x124 */
|
||||
u32 zqctl1; /* 0x128 */
|
||||
u8 res6[0x14]; /* 0x12c */
|
||||
u32 zqcr0; /* 0x140 zq control register 0 */
|
||||
u32 zqcr1; /* 0x144 zq control register 1 */
|
||||
u32 zqcr2; /* 0x148 zq control register 2 */
|
||||
u32 zqsr0; /* 0x14c zq status register 0 */
|
||||
u32 zqsr1; /* 0x150 zq status register 1 */
|
||||
u8 res7[0x6c]; /* 0x154 */
|
||||
u32 sched; /* 0x1c0 */
|
||||
u32 perfhpr0; /* 0x1c4 */
|
||||
u32 perfhpr1; /* 0x1c8 */
|
||||
u32 perflpr0; /* 0x1cc */
|
||||
u32 perflpr1; /* 0x1d0 */
|
||||
u32 perfwr0; /* 0x1d4 */
|
||||
u32 perfwr1; /* 0x1d8 */
|
||||
};
|
||||
|
||||
#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
|
||||
#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
|
||||
#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
|
||||
#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
|
||||
#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
|
||||
|
||||
/*
|
||||
* DRAM common (sunxi_mctl_com_reg) register constants.
|
||||
*/
|
||||
#define MCTL_CR_RANK_MASK (3 << 0)
|
||||
#define MCTL_CR_RANK(x) (((x) - 1) << 0)
|
||||
#define MCTL_CR_BANK_MASK (3 << 2)
|
||||
#define MCTL_CR_BANK(x) ((x) << 2)
|
||||
#define MCTL_CR_ROW_MASK (0xf << 4)
|
||||
#define MCTL_CR_ROW(x) (((x) - 1) << 4)
|
||||
#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
|
||||
#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
|
||||
#define MCTL_CR_BUSW_MASK (7 << 12)
|
||||
#define MCTL_CR_BUSW8 (0 << 12)
|
||||
#define MCTL_CR_BUSW16 (1 << 12)
|
||||
#define MCTL_CR_SEQUENCE (1 << 15)
|
||||
#define MCTL_CR_DDR3 (3 << 16)
|
||||
#define MCTL_CR_CHANNEL_MASK (1 << 19)
|
||||
#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
|
||||
#define MCTL_CR_UNKNOWN (0x4 << 20)
|
||||
#define MCTL_CR_CS1_CONTROL(x) ((x) << 24)
|
||||
|
||||
/* DRAM control (sunxi_mctl_ctl_reg) register constants */
|
||||
#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */
|
||||
#define MCTL_MR1 0x40
|
||||
#define MCTL_MR2 0x18 /* CWL=8 */
|
||||
#define MCTL_MR3 0x0
|
||||
|
||||
#endif /* _SUNXI_DRAM_SUN8I_A33_H */
|
||||
Reference in New Issue
Block a user