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clk: imx8mm: Add SPI clocks

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Add the clocks for the ECSPI controllers. This is ported from
Linux v5.13-rc4.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
This commit is contained in:
Frieder Schrempf
2021-06-07 14:36:43 +02:00
committed by Stefano Babic
parent 2a79775069
commit ef62fff269
1 changed files with 21 additions and 0 deletions
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21
drivers/clk/imx/clk-imx8mm.c
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@@ -131,6 +131,15 @@ static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "
static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static ulong imx8mm_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -393,7 +402,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
clk_dm(IMX8MM_CLK_USB_PHY_REF,
imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MM_CLK_ECSPI1,
imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MM_CLK_ECSPI2,
imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MM_CLK_ECSPI3,
imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,