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net: gem: Enable ethernet rx clock for versal

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Enable rx clock along with tx clock for versal platform. Use compatible
data to enable/disable clocks in the driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
T Karthik Reddy
2021-02-03 03:10:48 -07:00
committed by Michal Simek
parent 8faa7913a4
commit ea4d4cb39a
1 changed files with 27 additions and 6 deletions
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33
drivers/net/zynq_gem.c
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@@ -129,6 +129,8 @@
#define ZYNQ_GEM_FREQUENCY_100 25000000UL
#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
#define RXCLK_EN BIT(0)
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* 0x0 - Network Control reg */
@@ -205,10 +207,12 @@ struct zynq_gem_priv {
struct phy_device *phydev;
ofnode phy_of_node;
struct mii_dev *bus;
struct clk clk;
struct clk rx_clk;
struct clk tx_clk;
u32 max_speed;
bool int_pcs;
bool dma_64bit;
u32 clk_en_info;
};
static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -476,18 +480,25 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
ret = clk_set_rate(&priv->clk, clk_rate);
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");
return ret;
}
ret = clk_enable(&priv->clk);
ret = clk_enable(&priv->tx_clk);
if (ret) {
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
if (priv->clk_en_info & RXCLK_EN) {
ret = clk_enable(&priv->rx_clk);
if (ret) {
dev_err(dev, "failed to enable rx clock\n");
return ret;
}
}
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -694,12 +705,20 @@ static int zynq_gem_probe(struct udevice *dev)
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk);
if (ret < 0) {
dev_err(dev, "failed to get clock\n");
dev_err(dev, "failed to get tx_clock\n");
goto err1;
}
if (priv->clk_en_info & RXCLK_EN) {
ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk);
if (ret < 0) {
dev_err(dev, "failed to get rx_clock\n");
goto err1;
}
}
priv->bus = mdio_alloc();
priv->bus->read = zynq_gem_miiphy_read;
priv->bus->write = zynq_gem_miiphy_write;
@@ -794,11 +813,13 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
(ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
phy_string_for_interface(priv->interface));
priv->clk_en_info = dev_get_driver_data(dev);
return 0;
}
static const struct udevice_id zynq_gem_ids[] = {
{ .compatible = "cdns,versal-gem" },
{ .compatible = "cdns,versal-gem", .data = RXCLK_EN },
{ .compatible = "cdns,zynqmp-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },