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sunxi: Fix H616 DRAM read calibration for dual rank

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Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)

Fix it.

Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Jernej Skrabec
2022-01-29 16:58:43 +01:00
committed by Andre Przywara
parent 18a5927698
commit e97943b732
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-sunxi/dram_sun50i_h616.c
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@@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
}
}
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
}
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);