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board: gateworks: venice: add imx8mm-gw7901 support

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The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
 - i.MX8M Mini SoC
 - LPDDR4 DRAM
 - eMMC FLASH
 - SPI FRAM
 - Gateworks System Controller (GSC)
 - Atmel ATECC Crypto Authentication
 - USB 2.0
 - Microchip GbE Switch
 - Multiple multi-protocol RS232/RS485/RS422 Serial ports
 - onboard 802.11ac WiFi / BT
 - microSD socket
 - miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets
 - Wide range DC power input
 - 802.3at PoE

To add support for this board:
 - add dts from Linux (accepted for v5.14)
 - add SPL PMIC config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
2021-06-30 16:50:02 -07:00
committed by Stefano Babic
parent 6b86554865
commit c9f7ef37f9
5 changed files with 1193 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
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@@ -865,6 +865,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-venice-gw7901.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \

117
arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi Normal file
View File

@@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Gateworks Corporation
*/
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};

1020
arch/arm/dts/imx8mm-venice-gw7901.dts Normal file
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File diff suppressed because it is too large Load Diff

55
board/gateworks/venice/spl.c
View File

@@ -26,6 +26,7 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <power/bd71837.h>
#include <power/mp5416.h>
#include "gsc.h"
@@ -88,8 +89,23 @@ int board_early_init_f(void)
* Note that we can not use pmic dm drivers here as we have a generic
* venice dt that does not have board-specific pmic's defined.
*
* Instead we must use dm_i2c.
* Instead we must use dm_i2c so we a helpers to give us
* clrsetbit functions we would otherwise have if we could use PMIC dm
* drivers.
*/
static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
{
int ret;
u8 val;
ret = dm_i2c_read(dev, reg, &val, 1);
if (ret)
return ret;
val = (val & ~clr) | set;
return dm_i2c_write(dev, reg, &val, 1);
}
static int power_init_board(void)
{
const char *model = gsc_get_model();
@@ -117,6 +133,43 @@ static int power_init_board(void)
BIT(7) | MP5416_VSET_SW3_SVAL(920000));
}
else if (!strncmp(model, "GW7901", 6)) {
ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a30000", &bus);
if (ret) {
printf("PMIC : failed I2C2 probe: %d\n", ret);
return ret;
}
ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
if (ret) {
printf("PMIC : failed probe: %d\n", ret);
return ret;
}
puts("PMIC : BD71847\n");
/* unlock the PMIC regs */
dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
/* set switchers to forced PWM mode */
dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
/* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
/* increase VDD_SOC to 0.85v before first DRAM access */
dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
/* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
/* Lock the PMIC regs */
dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
}
return 0;
}

2
configs/imx8mm_venice_defconfig
View File

@@ -58,7 +58,7 @@ CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x"
CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y